Friday, May 22, 2015

Imec 5 day training in Nanoscale CMOS process technology


Imec offers a 5 day training in Nanoscale CMOS process technology 8-12 June in Leuven, Belgium. Here is the full program and for ALD guys there is especially two sessions that must be of interest (below) plus courses  in interconnects, memory and emerging memory.


Material deposition 

Essentially, manufacturing of semiconductor devices is based on the deposition and removal of layers/materials, with intermediate lithographic patterning steps. This lecture gives an overview of the most prevalent layer deposition processes as used in manufacturing of semiconductor circuits. Basically, most of these processes are based on the use of chemical precursors and are therefore called ‘Chemical Vapor Deposition’ processes. Next to the generic thermal and plasma-enhanced CVD processes, there are more specific types of CVD processes such as epitaxy used for the growth of mono-crystalline semiconductor layer structures and Atomic Layer Deposition (ALD) used for the deposition of various materials. A powerful technique based on atomic precursors (Physical Vapor Deposition, PVD) is Molecular Beam Epitaxy, which is mainly used in R&D due to its high flexibility.

By Roger Loo 

Gate stack 

The properties of silicon dioxide are seen as key to the success of the CMOS indus- try due to the high electrical quality of the Si/SiO2 interface, its favorable material properties and reliability. The continued reduction of the physical oxide thickness demanded by the scaling requirements ultimately renders the material unfit for further scaling as it would increase the gate leakage current prohibitively due to fundamental quantum mechanical tunneling. Materials with a higher dielectric con- stant (k-value) maintain channel control for larger thicknesses and reduce the gate leakage current. The introduction of high-k metal gate technology, which resolved the gate leakage issue in 45 nm production MOSFETs is one of the largest recent innovations in CMOS technology. This lecture discusses the properties of SiO2 lay- ers and introduces the high-k and metal gate technology used for advanced CMOS devices. 

By Lars-Ake Ragnarsson