AlixLabs to Demonstrate APS™ on 300-millimeter UMC wafers at the 2025 CMC Conference

Atomic Layer Etching Pitch Splitting (APS) proven on more industry-leading wafers, doubling fin density and proving flexibility without EUV.

Austin, TX, USA/Stockholm, Sweden – April 10th, 2025 – AlixLabs AB, a Swedish semiconductor startup specializing in Atomic Layer Etching (ALE), today demonstrates the latest in its line of groundbreaking development in advanced chip fabrication unveiling additional research into its novel semiconductor manufacturing process known as APS™ (Atomic Layer Etching Pitch Splitting) capable of doubling fin density while introducing the unprecedented flexibility to vary pitch and critical dimensions within the same wafer area.

Proven on 300-millimeter wafers provided by United Microelectronics Corporation (UMC), the APS™ technology successfully halved pitch compared to current industry benchmarks. This significant advancement was achieved entirely without relying on expensive and energy-intensive Extreme Ultraviolet (EUV) lithography.

Instead, APS™ leverages advanced etching techniques that substantially enhance sustainability, drastically reducing energy consumption without compromising throughput. Previous demonstrations of the APS™ process, validated through Intel’s Test Vehicle Program[1], confirmed its potential by achieving metal pitches as small as 25 nanometers.

“Today we are sharing more proof that the APS™ process can be a game changer for leading foundries. Thanks to UMC, we have been able to verify our process on production wafers that are shipped in quantities measured in millions of wafers annually,” said Dr. Robin Athle, Principal Researcher at AlixLabs. “Our mission is to create equipment that allows companies that don’t have access to EUV tools to scale down their production to 5 nanometer and beyond. By eliminating the dependency on EUV lithography, we are offering the industry a path towards more sustainable and economically feasible high-density chip production.”

Detailed results from AlixLabs’ UMC wafer tests and further insights into APS™ technology will be presented at the 2025 CMC Conference, scheduled for April 10th in Austin, Texas. Dr. Athle’s presentation “Atomic Layer Etching Pitch Splitting (APS™): a New Alternative to Multi Patterning” will be held at 4:00 PM at the Bergstrom Ballroom in Hilton Austin Airport Hotel.

EU Business Hub | Semicon Japan 2024 Business Mission - Introducing AlixLabs AB

Introducing AlixLabs AB (Sweden): one of our selected companies to participate on the EU Business Hub at Semicon Japan 2024. 

During the recent EU Business Hub at Semicon Japan 2024 business mission that took place between the 9th and 13th of December, we witnessed the spark of global collaboration in action. European and Japanese companies participating in the mission shared their impressions – and their feedback reveals exciting opportunities on the horizon. 

The EU Business Hub at Semicon Japan 2024 mission stood out for its comprehensive approach to supporting European businesses seeking to enter the Japanese market: 

Tailored B2B Matchmaking: European companies had the chance to meet with key Japanese industry players through personalized B2B meetings, fostering future partnerships.

Market Intelligence & Local Expertise: Participants received valuable market insights and coaching on business culture, provided by the programme team, helping them navigate the Japanese market with ease.

Cultural & Linguistic Support: Expert interpreters and briefings on Japanese business culture ensured that each interaction was smooth and effective.

EU-Branded Pavilion: A platform for European companies at Semicon Japan 2024, showcasing cutting-edge solutions and elevating visibility among global tech leaders.

3rd and Last Call for Papers, and List of Speakers / Symposium on ALD & ALE Applications #21, at 248th ECS Fall Meeting / Oct. 12-16, 2025 in Chicago, USA

This fall, the 248th ECS Meeting will be held on Oct. 12-16, 2025 in Chicago (IL, USA), and is expected to gather some 3,000 participants and 40 exhibitors from both academia and industry.

The conference has a strong focus on emerging technology and applications in both solid-state science & technology and electrochemistry.

• General information and the Meeting Program can be found here: Important Information and Call for Papers.
• For more information about our annual symposium G01 and the conference website: Meeting Information. 

The organizers of symposium G01 on “Atomic Layer Deposition & Etching Applications, 21” encourage you to submit your abstract(s) on topics, comprising but not limited to: 

1. Semiconductor CMOS applications: development and integration of ALD high-k oxides and metal electrodes with conventional and high-mobility channel materials; 

2. Volatile and non-volatile memory applications: extendibility, Flash, MIM, MIS, RF capacitors, etc.; 3. Interconnects and contacts: integration of ALD films with Cu and low-k materials; 

4. Fundamentals of ALD processing: reaction mechanisms, in-situ measurement, modeling, theory; 

5. New precursors, delivery systems & sustainability issues; 

6. Optical, photonic and quantum applications; applications aiming at Machine Learning, Artificial Intelligence 

7. Coating of nanoporous materials by ALD; 

8. Molecular Layer Deposition (MLD) and hybrid ALD/MLD; 

9. ALD for energy conversion applications such as fuel cells, photovoltaics, etc.; 

10. ALD for energy storage applications; 

11. Productivity enhancement, scale-up and commercialization of ALD equipment and processes for rigid and flexible substrates, including roll-to-roll and spatial processing; 

12. Area-selective ALD; 

13. Atomic Layer Etching (‘reverse ALD’) and related topics aiming at self-limited etching, such as atomic layer cleaning, etc. 

FYI: Last year at the PRiME 2024 Meeting in Honolulu, our symposium G01 on ALD & ALE Applications 20 attracted some 80 participants, attending a full 3-days schedule with 50 presentations (42 oral, of which 16 invited, plus 8 poster presentations). We expect to be at least as successful this Fall in Chicago. 

Abstract submission 

Meeting abstracts should be submitted not later than the deadline of March 28, 2025 via the ECS website: Submission Instructions

Submission Instructions Invited speakers A list of invited speakers follows below: 

Visa and travel For extensive information, see last year’s version: VISA AND TRAVEL INFORMATION

In addition, ECS’ Francesca Di Palo (francesca.dipalo@electrochem.org) can provide you with an official participation letter issued by the Electrochemical Society. For (limited) general travel grant questions, please contact travelgrant@electrochem.org. 

As in the past years, we expect also our symposium to be able provide some partial travel allowance to selected speakers. We are looking forward to meeting you all at our symposium G01 on ALD & ALE Applications 21, in Chicago | Oct. 12-16, 2025!

ALD FOR INDUSTRY 2025: Advancing Atomic Layer Deposition from Science to Industrial Applications in Dresden

The 8th International Conference "ALD for Industry" took place in Dresden from March 11 to 12, 2025, bringing together experts to discuss advancements in Atomic Layer Deposition (ALD) technology. In addition to the previously mentioned presentations, the conference featured several notable talks:

Prof. Fred Roozeboom

AlixLabs and Aether Semiconductor

Silicon Austria Labs

ASM International

The handshake

Prof. Riikka Puurunen

"Fundamentals of Atomic Layer Deposition: A Tutorial" by Prof. Riikka Puurunen

Prof. Riikka Puurunen from Aalto University, Finland, delivered a comprehensive tutorial on the fundamentals of ALD. She covered the history of ALD, its underlying surface chemistry, typical reaction mechanisms, and growth modes. Prof. Puurunen also discussed the role of diffusion in 3D structures and provided insights into surface reaction kinetics.

​In her tutorial titled "Fundamentals of Atomic Layer Deposition," Prof. Riikka Puurunen of Aalto University provided a comprehensive overview of ALD, a nanotechnology technique for precise surface modifications and thin coatings. She traced ALD's dual origins: Atomic Layer Epitaxy (ALE) developed by Tuomo Suntola in 1974, and Molecular Layering (ML) introduced by Valentin Aleskovskii and Stanislav Koltsov in the 1960s. The tutorial delved into the core principles of ALD, emphasizing its reliance on repeated, self-terminating reactions between gaseous reactants and surfaces. Prof. Puurunen categorized typical reaction mechanisms, discussed factors influencing saturation and growth modes, and highlighted "growth per cycle" (GPC) as a fundamental characteristic of ALD processes. She also explored the role of diffusion in complex 3D structures, noting how diffusion-limited growth can provide insights into surface reaction kinetics. The presentation available at Fundamentals of ALD: tutorial, at ALD for Industry, Dresden, by Puurunen 2025-03-11 | PPT

"Spatial ALD of IrO₂ and Pt Films for Green H₂ Production by PEM Electrolysis" by Dr. Paul Poodt

Dr. Paul Poodt, Chief Technology Officer at SparkNano, presented on the application of spatial ALD in fabricating iridium dioxide (IrO₂) and platinum (Pt) films. These materials are crucial for enhancing the efficiency of proton exchange membrane (PEM) electrolyzers used in green hydrogen production. Dr. Poodt highlighted how spatial ALD enables precise control over film thickness and composition, leading to improved performance and durability of electrolyzer components.

SparkNano’s CTO, Paul Poodt, presented on Spatial ALD of IrO₂ and Pt Films for Green H₂ Production by PEM Electrolysis on March 12 at 10:20 AM during the Emerging Applications session. Attendees had the opportunity to connect with him to discuss SparkNano’s spatial ALD technology.

"Advancements in ALD for Next-Generation Semiconductor Devices" by Dr. Christoph Hossbach

Dr. Christoph Hossbach from Applied Materials / Picosun Europe discussed recent progress in applying ALD techniques to next-generation semiconductor devices. His presentation covered the integration of ALD processes in manufacturing advanced transistors and memory devices, emphasizing the role of ALD in achieving atomic-scale precision and conformality required for modern microelectronics. 

"ALD Applications in Quantum Technology" by Dr. Martin Knaut

Dr. Martin Knaut of TU Dresden explored the utilization of ALD in developing components for quantum technologies. He highlighted how ALD's ability to deposit uniform and defect-free thin films is essential for fabricating qubits and other quantum devices, potentially leading to more stable and scalable quantum computing systems. 

"Emerging Applications of ALD in the Medical Field" by Dr. Mira Baraket

Dr. Mira Baraket from Atlant 3D presented on the potential of ALD in medical applications, including the development of biocompatible coatings for implants and drug delivery systems. She discussed how ALD can enhance the performance and safety of medical devices by providing precise control over surface properties.

Sources:

ALD for Industry 2025 – EFDS

AlixLabs Demonstrates 3 nanometers on Intel Silicon – Without EUV

The Swedish semiconductor company has fabricated leading-edge structures without using complex and costly lithography techniques.

The Swedish semiconductor company AlixLabs announces that it has used its technology to etch structures equivalent to commercial 3-nanometer circuits on Intel test silicon. Notably, this has been achieved without the use of extreme ultraviolet lithography (EUV) or advanced multi-patterning techniques such as SADP and SAQP (Self-Aligned Double Patterning and Self-Aligned Quad Patterning, respectively).

AlixLabs, a startup based in Lund, specializes in the development of Atomic Layer Etching (ALE), a type of plasma-based dry etching for cutting-edge structures, and ALE Pitch Splitting (APS), which enables transistor fins to be split using etching. The advantage of this approach is that it significantly reduces costs at the cutting edge, where wafer prices skyrocket with each new generation.

"We are pleased to demonstrate how APS can help the industry reduce its dependence on multi-patterning while lowering costs and environmental impact. Our technology enables the fabrication of sub-10-nanometer structures on silicon, and through Intel’s Test Vehicle Program, we have proven that sub-5-nanometer structures can be achieved using etching alone."

– Dmitry Suyatin, CTO and Co-Founder of AlixLabs

According to Dmitry Suyatin, AlixLabs’ CTO, this demonstration was made possible through Intel’s Test Vehicle Program, which provided test silicon for AlixLabs to process with its APS technology. While ALE has traditionally been limited to structures in the 10-nanometer class, AlixLabs' APS technique has significantly simplified the manufacturing of structures smaller than 5 nanometers.

Etching 3-nanometer-class structures without advanced EUV lithography, using only immersion lithography, is a significant breakthrough—provided the technology can be scaled and applied in practical manufacturing. AlixLabs has previously stated its goal of seeing its technology adopted by TSMC and Samsung for their 2-nanometer processes.

Since the industry moved past the 28-nanometer node, multi-patterning has become increasingly necessary to create smaller structures and transistors. This lithographic technique involves breaking down complex patterns into simpler ones and sequentially patterning them onto the silicon wafer for higher precision and detail. Lithography can perform this in two, three, or four steps (SADP, SAQP), though more steps are theoretically possible, they are considered too complex and costly for practical use at smaller nodes.

"APS technology demonstrates that complex multi-patterning techniques such as SADP and SAQP are not needed to manufacture circuits at 5 nanometers and below. This increases the potential to use immersion lithography for critical mask layers in 3-nanometer processes. These results were achieved with our early Alpha equipment, and Beta equipment will follow later in 2025. We thank Intel for enabling this demonstration and providing high-quality test silicon."

– Jonas Sundqvist, CEO and Co-Founder of AlixLabs

While lithographic multi-patterning is often necessary, it comes with several downsides. Each additional step requires more masks, which must be precisely aligned to form the final, complex pattern. Even a slight misalignment can lower yield and performance, but more importantly, it significantly extends production time. Avoiding multi-patterning whenever possible is therefore always preferable.

It is essential to distinguish between "nanometer-class" structures and actual physical nanometer measurements. What AlixLabs has achieved is a metal pitch (the distance between metal interconnects connecting transistor gates) of 25 nanometers through dry etching. This compares to TSMC’s most advanced 3-nanometer process, which achieves a metal pitch as low as 23 nanometers in certain high-density configurations.

AlixLabs highlights this test silicon as a major milestone towards commercialization and announces that more updates will follow later in 2025. Additional details will be presented by CTO Dmitry Suyatin at SPIE Advanced Lithography + Patterning in San Jose, California, on February 27, from 9:00–9:20 AM (local time).

Sources:

AlixLabs demonsterar 3 nanometer på Intel-kisel – utan EUV – Semi14

AlixLabs to Showcase Latest APS™ Findings at SPIE Advanced Lithography + Patterning – AlixLabs

Browse the 2025 program for SPIE Advanced Lithography + Patterning

ALD for Industry | International Conference & Exhibition - March 11 - 12, 2025 | Dresden, Germany

ALD for Industry | International Conference & ExhibitionMarch 11 - 12, 2025 | Dresden, Germany

+++ Poster Submission, Early Bird Registration & Exhibition Booking +++

Deadline: January 31, 2025

Atomic Layer Deposition is an important technology for surface modification and structuring. Again we will discuss recent developents and applications of the technology in March in Dresden. Already 26 speakers confirmed their contributions. Check the first anounnced talks and use the earyl bird registration until January 31, 2025.

Also Poster Submissions and booking of exhibition places is possible until January 31, 2025. Present your services and products to the ALD Community and become visible to interested people.

More information you can find the the ALD Website: https://lnkd.in/eKt86GV7

General Information to the event [PDF]

Template Abstract ALD for Industry 2025 [PDF]

Hotel Recommendations [PDF]

Program Preview

We are pleased to announce first speakers of the upcoming event. A complete porgram will be published in January 2025Fundamentals of atomic layer deposition: a tutorial| Riikka Puurunen, Aalto University, Sweden

• Industrial batch ALD for optical applications | Shuo Li, Afly Solution Oy, Finland
• Direct Processing by µDALP™. Precision Coatings for Next Gen Devices | Maksym Plakhotnyuk, ATLANT 3D, Denmark
• Nanoscale solid-state lithium-ion electrolytes enabled by atomic layer deposition | Messaoud Bedjaoui, CEA Leti, France
• Fabrication of Surface Relief Gratings using ALD-based Technologies to Overcome the Challenges of Reactive Ion Etching of TiO2 | Mathias Franz, Fraunhofer ENAS, Germany
• Monitoring and optimisation of ALD processes with Remote Plasma Optical Emission Spectroscopy | Erik Cox, Gencoa Ltd, UK
• Optimizing Plasma-Assisted Atomic Layer Deposition using Impedans RFEAs | Angus McCarter, Impedans Ltd., UK
• Improving atomic layer deposition process of silicon oxide (SiO2) and aluminum oxide (Al2O3) | Long Lei, Fraunhofer IMPS, Germany
• Introducing a Surface Acoustic Wave-Based Miniaturized Aerosol Source for Controlled Liquid Precursor Delivery in ALD Processes | Mehrzad Roudini, Leibniz IFW, Germany
• Challenges and Solutions in ALD of Thermal Budget Sensitive Ferroelectric Materials | Bart Vermeulen, Ferroelectric Memory Co GmbH, Germany
• ALD for Nanoparticles: From Fundamentals to Industrial Applications | Rong Chen, University of Science and Technology HUST, China
• Recent developments and emerging applications in atmospheric-pressure ALD on high-porosity membranes | Fred Roozeboom, University of Twente, Netherlands
• Past, present and future of ALD from an industrial perspective | Jan Willem Maes, ASM, Belgium
• Advanced in-situ QCM process monitoring | Martin Knaut, ALS Metrology UG, Germany
• Cryogenic Atomic Layer Etching (Cryo-ALE) of low-k dielectrics like SiO2, and GaN etching. | Rémi Dussart, Université d´Orleans, France
• ALD for Memory Applications: a matter of details | Laura Nyns, IMEC, Belgium
• Spatial ALD of IrO2 and Pt films for green H2 production by PEM electrolysis | Paul Poodt, SparkNano B. V., The Netherlands
• APECS Pilot Line – Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems | Wenke Weinreich, Fraunhofer IPMS, Germany

Program Committee

• Sean Barry, Carleton University, Canada
• Gloria Gottardi, Fondazione Bruno Kessler, Italy
• Christoph Hossbach, Applied Materials / Picosun Europe, Germany
• Martin Knaut, TU Dresden, Germany
• Laura Nyns, IMEC, Belgium
• Fred Roozeboom, University Twente, Netherlands
• Jonas Sundqvist, Alixlabs, Sweden

POSTER Exhibition

The Poster Submission is open until January 31, 2025. Please send us an Abstract for your Poster Application. PO001 | Deposition of High Quality Aluminium Fluoride Layers through Optimization of a PEALD Process using Al(CH3)3 and SF6 | Fabian Steger, RhySearch, Buchs, Austria PO002 | Evaluating the Enhanced Fire Resistance of Polyamide Fabric through Dual-Layer Treatment with ALD-ZnO and DOPO-Based Silane | Sebastian Lehmann, Leibniz IFW, Germany

Surface Passivation: A Cornerstone for Advancing Semiconductor Technologies

Modern semiconductor devices like transistors, solar cells, microLEDs, and thin-film transistors all rely heavily on effective surface passivation to enhance performance. As devices continue to evolve toward 3D architectures and smaller form factors, managing surface defects becomes critical to maintaining efficiency. Surface passivation, achieved through thin films deposited by atomic layer deposition (ALD) or similar techniques, minimizes charge carrier recombination at surface sites, thereby boosting the overall performance of semiconductor devices. The latest review paper by Bart Macco, published in the Journal of Vacuum Science and Technology A, provides a comprehensive analysis of surface passivation techniques across silicon, germanium, and III–V materials. The study highlights the importance of atomic-scale processing methods, such as ALD and atomic layer etching (ALE), in meeting the demands of advanced semiconductor architectures. It also explores the emerging trends in high-volume manufacturing of ALD Al₂O₃ layers, novel passivation stacks tailored for different semiconductor materials, and the growing role of in-situ cleaning processes. This review underscores how advancements in passivation methods are shaping next-generation semiconductor devices, addressing both performance and reliability challenges. For more details, the paper is open access and licensed under Creative Commons Attribution and you can also check out the recent post in AtomicLimiuts.com (links below).

Sources: 

Macco, B., et al. "Surface passivation approaches for silicon, germanium, and III–V semiconductors." Journal of Vacuum Science and Technology A.: Surface passivation approaches for silicon, germanium, and III–V semiconductors | Journal of Vacuum Science & Technology A | AIP Publishing

Surface passivation as a cornerstone of modern semiconductor technology – Highlighting a comprehensive review paper on surface passivation for silicon, germanium, and III–V materials – Atomic Limits

Atomic Level Processing of Gold: Advances in Atomic Layer Deposition (ALD) and Atomic Layer Etching (ALE)

Atomic layer processing methods, including Atomic Layer Deposition (ALD) and Atomic Layer Etching (ALE), have advanced the precision with which metals like gold can be manipulated at the atomic scale. Traditionally, gold has been challenging to process due to its low reactivity, but recent developments have made it possible to deposit and etch gold with atomic-scale control. While Professor Seán Barry’s work has focused on pioneering methods for gold deposition using ALD, Professor Steven M. George and his team have recently demonstrated a successful thermal ALE technique for gold. Together, these breakthroughs represent a new frontier in gold processing, enabling nanoscale applications in electronics, nanotechnology, and catalysis.

Advances in Atomic Layer Deposition (ALD) of Gold: Professor Seán Barry’s Work

Atomic Layer Deposition (ALD) relies on self-limiting surface reactions to grow thin films with atomic precision, and it is ideal for materials where control over layer thickness and uniformity is essential. However, gold presents unique challenges in ALD due to its inertness and lack of reactive sites. Despite this, Professor Seán Barry and his team have developed a plasma-enhanced ALD (PEALD) approach that overcomes these hurdles by using a specialized gold precursor and plasma activation.

Plasma-Enhanced ALD (PEALD) Method

Barry’s team utilized a trimethylphosphine-supported gold(III) precursor, specifically Me₃AuPMe₃, in combination with oxygen plasma to deposit gold layers. The plasma serves to activate the precursor and facilitate the deposition reaction, which would otherwise be hindered by gold’s low reactivity.

Low-Temperature Deposition

The process is achievable at temperatures around 120–130°C, considerably lower than traditional thermal ALD processes. This temperature range minimizes the risk of precursor decomposition, allowing the deposition of smooth and uniform gold films without unwanted by-products.

Deposition Rate and Film Quality

The deposition process achieved a growth rate of approximately 0.5 Å per cycle, providing exceptional control over film thickness. Barry’s PEALD method allows for uniform, conformal gold coatings that are valuable in microelectronics, sensing devices, and other applications where thin films of noble metals are required.

University of Helsinki Unveils Thermal ALD Process for Gold Coating in 3D Applications

The University of Helsinki has developed a groundbreaking thermal Atomic Layer Deposition (ALD) process for gold using the precursor Me₂Au(S₂CNEt₂) with a broad process window (120–250°C), achieving uniform and highly conductive films. This innovation addresses the limitations of plasma-enhanced ALD, which can struggle with coating complex 3D structures. By utilizing ozone as a co-reactant, the researchers achieved continuous gold films with a growth rate of 0.9 Å/cycle at 180°C and low resistivity, ideal for advanced applications requiring precise, conductive coatings. This follows an earlier Helsinki breakthrough in Ruthenium ALD, marking another step forward in atomic-level metal deposition techniques.

Breakthrough in Atomic Layer Etching (ALE) of Gold: Professor Steven M. George’s Method

Building on the advances in ALD for gold, Professor Steven M. George’s recent work on thermal ALE offers a complementary technique to precisely remove gold layers. Published in May 2024, George’s ALE method for gold uses a novel two-step thermal process involving chlorination and ligand addition. This approach bypasses the need for plasma, instead relying on a purely thermal cycle to achieve atomic-level etching of gold.

The study demonstrates a thermal atomic layer etching (ALE) process for gold using sequential reactions: chlorination with sulfuryl chloride (SO₂Cl₂) to form gold chloride, followed by ligand addition with triethylphosphine (PEt₃) to produce a volatile etch product, AuClPEt₃. This method achieved consistent etching at 0.44 ± 0.16 Å per cycle at 150°C on gold films. Mass spectrometry confirmed AuClPEt₃ as the main etch product, while analysis showed that ALE maintained nanoparticle smoothness without surface roughening. The approach was also effective on copper and nickel, offering a versatile ALE pathway for metals through controlled chlorination and ligand-addition reactions. LINK: https://pubs.acs.org/doi/10.1021/acs.chemmater.4c00485

Two-Step Thermal ALE Process

Chlorination: The gold surface is initially chlorinated using sulfuryl chloride (SO₂Cl₂), which forms gold chloride (AuCl) on the surface. This step primes the gold for the ligand addition reaction.

Ligand Addition with Triethylphosphine (PEt₃): After chlorination, triethylphosphine (PEt₃) is introduced to bind with the gold chloride, creating a volatile product, AuClPEt₃, which desorbs from the surface, effectively removing one atomic layer of gold.

Etch Rate and Temperature Control

The ALE process operates in a temperature range of 75 to 175°C, with the optimal and most consistent etch rate of 0.44 ± 0.16 Å per cycle occurring at 150°C. This repeatable, self-limiting reaction cycle ensures precise control over the etching process, which is critical for applications demanding high accuracy.

Experimental Observations and Mass Spectrometry

Quartz crystal microbalance (QCM) measurements tracked mass changes during each ALE cycle, while in situ quadrupole mass spectrometry (QMS) on gold nanopowder confirmed that AuClPEt₃ was the primary volatile product. The intensity of the AuClPEt₃+ ion peaked early in each PEt₃ dose, indicative of a self-limiting reaction where gold is etched in controlled increments.

Structural Integrity of Gold Nanoparticles

Analysis using X-ray photoelectron spectroscopy (XPS) and transmission electron microscopy (TEM) showed that the ALE process did not roughen the surface of gold nanoparticles. This smoothness is crucial for applications in electronics and photonics, where surface quality affects device performance. Additionally, powder X-ray diffraction (XRD) revealed slight broadening of diffraction peaks post-ALE, indicating sintering and suggesting that gold redistribution could contribute to the formation of larger nanoparticles.

Combined Implications of ALD and ALE for Gold

The complementary nature of Barry’s PEALD for gold deposition and George’s thermal ALE for gold etching offers an unprecedented level of control over gold at the atomic level. Together, these methods enable:

High-Precision Patterning: Combined ALD and ALE allow for nanoscale patterning of gold films with atomic precision, benefiting fields such as semiconductor manufacturing and nanotechnology.

Surface Engineering: The smoothness and control over film morphology achieved through these processes make it possible to engineer gold surfaces with specific properties, crucial for sensors, catalysis, and plasmonic devices.

Enhanced Flexibility in Fabrication: The ability to alternate between deposition and etching at the atomic scale provides unparalleled flexibility, especially for creating multilayer structures or complex geometries in microelectronics and MEMS devices.

Sources:

https://pubs.acs.org/doi/10.1021/acs.chemmater.4c00485

Previous Articles on Gold ALD:

BALD Engineering - Born in Finland, Born to ALD: Thermal Atomic Layer Deposition of Gold

BALD Engineering - Born in Finland, Born to ALD: Thermal Atomic Layer Deposition of Gold: Mechanistic Insights, Nucleation, and Epitaxy

BALD Engineering - Born in Finland, Born to ALD: University of Helsinki present a thermal ALD gold process

BALD Engineering - Born in Finland, Born to ALD: Picosun and Carleton Strike Gold with ALD

Seiichi Iwamatsu, the Inventor of Atomic Layer Etching: The Conception of Cycled Exposures of Silicon to Halogens and Pulses of Heat, Ions, and More

Seiichi Iwamatsu, the Inventor of Atomic Layer Etching: The Conception of Cycled Exposures of Silicon to Halogens and Pulses of Heat, Ions, and More

Fred Roozeboom University of Twente, Jonas Sundqvist AlixLabs, Dmitry B. Suyatin AlixLabs, Kuniyuki Kakushima Institute of Science Tokyo (Tokyo Institute of Technology)

ECS-PRiME 2024 in Honolulu

The history of Atomic Layer Deposition (ALD) has been extensively researched in the VPHA-project (www.vph-ald.com/) initiated in 2013 by R. Puurunen [1]. It is commonly accepted that Atomic Layer Deposition (ALD) was conceived in the Baltic area as a unique ultrathin-film growth method based on the repeated, self-terminating gas-solid half-reactions of at least two volatile compounds on a solid substrate surface. Originally, in the 1960’s, the Russians Alekskovski and Kol'tsov [2]) named this method Molecular Layering and exactly 50 years ago, in 1974 the Finnish inventors Suntola and Antson [3] patented the method as Atomic Layer Epitaxy. This fact has been officially celebrated at the 24th ALD Conference in Helsinki (Aug. 5, ’24 ald2024.avs.org).

Atomic Layer Etching (ALE) has lagged behind ALD. For long [4,5] the first patent published on ALE was thought to have been initiated by Max Yoder [6]. In 1987 he conceived the idea on diamond etching with intermittent pulsing of nitrogen dioxide and noble gas ions mixed with hydrogen gas. However, it was Seiichi Iwamatsu (Fig. 1) of Seiko Epson, Japan, who filed in 1981 an application on Si-etching by repeated exposure to iodine (I2) chemistry at moderate temperatures (20 °C to 100 °C) followed by a light or heat pulse up to ~ 300 °C [7]; see Fig. 2. This patent was followed by several others on ALE [8]. One of these patents disclosed quasi-ALE (named “digital etching”) via Si-surface modification by “lamination” of a single Cl-atomic layer from exposure to Cl2 gas, followed by a removal step carried out by Ar+-ion bombardment to etch off “one atomic layer or at most three atomic layers by controlling the kinetic energy” [9].

This presentation will highlight the groundbreaking work and background of the Japanese inventor Seiichi Iwamatsu. Born in 1939 in Kyoto to a family of doctors - his father being a practicing physician- he grew up and studied in Osaka, after which he spent many years as a ‘master inventor’ (over 1200 patents filed in his name) for Seiko Epson (~1970-1990) and others afterwards. He played key roles in thin-film technology and e-beam lithography. He also contributed to the success story of Seiko’s quartz watch, a masterpiece in micromachining a miniature tuning fork from crystalline fused silica, tuning/trimming it to 32,768 Hz (=215 Hz), packaging it in a hermetically sealed case and integrating it with flip-flop frequency dividing and counting electronic circuitry and a step motor [10].

From the above it is clear that Mr. Iwamatsu can be recognized as the original inventor of Atomic Layer Etching.

Source: Late G-5068 - Seiichi Iwamatsu, the Inventor of Atomic Layer Etching: The Conception of Cycled Exposures of Silicon to Halogens and Pulses of Heat, Ions, and More https://ecs.confex.com/ecs/prime2024/meetingapp.cgi/Paper/199461

----------------------------------------------------

Acknowledgement

The authors would like to thank Dr. Masanobu Honda (Tokyo Electron Miyagi Ltd., Japan) for his support in retrieving some of the historic facts mentioned herewith about Dr. Iwamatsu.

References

[1] R.L. Puurunen, Chem. Vap. Deposition 20, pp. 332–344 (2014); doi:10.1002/cvde.201402012.

[2] V.B. Alekskovski and S. I. Kol'tsov, Some characteristics of molecular layering reactions, Abstract of Scientific and Technical Conference, Goskhimizdat, Leningrad, 1965, p. 67 (in Russian).

[3] T. Suntola and J. Antson, FIN 52359, priority Nov. 29, 1974, US Patent 4,058,430, Nov. 15, 1977.

[4] K.J. Kanarik, et al., J. Vac. Sci. Technol. A 33, 020802 (2015); doi/10.1116/1.4913379.

[5] W.M.M. Kessels, www.atomiclimits.com/ March 2, 2020.

[6] M.N. Yoder, Atomic Layer Etching, US Patent 4,756,794, July 12, 1988; assigned to US Navy.

[7] S. Iwamatsu, Atomic Layer Etching Method, JPS5898929A / JPH0379862B2; priority Dec. 9, 1981, published June 13, 1983; assigned to Seiko Epson Corp.

[8] https://worldwide.espacenet.com/patent/search/family/016189802/publication/JPH0472726A?q=iwamatsu%20seiichi%20atomic%20layer%20etching

[9] S. Iwamatsu, Digital Etching Process, JPH0472726A, priority: July 13, 1990, published March 6, 1992; assigned to Seiko Epson Corp.

[10] https://corporate.epson/en/technology/search-by-products/wearable/quartz-watch.html

Lam Research Sees Growth Opportunities in Etch and Deposition Technologies Despite NAND Downturn

In its Q1 2025 earnings call, Lam Research reported strong performance and emphasized growth opportunities, particularly in etch and deposition technology. CEO Tim Archer highlighted optimism for NAND spending recovery in 2025, supported by technology upgrades and a transition to molybdenum through Lam’s advanced Atomic Layer Deposition (ALD). Lam is positioned to capture opportunities in advanced semiconductor nodes like gate-all-around and EUV patterning, while its expanded offerings in high-bandwidth memory (HBM) and advanced packaging align with growing demand in AI and high-performance computing. Despite regulatory challenges in China, Lam continues to serve this market by focusing on upgrades and services. Looking ahead, Lam expects to outpace industry growth, driven by its strategic positioning across advanced technologies.

In its Q1 2025 earnings call, Lam Research Corporation (NASDAQ: LRCX) reported solid performance and reiterated optimism for growth in 2025, largely driven by demand for etch and deposition technologies. CEO Tim Archer emphasized Lam’s strategic positioning in an industry experiencing technological shifts, despite a prolonged downturn in NAND spending.

Lam anticipates a recovery in NAND spending in 2025, largely driven by technology upgrades rather than new capacity expansions. Key factors include a transition from tungsten to molybdenum in NAND structures, which improves performance by reducing resistivity. Lam is well-positioned in this area due to its extensive installed base and production wins, projecting an advantageous position as these upgrades scale into 2025.

NAND Technology Upgrades Set to Drive Etch and Deposition Demand in 2025

While the NAND segment has been in a prolonged downturn, Lam anticipates a recovery in 2025 as manufacturers upgrade to advanced nodes. The push toward 3D NAND layers exceeding 200 is essential to meet the growing demand for high-speed, high-capacity storage in data centers and client devices. Currently, about two-thirds of NAND capacity remains at older technology nodes, highlighting significant room for technology upgrades. Lam’s extensive installed base of NAND equipment positions it well to benefit as customers look to improve efficiency and performance.

Furthermore, Archer highlighted a shift from tungsten to molybdenum as a key materials change in NAND, addressing word line resistance challenges. This transition is particularly favorable for Lam, as it has already secured production wins in molybdenum deposition, which will scale up throughout 2025. These advancements are expected to enhance Lam's leadership position in NAND technology transitions.

Lam's product offerings mentioned in the reporting, along with their primary applications and strategic impacts.

Advanced Logic and Foundry Nodes: Key Growth Segments for Lam

Lam is also poised to benefit from shifts in advanced logic and foundry nodes, which are increasingly adopting gate-all-around architectures, backside power distribution, and advanced EUV patterning. These cutting-edge technologies require more intensive use of etch and deposition processes, aligning with Lam’s expertise and product offerings.

Archer noted the company's recent wins in selective etch tools and other innovations that support these advanced nodes, positioning Lam favorably as customers transition to architectures with greater power and performance needs. This expanding demand from foundry and logic customers offers a substantial growth opportunity for Lam’s advanced etch and deposition technologies.

Advanced Packaging Driven by AI Fuels Revenue Growth

The AI and high-performance computing boom has intensified demand for advanced packaging, particularly for high-bandwidth memory (HBM). Lam’s copper plating technology, SABRE 3D, has experienced substantial adoption, doubling its market share this year. This growth has been fueled by the rising complexity of 2.5D and 3D packages, which require high-performance interconnections to support AI-driven systems.

Lam anticipates this trend will continue into 2025 as the industry moves toward more advanced and intricate packaging solutions. According to Archer, advanced packaging will play a critical role in the semiconductor ecosystem for the foreseeable future, and Lam’s early investment in this technology has positioned it for continued market share gains.

Supporting Installed Base and Productivity in Memory Markets

Lam’s Customer Support Business Group (CSBG) has also shown growth, focusing on productivity enhancements and tool reuse. With Lam’s extensive tool installations in both DRAM and NAND, customers are prioritizing upgrades over entirely new systems, especially as they look to improve cost efficiency during NAND’s down cycle. This focus on tool reuse has led to recent market share gains for Lam, as existing tools are upgraded for better value than new installations.

As DRAM and NAND customers intensify efforts to reduce costs, Lam’s service-oriented model and productivity solutions, including equipment intelligence services, have seen greater adoption. This trend underscores Lam's ability to support its customers' evolving needs in an era of increased etch and deposition intensity.

Lam Research Leverages ALD for Moly Transition in NAND, Driving Next-Gen Semiconductor Performance

Lam Research's perspective on ALD is optimistic, particularly as it becomes increasingly essential in NAND technology upgrades. The company highlighted the industry's ongoing shift from tungsten to molybdenum (moly) for improved resistivity in 3D NAND structures, a transition that Lam’s ALD technology is well-positioned to support. Lam has already secured production wins for ALD applications with molybdenum, expected to ramp up significantly in 2025. This capability extends beyond NAND, with potential applications in DRAM and advanced logic/foundry nodes, underscoring ALD’s growing importance in meeting next-generation semiconductor demands.

Lam Research Adapts to Regulatory Challenges as China Revenue Set to Decline in 2025

In its Q1 2025 earnings presentation, Lam Research highlighted key developments and expectations for the China market. China accounted for roughly 37% of Lam's revenue in the September quarter, but the company anticipates this share will decrease to around 30% by December and potentially decline further in 2025. This projected downturn reflects both anticipated shifts in demand and the impact of U.S. export restrictions on advanced semiconductor equipment sales to China. Lam acknowledged the challenges posed by ongoing and potential new U.S. export controls, which could limit its ability to sell to certain advanced technology segments in China. Nevertheless, Lam remains committed to supporting its domestic Chinese customers within the boundaries of regulatory compliance, expecting demand in restricted segments to normalize as global WFE (wafer fabrication equipment) spending adjusts.

Much of Lam's business in China now focuses on servicing domestic fabs with tools for trailing-edge and specialty node processes, areas that generally remain unaffected by export controls. Through its Reliant product line, Lam continues to support these nodes, emphasizing upgrades and maintenance services as primary offerings in a market constrained by new advanced technology sales. Despite potential reductions in advanced equipment sales, the company is confident that its service and support model will help stabilize revenue in the region. By prioritizing productivity solutions and customer support, Lam is adapting to a complex regulatory environment while anticipating that China’s share of its revenue will gradually normalize amid a broader decline in WFE spending in the country.

Strategic Positioning in 2025 and Beyond

In summary, Lam Research is set to capitalize on a growing demand for etch and deposition technology driven by the industry’s shift to advanced architectures. Archer concluded the call with optimism, stating that the company is well-positioned to capture market share as the semiconductor industry increasingly relies on complex, three-dimensional structures. With its advanced product offerings, Lam expects to outperform overall wafer fabrication equipment (WFE) growth in 2025, strengthening its leadership across multiple semiconductor sectors.

Technological Innovations in Semiconductor Manufacturing: Insights from Tokyo Electron's 2024 Integrated Report

This summary, based on Tokyo Electron's Integrated Report 2024, provides insights into the future outlook of the Wafer Fab Equipment (WFE) market, with a particular focus on the technological advancements driving demand for advanced etch and deposition processes, including the transition to next-generation semiconductor architectures like GAAFET (Gate-All-Around Field-Effect Transistor). As the industry evolves, these technologies are becoming increasingly critical to maintaining the pace of innovation and ensuring the continued scaling of semiconductor devices.

The Wafer Fab Equipment (WFE) market is set for significant growth, driven by several key factors: the rising demand for semiconductors fueled by advanced technologies like AI, IoT, 5G, and autonomous vehicles; the ongoing transition to more advanced process nodes, which requires increasingly complex and precise equipment, particularly in etching, deposition, and lithography; substantial investments in new semiconductor fabs globally, expected to boost WFE demand as these facilities come online between 2022 and 2026; and the emergence of new semiconductor architectures like 3D NAND, DRAM, and GAAFET, which necessitate leading-edge WFE to manage the heightened complexity of these manufacturing processes.

According to Tokyo Electron (TEL), the future outlook of the Wafer Fab Equipment (WFE) market is poised for substantial growth, largely driven by the rapid technological advancements in the semiconductor industry. The escalating complexity of semiconductor devices, particularly in the areas of 3D NAND, DRAM, and advanced logic devices, is creating an increasing demand for sophisticated etch and deposition technologies, such as Atomic Layer Deposition (ALD). These technologies are critical for enabling the high precision and performance required in modern semiconductor manufacturing.

For 3D NAND, the trend towards higher layer counts—potentially reaching 500 to 1,000 layers—necessitates advanced etching processes capable of creating deep holes and trenches with high aspect ratios. This is essential for maintaining structural integrity while maximizing storage density. Similarly, ALD is becoming increasingly important in the deposition of conformal films over these intricate 3D structures, ensuring uniformity at the atomic level, which is crucial for device performance and reliability.

DRAM technology is also evolving, with the shift towards 3D DRAM structures demanding new solutions in both etching and deposition. As memory cells are stacked vertically, the need for precise etch processes to define these high aspect ratio structures becomes critical. Concurrently, ALD plays a vital role in creating ultra-thin films that can meet the stringent requirements of these new architectures, enabling the continued scaling of DRAM technology.

The transition to GAAFET (Gate-All-Around Field-Effect Transistor) structures marks a significant evolution in semiconductor technology, necessitating highly advanced etch processes. These processes must achieve extreme precision in defining the narrow, high aspect ratio features characteristic of GAAFETs, ensuring device integrity and performance as scaling continues. The integration of etch with ALD is particularly crucial, allowing for the precise control of gate structures at an atomic level, which is essential for optimizing device characteristics. Additionally, the co-optimization of etching with high-NA EUV lithography ensures that the finest features can be accurately patterned and etched, supporting the successful scaling of next-generation devices. As semiconductor architectures become more complex, the role of advanced etch technologies will be pivotal in enabling the high performance and reliability demanded by GAAFET and beyond.

Furthermore, the industry’s focus on sustainability is driving demand for WFE that not only enhances performance but also reduces environmental impact. Technologies like ALD and advanced etch processes are being developed with an eye towards lowering power consumption and minimizing CO2 emissions, aligning with broader goals of achieving net-zero emissions in semiconductor manufacturing.

Overall, the WFE market is expected to see robust growth, underpinned by the critical role of etch and deposition technologies in advancing semiconductor innovation. These technologies are not only essential for maintaining the pace of Moore’s Law but also for enabling new device architectures that will define the future of the semiconductor industry. With significant investments in R&D and a strategic focus on early-stage technology development, the WFE market is well-positioned to meet the evolving needs of semiconductor manufacturers.

Source: Integrated Report/Annual Report | Investor Relations | Tokyo Electron Ltd. (tel.com)

AlixLabs Qualifies APS™ for Use In 300-millimeter Silicon Wafer Designs

Swedish semiconductor startup clears technical hurdle for leading-edge process use on 300 mm wafer design*.

Scanning electron microscopy (SEM) images of amorphous silicon lines before (top) and after the APSTM process: nominal 40 nm line width and 40 nm half-pitch converted to lines with width below 15 nm and a half-pitch of 20 nm. Bild: Alixlabs

Stockholm, Sweden – September 12th, 2024 – AlixLabs AB, a Swedish semiconductor startup specializing in Atomic Layer Etching (ALE), announces that it has qualified its APS™ (ALE Pitch Splitting) process on a 300-millimeter silicon wafer design, marking one of its final steps towards commercial adoption. APS™ provides atomic-scale precision and pattern fidelity with critical dimensions below 15 nanometers for both single crystalline and amorphous silicon.

AlixLabs APS™ is designed to reduce the cost of leading-edge manufacturing, sub-7-nanometer, where feature sizes of less than 20 nanometers are required. An estimated cost saving of up to 40 percent per mask layer can be achieved with APS™ rather than relying on EUV lithography, and complex self-aligned multi patterning schemes.

AlixLabs' patented and wordmarked APS™ IP – short for Atomic Layer Etch (ALE) Pitch Splitting, here demonstrated in a simple animation.

“Proving that APS™ works on lithography designs on 300-millimeter wafers, is what we’ve all worked on since we founded AlixLabs in 2019,” says CEO and co-founder Dr. Jonas Sundqvist. “Not only do we aim to provide chip manufacturers wafer processing equipment that can create 20-nanometer half-pitch lines and critical dimension below 15 nanometers on silicon, we aim to do that at a lower cost and a more sustainable way than other technologies”

“We are also able to provide record breaking 3-nanometer critical dimension features on gallium phosphide (GaP) wafers today showing that APS™ can scale far into the future beyond what is needed today,” adds CTO and co-founder Dmitry Suyatin.

APS™ is positioned as an alternative to self-aligned double and quadruple patterning (SADP and SAQP). It allows for splitting dense line structures that can act as a foundation for transfer-etch into various materials such as dielectrics, metals, metal nitrides, and high-k dielectrics. The structures created with APS™ can also be used as-is for critical device features such as the fins in FinFET-type transistors due to extremely low surface damage.

AlixLabs’ goal is to supply leading semiconductor manufacturers, in both logic and memory segments. By enabling them to simplify and speed up their chip production at least fourfold for each critical mask layer by replacing four plasma wafer processing chambers in the SADP process flow with one APS™ chamber and eightfold correspondingly in SAQP. Finally, AlixLabs contributes overall to more sustainable semiconductor manufacturing.

*EBL patterned 300 mm wafers were provided by Fraunhofer IPMS Center Nanoelectronic Technologies (CNT) and financed by Ascent+ European Union's Horizon 2020 research and innovation program under GA No 871130.

Sources:

www.alixlabs.com

New Export Controls on ALD, ALE and ASD Technologies Effective September 2024 to Safeguard National Security

The US Bureau of Industry and Security (BIS) is introducing* stringent export controls targeting advanced technologies essential to national security, particularly within the semiconductor, quantum computing, and additive manufacturing sectors. These controls include new and revised Export Control Classification Numbers (ECCNs) and specific restrictions on critical equipment and materials, such as those involved in Gate-All-Around Field-Effect Transistor (GAAFET) technology, Atomic Layer Etching (ALE), and Atomic Layer Deposition (ALD). The controls aim to safeguard U.S. technological leadership while harmonizing with international export control standards. Specific restrictions apply to high-precision wafer processing equipment and isotopically enriched materials used in quantum computing, reflecting the critical importance of these technologies. These measures ensure that while international collaboration continues, sensitive technologies remain protected under national security protocols.

BIS has introduced new export controls focused on advanced technologies, particularly in the semiconductor, quantum computing, and additive manufacturing sectors. These controls include new Export Control Classification Numbers (ECCNs), revisions to existing ones, and the addition of new license exceptions for countries with similar technical controls. This rule aims to protect national security and advance foreign policy objectives by aligning U.S. export controls with those of international partners. The controls cover a wide range of items, including quantum computing technologies and semiconductor manufacturing equipment, reflecting the critical importance of these technologies to national security. The rule is effective immediately, though there are delayed compliance dates for certain items, allowing businesses time to adjust to the new requirements.

BIS has also established a framework to differentiate between items controlled multilaterally and those controlled through Implemented Export Controls (IEC), which are harmonized with international partners. The new regulations include provisions for annual reporting, particularly concerning the deemed export of quantum technology and software, highlighting the global nature of innovation in these fields. The rule is designed to support U.S. technology leadership while ensuring that export controls do not impede international collaboration, particularly in areas like quantum computing, where global expertise is crucial. Comments on the rule and its potential impact on supply chains and compliance programs are invited, with a focus on refining the scope and clarity of the new ECCNs and license exceptions.

BIS specifies that the restrictions on GAAFET (Gate-All-Around Field-Effect Transistor) technology primarily focus on the "technology" required for the "development" or "production" of GAAFET structures. This includes process recipes and other detailed specifications necessary for fabricating these advanced semiconductor devices. These restrictions are captured under ECCN 3E905, which applies to the "technology" for GAAFETs but does not extend to vertical GAAFET architectures used in 3D NAND. The export, reexport, or transfer of this technology to certain countries requires a license due to its national security and regional stability implications. However, the rules include specific exceptions for existing collaborations and provisions for continued access under certain conditions.

The specific wafer processing technologies restricted for export include:

Dry Etching Equipment:

Equipment designed for isotropic dry etching, as well as anisotropic etching of dielectric materials. These include technologies that enable the fabrication of high aspect ratio features, with aspect ratios greater than 30:1 and a lateral dimension on the top surface of less than 100 nn.  

The specific restrictions on Atomic Layer Etching (ALE) equipment are detailed under the export control regulations. The BIS has imposed controls on equipment designed or modified for anisotropic dry etching, which includes certain types of ALE equipment. These tools, particularly those using RF pulse-excited plasma, pulsed duty cycle excited plasma, and other advanced techniques, are now restricted due to their critical role in the precise fabrication of high-performance semiconductor devices. The restrictions apply to ALE equipment that is capable of producing high aspect ratio features, which are essential for advanced semiconductor manufacturing, making these tools subject to national security and regional stability controls .

Deposition Technologies:

Equipment designed for the selective bottom-up chemical vapor deposition (CVD) of tungsten fill metal, and other deposition processes such as those for tungsten nitride, tungsten, and cobalt layers. This also includes atomic layer deposition (ALD) equipment designed for area selective deposition of barriers or liners.

The restrictions on Atomic Layer Deposition (ALD) equipment are focused on several key types of equipment essential for advanced semiconductor manufacturing. Specifically, ALD equipment designed for area-selective deposition of barriers or liners using organometallic compounds is controlled. This includes equipment capable of area-selective deposition (ASD) that enables fill metal contact to an underlying electrical conductor without a barrier layer at the fill metal via interface to the conductor. Additionally, ALD equipment designed for depositing tungsten (W) to fill interconnects or channels less than 40 nm wide is also restricted. These restrictions are imposed due to the critical role these technologies play in the precision required for the fabrication of next-generation semiconductor devices.

These technologies are controlled under ECCNs (Export Control Classification Numbers) such as 3B001 and related classifications, and are subject to national security (NS) and regional stability (RS) controls.

The specific materials, chemicals, or precursors that are being restricted under the new export controls include:

These restrictions reflect the importance of controlling advanced materials that play a crucial role in emerging technologies, particularly those with significant national security implications, i.e., quantum technologies.

Epitaxial Materials: This includes materials with at least one epitaxially grown layer of silicon or germanium containing a specified percentage of isotopically enriched silicon or germanium. These materials are controlled due to their critical role in developing spin-based quantum computers.

Fluorides, Hydrides, Chlorides: Specific chemicals of silicon or germanium that contain a certain isotopic composition are also restricted. These chemicals are essential in semiconductor manufacturing processes, particularly in the development of quantum technologies.

Silicon, Silicon Oxides, Germanium, or Germanium Oxides: These materials, when isotopically enriched, are restricted due to their applications in quantum computing and other advanced technologies. The control extends to various forms such as substrates, lumps, ingots, boules, and preforms . 

* The new export controls introduced by the Bureau of Industry and Security (BIS) are effective as of September 6, 2024. However, there are delayed compliance dates for certain items, allowing businesses until November 5, 2024, to comply with the new requirements, particularly for specific quantum technologies and related equipment. This delayed compliance is intended to give affected parties time to adjust to the new regulations.

Source:

2024-19633.pdf (SECURED) (govinfo.gov)

The AVS ALD ALE 2024 Conference in Helsinki - Record Breaking Attendance and Deposition Speed of ALD

The AVS ALD ALE 2024 conference in Helsinki, Finland, which took place from August 4-7, 2024, attracted significant attention number of delegates (number still pending) and reporting on social media among professionals in the field of atomic layer deposition and etching. Participants and companies highlighted key moments and innovations presented during the conference.

One of the major highlights shared on platforms like X/Twitter was the celebration of the 50th anniversary of Atomic Layer Deposition (ALD), with special recognition given to Dr. Tuomo Suntola, the pioneer of ALD technology. His opening remarks were highly anticipated and well-received, marking a significant milestone in the field.

#ALDALE2024 Plenary Talk provided by Tuomo Suntola with a full house. 50 Years in the making! @AVS_Members pic.twitter.com/9W106TGSWm

— Heather Korff (@HeatherKorff) August 5, 2024

Attendees shared their experiences from the welcome reception and the technical sessions, with many noting the high caliber of presentations and the importance of networking opportunities provided by the event under the tag #ALDALE2024 (#ALDep - Search / X (twitter.com)). Overall, social media posts reflected an as usual vibrant and engaged ALD & ALE community, excited about the advancements and collaborations emerging at AVS ALD 2024 in Helsinki.

The 2024 Chairs for ALD Prof. Mikko Ritala and Prof. Markku Leskelä and for ALE Prof. Fred Roozeboom and Dr. Dmitry Suyatin. In the middle ASM Internationals former CTO Ivo Raaijmakers and on the rigt Dr. Tuomo Suntola, The ALD Inventor himself. LINK

The largest group photo at the ALD/ALE 2024 backdrop by registration - Helsinki University! LINK

A Crowded House for the Plenary by Dr. Suntola. LINK

Congratulations to ALD Innovator Awardee Annalise Delabie also presenting to a full house! LINK

Plenary talk by Ivo Raaijmakers, The leading ALD company ASM International. LINK

Best poster ALD 2024 Award by BALD Engineering. Thermal Ru without desalination by Parmish Kaur. LINK

One of numerous Finnish Sauna Events LINK

ALD Tough Guys and social events. LINK

Additionally, the leading ALD & ALE companies showcased their latest advancements. For example, Lotus Applied Technology drew attention for their presentation on ultra-high-speed ALD film growth, achieving deposition rates of 30 Å/second while maintaining film uniformity. This breakthrough was a trending topic among attendees, reflecting the ongoing innovation in the ALD sector.

Lotus Applied Technology reported: The research on ultra-high-speed spatial Plasma-Enhanced Atomic Layer Deposition (PEALD) introduces a novel approach to separating ALD half-reactions by leveraging a unique plasma-based mechanism. Instead of traditional differential flow and pumping, the process utilizes a gas shroud surrounding the plasma electrode, which facilitates the neutralization of oxidation radicals, preventing interaction with metal precursor vapors within the reactor. This method effectively separates the reactive species and allows for high deposition rates, achieving coating speeds over 25 angstroms per second for SiO₂ films. The process also includes innovations to reduce ozone byproducts, such as using carbon dioxide as the plasma gas and applying an active catalyst in the exhaust path​ (Lotus Applied Technology | Home).

At the end the AVS ALD ALE 2025 was presented: The AVS 25th International Conference on Atomic Layer Deposition (ALD 2025) featuring the 12th International Atomic Layer Etching Workshop (ALE 2025) will be a three-day meeting dedicated to the science and technology of atomic layer controlled deposition of thin films and atomic layer etching. Since 2001, the ALD conference has been held alternately in the United States, Europe and Asia, allowing fruitful exchange of ideas, know-how and practices between scientists. The conference will take place Sunday, June 22-Wednesday, June 25, 2025, at the International Convention Center Jeju (ICC Jeju), Jeju Island, South Korea. ald2025 (avs.org)

ALD Program Chair:
Prof. Han-Bo-Ram (Boram) Lee
(Incheon National University, South Korea)


ALE Program Chair:
Prof. Heeyeop Chae
(Sungkyunkwan University, South Korea)

The 2024 Chairs handing over to the 2025 Chairs in Korea. LINK