MSS Corp Low temp ALD the solution for analyzing extreme ultraviolet photoresist

MSS launches new materials analysis items: "ALD sample preparation" for 5nm ~ 2nm EUV PR & Low-k materials

MSS launches new materials analysis items: "ALD sample preparation" for 5nm ~ 2nm EUV photoresist & Low-k materials process structure and composition analysis! All the loyal customers can still keep ALD sample preparation technical services with the same the price. On the other hand, the customers will be applicable to the quotation of new analysis service items.

[MSS Corp article] Atomic layer deposition (ALD) has attracted considerable attention in integrated circuit (IC) equipment industry in recent years. This is largely due to its superior properties, excellent coating conformity, and controllable coating thickness in single atomic layer, especially when compare to other coating systems.

Today, ALD has turned into a core technology in IC fabrication processes and its significance has become even more pronounced as a result of its advanced fabrication processes, including such modern solutions as 3D FinFET or even future gate-all-around (GAA), along with all other variants where precisely well-controlled coating thickness and thin film conformity in sub-nanometer level are in high demanded.

Apart from the above applications in IC fabrication, ALD can also be used for material analysis. A good example in this regard would be the transmission electron microscope (TEM), where by ALD is used to prepare a protection layer on top of areas of interest (AOI) before TEM lamella preparation. Here, it is well known that TEM lamellas are mainly prepared by focused ion beam (FIB). In order to protect AOI from ion bombardment during FIB milling, an external protection layer on top of AOI is indispensable. The material within this protection layer is generally carbon-based glues or metals, and the layer thickness varies from tens of nanometers up to about 500 nm. This protection layer can be coated on surface of AOIs by spin coaters or deposition systems in a vacuum chamber.

Now, depending on coating mechanisms, sample temperature and ion bombardment effects are two main factors that should be considered in order to prevent structures of AOI being altered or damaged during coating processes. For older technology nodes (bigger than 28 nm node), such coating can be easily achieved with wider preparation windows. This is because both the material and structure of AOI are relatively robust and stable. Generally speaking, coating with normal preparation conditions leads to no obvious structural changes or damages of the AOI when observing TEM results.

In terms of advanced technology nodes (below 16 nm node), continuous shrinkage of critical dimension (CD) along with the fact that many new materials are now involved in the fabrication processes are important factors to consider. For instance, extreme ultraviolet (EUV) photoresist (PR) has become one of the most crucial materials used in fabrication processes of 7 nm (and below) node FinFET and future GAA. However, it has been widely reported that EUV PR is extraordinarily fragile and highly sensitive to temperature and ion (both polarities). Damaged or deformed AOIs are expected to be found by traditional coating for older technology nodes, and pristine structures no longer exist for further analysis.

Coating conformity can also be problematic for structures with smaller CDs, such as vias or trenches, when using traditional methods. Extrinsic pinholes or bubbles are expected to be formed before vias or trenches being fully filled with the coating material. These unwanted artifacts could lead to possible difficulties in terms of preventing curtain effect during FIB milling and afterwards when it comes to TEM data interpretation.

To solve all of the above listed challenges, MSS proposes an innovative approach – utilizing a low-temperature vacuum ALD approach to prepare the protection layer on surface of AOIs. Because of its growth mechanism, ALD has an excellent coating conformity, so it is perfectly fitted for coating materials into vias, trenches, or other structures with smaller CDs.

When it comes to preventing damages from FIB milling and following TEM observation (high-energy electron damages), a thicker protection layer is preferred – at least 50 nm in thickness. This is because the thick protection layer is like a powerful armor and has a strong resistance to FIB milling and high-energy electron bombardment. Depending on surface properties of AOIs and analytic purposes, different protection materials can be prepared. Most importantly, despite varieties of protection materials, the sample temperature must always be kept at a low temperature throughout preparation – only a bit higher than room temperature, but certainly well below the one utilized in traditional coating systems. It is crucial, especially for EUV PR because all these steps have to ensure EUV PR stays intact throughout the whole analysis flow and precise results can be delivered.

Figure 1. a-d TEM images of PR structures. Two different types of PR structures were utilized a, b and c, d. The protection layers in a and c were prepared by the traditional coating and those in b and d were prepared by MSS ALD coating. In a and c, obviously, the PR structures were damaged or altered by comparing with those in b and c, see the areas marked by green arrows.

Figures 1a and 1c exhibit TEM images taken from two different PR samples. Their protection layers were all prepared by the traditional coating method. Poor coating conformity can be observed, especially in Fig. 1c. For comparison, an MSS low-temperature vacuum ALD has been utilized on another two samples with the same structures and materials as Figs. 1a and 1c. The TEM images are shown in Figs. 1b and 1d, respectively. From these TEM images, it is easy to see the PR structures prepared by the traditional coating have been damaged or modified, especially the areas marked by green arrows, with certain degree by comparing with the ones prepared by MSS ALD.

The question here now becomes how best to prove the low-temperature vacuum ALD coating has no effects on modifying PR structures as shown in Figs.1 a and 1c. To answer this question, we utilized one of our niche analyses, non-coating high-resolution SEM, to observe the pristine sample before ALD coating and the result is shown in Fig. 2a. The same sample was then coated with MSS ALD followed by FIB milling and TEM observation, and the result is shown in Fig. 2b. The fact that the PR structure shown in Fig. 2a is consistent with the one shown in Fig. 2b observed by TEM strongly suggests the PR structure does not need to be altered or damaged with our ALD preparation.

Figure 2. a High-resolution non-coating SEM image of the PR structure. b TEM image of the PR structure, the same structure as a and the protection layer was prepared by MSS ALD coating. By comparing with these two images, the PR structures stay the same after the ALD coating.

In conclusion, we have successfully demonstrated that MSS’s low-temperature vacuum ALD can be utilized for preparing a protection layer on EUV PR in order to prevent damages from FIB milling and TEM observation. Such sample protection can be applied to other fragile samples as well, and the concept can be extended to other purposes not only in material analysis but failure analysis or even surface analysis.

MSS’s theory on utilizing a low-temperature vacuum ALD for sample protection has been patented in 2020. We believe more and more samples will need such technology in the near future.

Two days of Particle Atomic Layer Deposition and advanced surface engineering technique

ALD to take over more and more as CVD and spin-on processes no longer are viable for 3D NAND

EE Times reports [LINK] about the recently announced Striker FE from Lam Research, an enhanced atomic layer deposition (ALD) platform addresses semiconductor manufacturing challenges for 3D NAND as well as DRAM. It employs advanced dielectric gapfill technology the company has dubbed “ICEFill” for filling 3D NAND and DRAM structures — as well as logic devices — in emerging nodes. 

Lam Research’s recently announced Striker FE enhanced atomic layer deposition (ALD) platform addresses semiconductor manufacturing challenges for 3D NAND as well as DRAM

Lam Research Striker FE - Key applications (LINK):

• Gapfill dielectrics
• Conformal liners
• Patterning spacers and masks
• Hermetic encapsulation
• Etch stop layers
• Optical films

The need for gapfill methods isn’t new, said Aaron Fellis, vice president and general manager of Dielectric ALD products, but the traditional ones no longer meet today’s needs, especially as 3D NAND is stacked higher. “They’re so tall and they have a number of different features that get etched through them to enable the integration of different steps,” he said. “Ultimately, they need to get filled back up with a dielectric material, most commonly silicon oxide.”

Legacy techniques, such as chemical vapor deposition, diffusion/furnace, and spin-on processes that are normally used as gapfill for semiconductor manufacturing are no longer viable for 3D NAND, Fellis said, due to trade-offs between quality, shrinkage, and gapfill voids. “They tend to shrink and distort the actual structure that the customer is building and designing.”

According to Risto Puhakka, president of VLSIresearch, Lam Research is a dominant player for ALD technology, and the demands of its technology reflect those placed on memory. It’s all about increasing density for applications, such as artificial intelligence, that require more bits while keeping costs the same, and that includes gapfill capabilities as the memories such as 3D NAND are stacked higher, he said. “The stacking becomes more and more challenging from the manufacturing perspective, but the chip makers themselves get it a little bit little anxious about how much they have to spend.” Sticking with a known material such as silicon oxide adds some predictability because it’s well understood

But just as 3D NAND stacking will eventually hit limits, so will the gapfill techniques and ALD technology, added Puhakka. “It has its own roadmap and limitations.”

Chipmetrics Oy commercialises 3D test chip for ALD developed by VTT

The PillarHall test chip for analysing 3D thin film structures is ready for market. Chipmetrics Oy, a spin-off of VTT, is now starting to commercialise the solution. The test chip enables the production of smaller nanostructures and components. This opens up new opportunities for the development of semiconductors, memory circuits and smart devices, among others.

3D manufacturing and integration are megatrends in the semiconductor industry, as they can be used to improve the performance and energy efficiency of transistors and memory circuits. New micro-scale structures and materials as well as shrinking geometry are challenges for semiconductor manufacturers because they require process equipment, measurement and testing developed for 3D. PillarHall is the solution to these challenges.

Large global market

Artificial intelligence is being integrated everywhere, and intelligent transport, data centres and medical technology, among others, are affecting on people's lives. Components are now required to be more reliable than ever before, and more measurement and testing is needed to this end. The PillarHall test chip is suitable for the reliable, fast and cost-effective comparison of manufacturing processes of thin film structures. It can be used to measure the conformality of the thin film process, i.e. the ability to coat a 3D object evenly. 

"The PillarHall disposable test chip can be used to compare different 3D thin film processes and reactors. The method is exceptional, as typically measurements have been made directly from the processed wafers using demanding and expensive measuring devices. The test chip can be used to accelerate process development and also monitor production in the future,” says Chipmetrics founder, Dr. Mikko Utriainen.

"VTT has patented the unique structure of the test chip and developed manufacturing methods for the production of test chips. This provides a good technological basis for the growth of Chipmetrics in the global market,” says Tauno Vähä-Heikkilä, Vice President of Microelectronics, VTT.

Manufacturing to continue at Micronova

The test chip is the result of deep technological expertise: its background is the leading-edge research in atomic layer deposition (ALD) in Finland and VTT's experience in MEMS manufacturing processes. The test chip has been developed by VTT through various research projects since 2013. The development has taken place at Micronova, a unique, collaborative research, development and production environment that combines research and industry. In addition to VTT and Aalto University, some 20 companies operate in Micronova.

"With my experience in business development at VTT and 14 Research to Business projects, I am familiar with the challenges of a research-oriented start-up for an academic entrepreneur. PillarHall’s journey has so far been exceptionally successful in many ways. Its unique business model and product, market, demand, customer feedback, sales channels and scalability are all very promising,” says Utriainen.

The initial market focus of the test chip is in ALD. In addition to ALD equipment and process developers, component manufacturers have shown great interest in the test chip. The solution can also be used to develop any other thin film process technology to meet 3D requirements. 

VTT has already piloted the test chip on the international market. The commercialisation of this technology will further boost development, and Chipmetrics indeed aims to create a global business. ALD technology is widely used in many high-tech sectors. The PillarHall test chip is an important demonstration of Finland's strong expertise in ALD, and it strengthens our position in the areas of application of this technology.

High-quality HfS2 2D-material by ALD at 100°C

A high-quality 2D-material by #ALDep at 100°C! Yuanyuan's very systematic and complete study of the well-behaved surface chemistry performed in collaboration with 7 other groups @FAU_Germany is published in Adv. Mater. Interfaces:https://t.co/Y9g1RPsdTx pic.twitter.com/dW8bG0BHAD

— CTFM lab (@CtfmLab) December 6, 2020

AtomicLimits launch picture database for Atomic Level Processing

AtomicLimits Now serving the community with an image library of Atomic Scale Processing (ALD, ALE etc.) and its applications - A large and expanding set of free to use high quality images generated at TU Eindhoven

LINK: https://www.atomiclimits.com/2020/11/25/introducing-the-atomiclimits-image-library-a-central-place-to-find-and-re-use-figures/

PICOSUN® Sprinter launch disrupting fast batch ALD on 300 mm wafers at EFDS ALD for Industry 2020

ESPOO, Finland, 2nd December 2020 – Picosun Group, the leading supplier of AGILE ALD® (Atomic Layer Deposition) thin film coating solutions for global industries, has launched Sprinter, a brand new, fully automated high throughput ALD production module for 300 mm wafers. Barrier, high-k and other films are deposited in Sprinter with perfect ALD for semiconductor (e.g. emerging memory, transistor, capacitor), display, and IoT component applications.

In Sprinter, single wafer film quality and uniformity are upscaled to fast batch processing with the highest reliability and repeatability(*).

Compared to vertical furnace reactors typically used for batch ALD processing, Sprinter provides higher film quality with lower thermal budget, so it is suitable also for temperature-sensitive devices.

Sprinter combines very fast process times with smaller batch sizes than in vertical furnaces, which allows greater production flexibility and minimized risk without sacrificing throughput.

The core of the Sprinter is its disruptively designed reaction chamber, where fully laminar precursor flows ensure perfect ALD deposition with no parasitic CVD growth. This minimizes the need for system maintenance.

“PICOSUN® Sprinter meets directly the challenges in high volume ALD manufacturing on 300 mm wafers. We are happy to unveil this product to our new and existing customers in 300 mm semiconductor markets, and offer them a truly disruptive, modern alternative to old technologies in batch ALD manufacturing,” says Mr. Jussi Rautee, CEO of Picosun Group.

SEMI S2/S8 certified PICOSUN® Sprinter module can be integrated to customer’s manufacturing line or cluster. It is suitable also for single wafer manufacturing lines as it does not disturb the process flow. Sprinter is run with Picosun’s new, proprietary PicoOS™ operating system and process control software.

“Together with Sprinter, we are launching also our PicoOS™ operating system. Own operating system and process control software, developed by our in-house software team, means the highest control precision and accuracy, the fastest service times, and the best reliability and quality for our customers,” continues Rautee.

Full stack PicoOS™ software allows control, operation and configuration of PICOSUN® ALD equipment – either standalone systems or full production clusters – via one unified, intuitive, and user-friendly graphical HMI and ensures smooth connection between the system and the customer’s factory automation via SECS/GEM protocol.

Sprinter is available for process demos at Picosun facilities. Sprinter module sales starts in January 2021 and full Sprinter cluster with several ALD modules, central vacuum wafer handling unit and EFEM is available later in spring 2021.

Picosun launches PicoOS™, a unified control software for PICOSUN® ALD modules and clusters

ESPOO, Finland, 2nd December 2020 – Picosun Group, leading provider of AGILE ALD® (Atomic Layer Deposition) thin film coating solutions for industrial manufacturing, presents PicoOS™, the new, full stack operating system and process control software for PICOSUN® ALD equipment.

“PicoOS™ brings PICOSUN® ALD equipment control to the modern era. It is designed for wafer fabs and industrial environments where transition to Industry 4.0 is ongoing. Data-driven PicoOS™ enables future production solutions where machine learning, artificial intelligence, internet-of-things, and other new digital inventions are utilized for optimum industrial efficiency,” says Dr. Jani Kivioja, CTO of Picosun Group.

Picosun’s proprietary PicoOS™ software combines individual ALD module, wafer handling and transfer system, and instrumentation control under one common graphical HMI (human-machine interface). This ensures easy, intuitive and user-friendly operation, maintenance, and configuration of the whole PICOSUN® ALD cluster.

PicoOS™ enables full factory integration via SECS/GEM protocol, process and system data logging down to 20 ms rate, and real-time export of all data for continuous monitoring and further analysis.

PicoOS™ operating system is specifically developed by Picosun’s own in-house software team for the company’s fully automated production ALD systems Morpher and Sprinter, and it will be implemented in all future PICOSUN® ALD tool platforms.

“PicoOS™ is designed to ensure the highest control precision and accuracy, the fastest service times, and the best user experience for our customers. Having in-house control over all features and sub-components of our PICOSUN® ALD solutions is a key part of our holistic service model,” continues Kivioja.

PicoOS™ has freely configurable and scalable editor for ALD process recipe and processing job creation and storage, and recipes can be edited or new ones created any time during the ALD system operation. Configurable user levels and safety logic, instrumentation and interlocks guarantee safe use in day-to-day operations, and allow full access for tool management in maintenance situations. Maintenance procedures are sped up by specific clean-up and maintenance sequences inbuilt in the software.

The global semiconductor market is projected to grow by 8.4 percent in 2021 according to WSTS Forecast

WSTS has released it latest forecast for the global semiconductor industry. The Worldwide Semiconductor Market is forecasted to be US$ 433 billion in 2020 - an increase of 5.1 percent from 2019- growth in all major product categories, except Optoelectronics and Discrete Semiconductors. The largest growth contributors are Memory with 12.2 percent, followed by Sensors with 7.4 percent. In 2020, Americas and Asia. Pacific regions are expected to grow.

2021, the global semiconductor market is projected to grow by 8.4 percent, driven by double-digit growth of Memory and Optoelectronics.

LINK: https://www.wsts.org/esraCMS/extension/media/f/WST/4820/WSTS_nr-2020_11.pdf

SAMCO launch ALD system for MEMS and SiC and GaN power devices

Samco just released an open-load ALD system "AL-1" with a focus on gate insulator formation of GaN and SiC powerdevices, passivation layer deposition, as well as the MEMS field. This report shows the AL-1's system specifications and several pieces of performance data.

Report: Atomic Layer Deposition (ALD) System for Power Device Applications LINK

Ferroelectric Memory GmbH (FMC) Raises $20 M to Accelerate Next-Generation Memory for AI, IoT, Edge Computing, and Data Center Applications

[Press release] Ferroelectric Memory GmbH (FMC), the ferroelectric hafnium oxide technology leader, today announced that it has completed a $20 million Series B funding. The round of financing was led by the new investors M Ventures and imec.xpand, with participation of SK hynix, Robert Bosch Venture Capital, and TEL Venture Capital. The lead investor of Series A eCapital also participated in this round. The new set of investors aims to support FMC throughout the whole semiconductor value chain to bring FMC's advanced ferroelectric memory technology to market. The company plans to expand its team in Dresden, as well as to start international expansion, including into the US and Asian markets. 

"The rise of AI, IoT, Big Data, and 5G are demanding next-generation memory solutions that enable superior speed and ultra-low power consumption, while being compatible with leading-edge CMOS logic processes guaranteeing reduced manufacturing costs," said Ali Pourkeramati, CEO of FMC. "We have strong interest from customers and development partners for our advantages in fast access, program and erase speed, best-in-class ultra-low energy budget, ease-of-integration into existing manufacturing processes, and low manufacturing costs. This funding will speed up the commercialization of our ferroelectric field-effect transistor (FeFET) and capacitor (FeCAP) technology into exponentially increasing markets in the AI, IoT, embedded memory, and high-performance stand-alone data center sectors."

FMC has already made significant progress in the development of its non-volatile memory technology promising to offer superior performance compared with state-of-the-art and emerging memory solutions. It is currently working closely with major semiconductor companies, as well as with foundries in the US, Europe, and Asia. 

Transformation of amorphous hafnium oxide into its known crystalline states and into the newly discovered ferroelectric phase (Figure from www.ferroelectric-memory.com)

Technological Advantages

FMC's memory technology uses the ferroelectric properties of crystalline hafnium oxide (HfO2). HfO2 in its amorphous form is already the gate insulator material of every CMOS transistor ranging from planar to FinFET. FMC's patent-protected technology makes it simple to transform amorphous HfO2 into crystalline ferroelectric HfO2. This way, every standard CMOS transistor and capacitor can be turned into a non-volatile memory cell, a ferroelectric field-effect transistor (FeFET) or capacitor (FeCAP).

In addition to its high speed, ultra-low power, CMOS logic compatibility, reduced manufacturing cost, and extreme temperature stability, FMC's technology provides complete magnetic immunity and high radiation resistance. FeFETs and FeCAPs can be integrated into CMOS production lines using existing equipment without the need for extra capital expenditures.

About Ferroelectric Memory GmbH (FMC)

FMC has developed the most advanced ferroelectric hafnium oxide memory technology to deliver leading-edge non-volatile memory for future electronics and computing innovation. The company was incorporated in 2016 and is currently working with major semiconductor companies for its embedded and stand-alone memory solution. Its ferroelectric field-effect transistor (FeFET) and capacitor (FeCAP) technology is simple to integrate, fast, low-power, and scalable, and has high endurance with decades of data retention, suitable for a broad range of AI, IoT, edge, data center, and embedded applications.

Intel remains in the lead in 2020 semiconductor sales

IC Insights’ November shows the forecasted top-25 semiconductor suppliers in 2020. Seven top-15 semiconductor suppliers forecast to show ≥22% growth this year with Nvidia expected to post a huge 50% increase. The top-15 companies semiconductor sales are broken out into IC and O-S-D (optoelectronic, sensor, and discrete) device categories for 2019 and 2020. The forecasted 2020 top-15 semiconductor supplier ranking includes eight suppliers headquartered in the U.S., two each in South Korea, Taiwan, and Europe, and one in Japan.

Intel remains No 1. followed by Samsung and TSMC. 2020 show a very high growth for Fabless companies Qualcomm, Nvidia, MediaTek, Apple and AMD.

The Memory segment (DRAM and Flash) is led by SK Hynix +14% followed by Samsung +9% (incl. foundry) and Micron is down by -3%.

Please read the full IC Insights report here: LINK

Applied Materials will regain its No. 1 ranking in the semiconductor equipment market in 2020 from ASML

According to recent published data by The Information Network (Seeking Alpha LINK), Applied Materials will regain its top ranking in the semiconductor equipment market in 2020 from ASML. Fab equipment spend in 2020 was enhanced from pull-ins of sales into China and Taiwan, with 3Q QoQ increases of 22.5% and 36.2%, respectively.

As is well known ASML and Applied Materials does not compete in their  business segments, Lithography (ASML) resp. Deposition & Etch (Applied Materials). Applied Materials has a number 1 spot in PVD, CVD, Epi, CMP and Implant/Doping. However, business segments where Applied Materials so far has not been successful to reach a top 3 position in the past years include:

• Atomic Layer Deposition
• MOCVD
• Furnace 
• Dielectric Etch  
• Spray Processing
• Dielectric Etch (including ALE)
• Wet Stations

As is known, Applied Materials have several times made very serious attempts to enter the ALD segment, but failed several times to compete with ASMI, Tokyo Electron and the South Korean OEMs (Jusung Engineering, Wonik IPS and Eugene Technology. In 2019 Applied Materials announced that it will acquire Japanese Kokusai (LINK) but the final agreement is yet not settled. If successful Applied will have an opportunity to kill 2 birds with one stone:

1. Move in to top 3 spot in ALD

2. Take number 2 spot in Furnace business

Table based on information and own assumptions in the article (Seeking Alpha LINK)

Beneq ALD Stories Episode 4 - The story about the BALD Engineering Blog

I

n this episode we speak to Dr. Jonas Sundqvist, founder of BALD Engineering Blog and a senior researcher and consultant of ALD/ CVD processes.

Intel to present 3D stacked Nanoribbon Transistors for Continued Moore’s Law Scaling at IEDM 2020

Intel to present stacked gate-all-around FET (GAA-FET) technology, i.e., a complementary FET (CFET) at IEDM2020. In CFETs, the idea is to stack both nFET and pFET wires on each other. A CFET could stack one nFET on top of a pFET wire, or two nFETs on top of two pFET wires. This ‘folding’ of the nFET and pFET eliminates the n-to-p separation bottleneck, reducing the cell active area footprint (LINK). Please find the announcement below:

Home-2020 - IEDM 2020 ieee-iedm.org IEDM Conference 2020. To Be Held Virtually December 12-18. The on demand portion of the conference will begin on December 5th. Intel to present 3D stacked Nanoribbon Transistors for Continued Moore’s Law Scaling: 

Stacked NMOS-on-PMOS Nanoribbons: From planar MOSFETs, to FinFETs, to gate-all-around (GAA) or nanoribbon devices, novel transistor architectures have played a critical role in driving performance predicted by Moore’s Law. Intel researchers will describe what may be the next step in that evolution: NMOS-on-PMOS transistors built from multiple self-aligned stacked nanoribbons. This architecture employs a vertically stacked dual source/drain epitaxial process and a dual metal gate fabrication process, enabling different conductive types of nanoribbons to be built so that threshold voltage adjustments can be made for both top and bottom nanoribbons. The approach combines excellent electrostatics (subthreshold slope of <75 mV/dec) and DIBL (<30mV/V for gates ≥30nm) with a path to significant cell size reduction due to the self-aligned stacking. These devices were used to build a functional CMOS inverter with well-balanced voltage transfer characteristics. (Paper #20.6, “3-D Self-Aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore’s Law Scaling,” C.-Y. Huang et al, Intel) 

Paper #20.6, “3-D Self-Aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore's Law Scaling,” C.-Y. Huang et al, Intel

Paper Information (IEDM 2020) : LINK

Figures from IEDM 2020 Press briefing Material -Press kit : LINK

In the images above:

·        (1) shows the evolution of transistor architectures from planar, to FinFETs, to nanoribbons and to a 3D CMOS architecture.

·        (2) (a) shows a 3D schematic diagram of stacked CMOS Si nanoribbon transistors with NMOS on PMOS, (b) describes the process flow; (c) is a TEM image of a stacked multiple-nanoribbon CMOS inverter with a 40-nm gate length and inner (V_ss) and outer (V_cc) contacts, a common gate input (V_IN) and an inverter output node (V_OUT); while (d) is a TEM image of two Si NMOS nanoribbons atop 3 Si PMOS nanoribbons.

·       (3) (a) is a process flow of the vertically stacked dual S/D EPI process, while (b) shows P-EPI selectively grown on the bottom three nanoribbons, (c) shows N-EPI selectively grown on the top two nanoribbons, and (d) features TEM and EDS images showing selective N-EPI and P-EPI growth on the stacked nanoribbon transistors.

·       (4) (a) is a process flow of the vertically stacked dual metal gate process; (b) is a TEM image and (c, d) are EDS images of the dual metal gate with N-WFM (WFM = work function metal) on the top two nanoribbons and P-WFM on the bottom three nanoribbons.

Japanese researchers enable high thru put conformal CVD for SiC on Silicon wafer integration

As reported by ACS (LINK) New, concise method proposed for conformal chemical vapor deposition using sacrificial layers (SLs). SLs are porous membranes that filter high sticking-probability species, while allow the passage of low ones.

This is a really clever by researchers at University of Tokyo and IHI Corporation for CVD to compete with ALD on conformality and keeping a high deposition rate and at the same time produce bulk material like SiC on Si for larger wafer diameter.

Figure from ACS Twitter post (LINK)

Reference:

Porous Membranes as Sacrificial Layers Enabling Conformal Chemical Vapor Deposition Involving Multiple Film-Forming Species
Kohei Shima, Yuichi Funato, Noboru Sato, Yasuyuki Fukushima, Takeshi Momose, and Yukihiro Shimogaki
ACS Appl. Mater. Interfaces 2020, 12, 45, 51016–51025
Publication Date:October 30, 2020
https://doi.org/10.1021/acsami.0c14069