The website for the 2020 Area Selective Deposition Workshop is now live!

Developments in nanoelectronics and nanoscale surface modification have continued to drive the need for more elegant and reliable bottom-up area selective deposition (ASD) strategies. Most notably, the semiconductor industry has relentlessly pursued sub-10 nm transistor fabrication for next-generation devices, an endeavor that increasingly relies on selective deposition techniques to facilitate proper material alignment. However, other fields beyond traditional transistor fabrication have also found potential applications for selective deposition. Mixed-material catalysts have consistently shown the benefits of having site-specific material growth, but new optical devices and materials for energy storage have also contributed to an increased focus on developing new strategies for ASD.

Website: https://asd2020.avs.org/

The website for the 2020 Area Selective Deposition Workshop is now live! Come join us next April 2-3 at Stanford to learn about the cutting edge science being performed around the world! #Area_Selective #ASD20 #ALDep #CVDep https://t.co/MJxTgGECkf

— Bent Group (@BentGroup) September 11, 2019

In an effort to help facilitate the progression of ASD techniques, Stanford University is proud to host the 5th Area Selective Deposition Workshop (ASD 2020), held on April 2–3, 2020 in Palo Alto, California USA. Located in the heart of Silicon Valley, this year’s workshop will act as a central event for sharing and discussing the newest developments in ASD by gathering leading experts from both academia and industry. Attendees can expect to participate in talks regarding fundamental challenges related to recent developments in ASD, applications for ASD in next-generation technology, emergent processes for implementing ASD techniques, and new perspectives on metrological and characterization strategies for further understanding persistent mechanistic challenges.

Based on the success of the previous workshops, ASD 2020 will consist of two days of presentations by invited and contributing speakers, as well as a banquet reception and poster session at Stanford University. We hope that guests will also have time to experience some of the local attractions and natural beauty that the Bay Area has to offer!

Scientists Come up with ALD Technique to Repair Atom-sized Graphene Defects

As reported by The Korea Bizwire: Ulsan National Institute of Science and Technology said on September 10 that its College of Natural Sciences professor Kim Kwanpyo, jointly with Lee Han-Bo-Ram (Incheon National University), and Zhenan Bao and Stacey F. Bent (Stanford University), succeeded in developing a technique to repair graphene’s line defects by selectively depositing metal.

Graphene is pure carbon in the form of a very thin, nearly transparent sheet, one atom thick, with excellent mechanical, electrical properties. In order to apply graphene to photovoltaic cells, displays, or sensors, it must be made in large scale.

But graphene tended to crack and produce boundary lines, making it difficult to maintain excellent material properties. To address this problem, there have been attempts to deposit metal on graphene surface, which was not effective as the metal deposition was not selective enough to defective parts.

By using platinum, the research team successfully demonstrated the selective deposition of metal at chemical vapor deposited graphene’s line defects, notably grain boundaries, by atomic layer deposition. As a result, the team proved three times improved electrode and hydrogen gas sensors at room temperature. The research outcome was reported on the September 2 issue of Nature Communications (see abstract below).

Kim Kwanpyo, the principal author, said, “We used platinum in the latest experiment. But other metals such as gold and silver may be used in subsequent experiments to repair graphene defects and the applications may be expanded to other areas.”

 

Selective metal deposition at graphene line defects by atomic layer deposition

Kwanpyo Kim, Han-Bo-Ram Lee, Richard W. Johnson, Jukka T. Tanskanen, Nan Liu, Myung-Gil Kim, Changhyun Pang, Chiyui Ahn, Stacey F. Bent, & Zhenan Bao

 

One-dimensional defects in graphene have a strong influence on its physical properties, such as electrical charge transport and mechanical strength. With enhanced chemical reactivity, such defects may also allow us to selectively functionalize the material and systematically tune the properties of graphene. Here we demonstrate the selective deposition of metal at chemical vapour deposited graphene’s line defects, notably grain boundaries, by atomic layer deposition. Atomic layer deposition allows us to deposit ​Pt predominantly on graphene’s grain boundaries, folds and cracks due to the enhanced chemical reactivity of these line defects, which is directly confirmed by transmission electron microscopy imaging. The selective functionalization of graphene defect sites, together with the nanowire morphology of deposited ​Pt, yields a superior platform for sensing applications. Using ​Pt–graphene hybrid structures, we demonstrate high-performance hydrogen gas sensors at room temperature and show its advantages over other evaporative ​Pt deposition methods, in which ​Pt decorates the graphene surface non-selectively.

 

 

Selective ​Pt growth by ALD on one-dimensional defect sites of polycrystalline CVD graphene.

 

Call for Abstracts - The 5th AVS Area Selective Deposition Workshop (ASD 2021)

Developments in nanoelectronics and nanoscale surface modification have continued to drive the need for more elegant and reliable bottom-up area selective deposition (ASD) strategies. Most notably, the semiconductor industry has relentlessly pursued sub-10 nm transistor fabrication for next-generation devices, an endeavor that increasingly relies on selective deposition techniques to facilitate proper material alignment. However, other fields beyond traditional transistor fabrication have also found potential applications for selective deposition. Mixed-material catalysts have consistently shown the benefits of having site-specific material growth, but new optical devices and materials for energy storage have also contributed to an increased focus on developing new strategies for ASD.

LINK: https://asd2021.avs.org/

In an effort to help facilitate the progression of ASD techniques, The University of Texas at Austin University is proud to host the 5th Area Selective Deposition Workshop (ASD 2021), which will be held on April 6-8, 2021. The Area Selective Deposition Workshop scheduled for April 2-3 (ASD 2020) was postponed in March 2020 due to public health concerns relating to the coronavirus disease (COVID-19) and was later cancelled in anticipation of ASD 2021. ASD 2021 retains much of the character of previous workshops and what was intended for ASD 2020, albeit in a virtual format. This year’s workshop will act as a central event for sharing and discussing the newest developments in ASD by gathering leading experts from both academia and industry. Attendees can expect to participate in talks regarding fundamental challenges related to recent developments in ASD, applications for ASD in next-generation technology, emergent processes for implementing ASD techniques, and new perspectives on metrological and characterization strategies for further understanding persistent mechanistic challenges.

Self-Correcting Process for High Quality Patterning by Atomic Layer Deposition

Self-Correcting Process for High Quality Patterning by Atomic Layer Deposition

Fatemeh Sadat Minaye Hashemi, Chaiya Prasittichai, and Stacey F. Bent

ACS Nano, 2015, 9 (9), pp 8710–8717

DOI: 10.1021/acsnano.5b03125

Author Fatemah Hashemi discusses their new atomic layer deposition (ALD) approach, which combines selective etching with selective depositon. Read the related ACS Nano article at http://pubs.acs.org/doi/abs/10.1021/a...

Nanoscale patterning of materials is widely used in a variety of device applications. Area selective atomic layer deposition (ALD) has shown promise for deposition of patterned structures with subnanometer thickness control. However, the current process is limited in its ability to achieve good selectivity for thicker films formed at higher number of ALD cycles. In this report, we demonstrate a strategy for achieving selective film deposition via a self-correcting process on patterned Cu/SiO2 substrates. We employ the intrinsically selective adsorption of octadecylphosphonic acid self-assembled monolayers on Cu over SiO2 surfaces to selectively create a resist layer only on Cu. ALD is then performed on the patterns to deposit a dielectric film. A mild etchant is subsequently used to selectively remove any residual dielectric film deposited on the Cu surface while leaving the dielectric film on SiO2 unaffected. The selectivity achieved after this treatment, measured by compositional analysis, is found to be 10 times greater than for conventional area selective ALD.

Extended deadline for ASD 2019 Workshop

We are pleased to announce that the deadline for ASD abstract submission has been extended until Sunday 10 February. This means you have an extra ten days to finalize your abstracts and submit them at: abstract@asd2019-workshop.org

 

 

The workshop will feature the following invited speakers:

Rudy J. Wojtecki (IBM, USA), Katie Nardi (LAM Research, USA), Kanda Tapily (TEL, USA), Chi-I Lang (AMAT, USA), John Tolle (ASM, USA), Han-Bo-Ram Lee (Incheon National University), Gregory Parsons (NC State University, USA), Matthias Minjauw (University of Gent, Belgium), Necmi Biyikli (University of Connecticut, USA), Mohamed Saib (IMEC, Belgium), Efrain A. Sanchez (IMEC, Belgium), John G. Ekerdt (University of Texas, USA).

The workshop will cover a wide range of topics, including the following:

Area selective epitaxy and area selective chemical vapor deposition: processes and mechanisms, defects control

Intrinsic selectivity of ALD processes: nucleation and interface studies, chemical selectivity in surface reactions, competitive adsorption, precursors design, modeling of surface reactions

Methods for area selective activation / deactivation: use of inhibitors (self-assembled monolayers, polymers), plasma-/beam-induced activation

Processes and mechanisms for area selective atomic layer deposition: deposition of metals or dielectrics, thermal/plasma enhanced ALD, 3D or patterned substrates, substrates preparation, sequential deposition/etching,

Metrology and defects control: surface characterization techniques, selective etching of defects

Applications of area selective deposition: semiconductor industry (integration needs of device makers, solutions proposed by the equipment makers), catalysis, energy generation and storage, etc.


On behalf of the organizing committee, it will be our pleasure to welcome you in Leuven.

Andrea Illiberi Program Chair of the 4th ASD workshop

Self-Correcting Process For High Quality Patterning By Atomic Layer Deposition

An interesting publication using ALD for advanced pattering method which is a quite hot topic these days when lithography tools are swelling in all directions and just getting slower - The research is from the Bent Research Group at Stanford University!

Self-Correcting Process For High Quality Patterning By Atomic Layer Deposition.

Minaye Hashemi FS, Prasittichai C, Bent SF.

ACS Nano. 2015 Jul 16. [Epub ahead of print]

 

 

Schematic demonstrating self-aligned patterning through a combination of selective deposition (using ODPA SAM blocking layer on Cu oxide) and selective removal (using acid) of dielectric material. (Graphical abstract ACS Nano, Article ASAP,DOI: 10.1021/acsnano.5b03125)

Nanoscale patterning of materials is widely used in a variety of device applications. Area selective atomic layer deposition (ALD) has shown promise for deposition of patterned structures with sub-nanometer thickness control. However, the current process is limited in its ability to achieve good selectivity for thicker films formed at higher number of ALD cycles. In this report, we demonstrate a strategy for achieving selective film deposition via a self-correcting process on patterned Cu/SiO2 substrates. We employ the intrinsically selective adsorption of octadecylphosphonic acid self-assembled monolayers on Cu over SiO2 surfaces to selectively create a resist layer only on Cu. ALD is then performed on the patterns to deposit a dielectric film. A mild etchant is subsequently used to selectively remove any residual dielectric film deposited on the Cu surface while leaving the dielectric film on SiO2 unaffected. The selectivity achieved after this treatment, measured by compositional analysis, is found to be ten times greater than for conventional area selective ALD.

Applied Materials launch Selective Tungsten CVD for their Endura(TM) platform

[Applied Materials Blog LINK] Tungsten has been widely used as a gapfill material in middle-of-line (MOL) contacts for its low resistivity and bulk fill characteristics. MOL contacts form the critical electrical link between the transistors and the interconnects. Hence, ensuring low resistivity contacts is crucial for overall device performance.

With continued scaling, however, contact dimensions have decreased to the point at which contact resistance is becoming a bottleneck in realizing optimum device performance. As the cross-sectional area of the contact shrinks, a growing proportion of the volume is occupied by metal liner/barrier and nucleation layers, leaving less volume for the conducting metal fill. In addition, multiple resistive interfaces in the plug contribute to higher contact resistance.

An Applied Materials Endura(TM) Platform equipped with seven Selective Tungsten CVD Volta(R) and 2 pre-clean 300 mm chambers. (Credit: Applied Materials)

The Applied Endura Volta Selective W CVD system offers an integrated materials solution that relieves these adverse effects with a breakthrough in 2D scaling. The system combines surface treatment chambers with selective tungsten deposition chambers. The selective deposition is enabled by both the unique process capabilities of the deposition chambers and the various surface treatments that use specialized chemistries to prepare the underlying metal and dielectrics of the contact to enable bottom-up, metal-on-metal deposition. The selective process eliminates both liner/barrier and nucleation layers to alleviate the bottleneck in device performance, and produces void- and seam-free gapfill.

Cross section of a leading edge Logic processor showing the Source/Drain contacts to the transistors and the metal interconnetcs (Credit: TechInsight, Applied Materials)

As all process steps are performed in an ultra-clean, continuous high-vacuum environment, the integrated materials solution ensures a pristine interface and defect-free contact fill. With the volume of conducting metal maximized, contact resistivity is substantially improved compared to conventional liner/barrier contact fabrication. This lower resistance facilitates higher device density and extends 2D scaling.

The selctive W CVD defect-free contact fill maximizes the volume of conducting metal (right), contact resistivity is substantially improved compared to conventional liner/barrier contact fabrication (left). (Credit: Applied Materials)

Area-Selective ALD : Conformal Coating, Subnanometer Thickness Control, and Smart Positioning

Area-Selective Atomic Layer Deposition: Conformal Coating, Subnanometer Thickness Control, and Smart Positioning

Ming Fang†§ and Johnny C. Ho*†‡§
† Department of Physics and Materials Science, City University of Hong Kong, 83 Tat Chee Avenue, Kowloon, Hong Kong
‡ State Key Laboratory of Millimeter Waves, City University of Hong Kong, 83 Tat Chee Avenue, Kowloon, Hong Kong
§ Shenzhen Research Institute, City University of Hong Kong, Shenzhen, 518057, P. R. China
ACS Nano, Article ASAP
DOI: 10.1021/acsnano.5b05249

 

 

Transistors have already been made three-dimensional (3D), with device channels (i.e., fins in trigate field-effect transistor (FinFET) technology) that are taller, thinner, and closer together in order to enhance device performance and lower active power consumption. As device scaling continues, these transistors will require more advanced, fabrication-enabling technologies for the conformal deposition of high-κ dielectric layers on their 3D channels with accurate position alignment and thickness control down to the subnanometer scale. Among many competing techniques, area-selective atomic layer deposition (AS-ALD) is a promising method that is well suited to the requirements without the use of complicated, complementary metal-oxide semiconductor (CMOS)-incompatible processes. However, further progress is limited by poor area selectivity for thicker films formed via a higher number of ALD cycles as well as the prolonged processing time. In this issue of ACS Nano, Professor Stacy Bent and her research group demonstrate a straightforward self-correcting ALD approach, combining selective deposition with a postprocess mild chemical etching, which enables selective deposition of dielectric films with thicknesses and processing times at least 10 times larger and 48 times shorter, respectively, than those obtained by conventional AS-ALD processes. These advances present an important technological breakthrough that may drive the AS-ALD technique a step closer toward industrial applications in electronics, catalysis, and photonics, etc. where more efficient device fabrication processes are needed.

Highly Selective Directional ALE of Silicon by LAM Research (OPEN ACCESS ARTICLE)

LAM Research, Intel and others are pumping out great publications on Atomic Layer Etching (ALE) at the moment. Here is a good one on Si etchning from LAM Reasearch and I think this is also the first time I come across the term EPC as in "Etching per Cycle" as corresponding to GPC "Growth per Cycle" in ALD. Also the concept of an ALE window is explained. Check out the abstract below or go for the complete article by following the link:

Highly Selective Directional Atomic Layer Etching of Silicon (OPEN ACCESS)

Samantha Tan, Wenbing Yang, Keren J. Kanarik, Thorsten Lill, Vahid Vahedi, Jeff Marks and Richard A. Gottscho

Abstract

Following Moore's Law, feature dimensions will soon reach dimensions on an atomic scale. For the most advanced structures, conventional plasma etch processes are unable to meet the requirement of atomic scale fidelity. The breakthrough that is needed can be found in atomic layer etching or ALE, where greater control can be achieved by separating out the reaction steps. In this paper, we study selective, directional ALE of silicon using plasma assisted chlorine adsorption, specifically selectivities to bulk silicon oxide as well as thin gate oxide. Possible selectivity mechanisms will be discussed. 

As the IC industry approaches sub 10 nm devices, the need for atomic scale fidelity has been recognized. In the field of deposition, atomic layer deposition (ALD) emerged. The driving forces for advancement of ALD were among others conformal deposition in high aspect ratio structures and deposition of dielectrics and metals with atomic layer control. The idea that an analogous technology for removal of material might exist was proposed over 10 years after the discovery of ALD. The number of publications on this so called atomic layer etch (ALE) increased significantly in recent years and now ALE is transitioning from the lab to the fab.

One highly desirable quality of ALE is selectivity. Recently, Hudson et al. verified that a directional oxide ALE process can etch SiO₂ selective to Si₃N₄. Ikeda et al. showed that thermal ALE of germanium can be selective to silicon or SiGe. Thermal etching is isotropic and not directional. Etching of 3D devices requires directionality and selectivity. FinFET gate etching for instance requires overetches of 40 nm and more to clear the silicon between the fins while gate oxide is exposed. As fin heights increase to achieve the required I_on currents while CD's are shrinking further, the amount of overetch is expected to increase even more. During extended plasma exposure, species from the plasma can penetrate into the fin silicon and cause lattice damage and undesired fin recess. This drives the need for new etching approaches such as ALE. 

ALE processes are comprised of single unit steps which repeat in cycles. These single unit steps use the simplest possible chemistry to realize specific surface processes such as activation and removal. In analogy to ALD, ALE single unit steps should have as much self-limitation as possible. Self-limitation or saturation eliminates the influence of transport phenomena which are the root cause of aspect ratio dependent etching or ARDE on a microscopic scale.⁸ On an atomic scale, saturation of the single unit steps should lead to atomic level smoothness of the etching surface.⁵

Another important concept which can be adapted from ALD is the existence of an ideal process window. Figure 1a illustrates the so called “ideal ALD window,” which is defined as the region of nearly ideal ALD behavior between non-ideal regions.³ The graph shows “growth per cycle” or GPC as a function of surface temperature which for chemical surface reactions represents the available energy to overcome reaction barriers. The analogy of an ideal process window for ALE with ion based removal is shown in Fig. 1b. Here, “etch per cycle” or EPC is shown as a function of ion energy. The material to be etched is activated in a first step and the activated layer is removed in a second step by energetic ions. For instance, silicon can be activated by chlorine molecules or radicals and the resulting surface layer of SiCl_x can be removed by low energy noble gas ions. This particular embodiment of ALE is directional since the removal step is directional due to the use of ions that have been accelerated by a plasma sheath or ion beam source. There are other embodiments of ALE as well. For instance, in the absence of directionality in both, the activation and removal step, the result is isotropic ALE. In this case, surface temperature can be used as control variable of the removal step.

Fig. 1. a. Ideal process window for ALD adapted from. Ref. 3 b. Ideal process window for direction ALE. The region called “incomplete removal” in Figure 1b is characterized by ion energies that are insufficient to completely remove the activated surface layer. Under the conditions labeled “ideal ALE window,” the ion energy is chosen to be high enough to remove the activated layer but not the bulk silicon material. A third process regime is labeled “sputtering” and designates a region where the ion energy is high enough to remove bulk material.

The concept of an “ideal ALE window” can be extended to explain etch selectivity. In Fig. 2, material A exhibits an ALE window while material B does not. In the case of material B, the bonding energy of the adsorbed layer is significantly lower than for the bulk material. In this case, the adsorbed species would be removed as atomic species (EPC equals zero) and the removal of the bulk material realized only if the energy reaches the energy needed to sputter the bulk material. If this sputter threshold energy is higher than at least part of the energy range for ideal ALE of material A, high selectivities can be obtained. 

Fig. 2. Schematic of EPC for material A (e.g. silicon) and material B (e.g., silicon oxide) as a function of ion energy.. Hypothetically, infinite etch selectivity can be reached in the energy range that etches material A and not material B.

Hot paper on selective Atomic Layer Etching using fluorination and ligand-exchange reactions

Here is a very recent publication on Atomic Layer Etching (ALE) shared to me by my co-worker at Lund Nano Lab MD Sabbir Ahmed Khan (Now at Aalto University, Finland) - Thank you! The paper is from the group of Steven M. George at CU Boulder and Sematech on selective ALE using fluorination and ligand-exchange reactions - sort of backwards thermal ALD.

For those of you with interest in ALE please remember that the 4th International Atomic Layer Etching Workshop (ALE2017) will be featured at the 17th International Conference on Atomic Layer Deposition, July 15-18, 2017, Denver, Colorado. ALE2017 is chaired by Prof. Steven .M. George and Keren Kanarik from Lam Research.

Selectivity in Thermal Atomic Layer Etching Using Sequential, Self-Limiting Fluorination and Ligand-Exchange Reactions

Younghee Lee^†, Craig Huffman^‡, and Steven M. George^*†§

^† Department of Chemistry and Biochemistry, University of Colorado, Boulder, Colorado 80309, United States

^‡ SUNY Poly SEMATECH, Albany, New York 12203, United States

^§ Department of Mechanical Engineering, University of Colorado, Boulder, Colorado 80309, United States

Chem. Mater., Article ASAP

DOI: 10.1021/acs.chemmater.6b02543

(Figure Shared under Rightsink Account #:   3000915597)

Abstract: Atomic layer etching (ALE) can result from sequential, self-limiting thermal reactions. The reactions during thermal ALE are defined by fluorination followed by ligand exchange using metal precursors. The metal precursors introduce various ligands that may transfer during ligand exchange. If the transferred ligands produce stable and volatile metal products, then the metal products may leave the surface and produce etching. In this work, selectivity in thermal ALE was examined by exploring tin(II) acetylacetonate (Sn(acac)2), trimethylaluminum (TMA), dimethylaluminum chloride (DMAC), and SiCl4 as the metal precursors. These metal precursors provide acac, methyl, and chloride ligands for ligand exchange. HF-pyridine was employed as the fluorination reagent. Spectroscopic ellipsometry was used to measure the etch rates of Al2O3, HfO2, ZrO2, SiO2, Si3N4, and TiN thin films on silicon wafers. The spectroscopic ellipsometry measurements revealed that HfO2 was etched by all of the metal precursors. Al2O3 was etched by all of the metal precursors except SiCl4. ZrO2 was etched by all of the metal precursors except TMA. In contrast, SiO2, Si3N4, and TiN were not etched by any of the metal precursors. These results can be explained by the stability and volatility of the possible reaction products. Temperature can also be used to obtain selective thermal ALE. The temperature dependence of ZrO2, HfO2, and Al2O3 ALE was examined using SiCl4 as the metal precursor. Higher temperatures can discriminate between the etching of ZrO2, HfO2, and Al2O3. The temperature dependence of Al2O3 ALE was also examined using Sn(acac)2, TMA, and DMAC as the metal precursors. Sn(acac)2 etched Al2O3 at temperatures ≥150 °C. DMAC etched Al2O3 at higher temperatures ≥225 °C. TMA etched Al2O3 at even higher temperatures ≥250 °C. The combination of different metal precursors with various ligands and different temperatures can provide multiple pathways for selective thermal ALE.

Applied Materials Releases Selective Etch Tool - The Producer® Selectra™ Etch system

As reported by By Ed Korczynski, Sr. Technical Editor Solid State Technology : Applied Materials has disclosed commercial availability of new Selectra(TM) selective etch twin-chamber hardware for the company’s high-volume manufacturing (HVM) Producer® platform. Using standard fluorine and chlorine gases already used in traditional Reactive Ion Etch (RIE) chambers, this new tool provides atomic-level precision in the selective removal of materials in 3D devices structures increasingly used for the most advanced silicon ICs. The tool is already in use at three customer fabs for finFET logic HVM, and at two memory fab customers, with a total of >350 chambers planned to have been shipped to many customers by the end of 2016.

Fulls story : http://semimd.com/blog/2016/06/29/applied-materials-releases-selective-etch-tool/

Full information as released by Applied Materials can be found here : http://www.appliedmaterials.com/products/producer-selectra-etch

 

The Producer® Selectra™ Etch system introduces unprecedented capabilities for sustaining the momentum of Moore’s Law through further scaling of 3D logic and memory chips. This process can remove target materials with unprecedented selectivity to one or more films. (appliedmaterials.com)

Rapid and Selective Deposition of Patterned Thin Films on Heterogeneous Substrates via Spin Coating

[Tokyo Electron] Researchers at UC Santa Barbara along with TEL and SRC have collaborated to develop new methods for selective spin coating. With wide-ranging applications in the future of semiconductor patterning as device makers are challenged to build more complex transistors and simultaneously lower costs. 

They demonstrate that accurate control over the process parameters allows incomplete trichlorosilane self-assembled monolayers (SAMs) to induce spin dewetting on both homogeneous (SiO₂) and heterogeneous (Cu/SiO₂ or TiN/SiO₂) surfaces. Under optimal conditions, spin dewetting on line–space patterns results in the selective deposition of polymer over regions not functionalized with SAM.  

Source: "Rapid and Selective Deposition of Patterned Thin Films on Heterogeneous Substrates via Spin Coating"  LINK

IBM Zurich present III-V on silicon wafers breakthrough technology using ALD

IBM has done it - a method of depositing ultra-fast III-V nanowires suitable for transistor channels and other structures on silicon-on-insulator (SOI) substrates -  and for sure ALD was involved in one of the early crucial processing steps to create the template for TASE - Template Assisted Selective Epitaxy. 

"A 30-nm-thick SiO2 layer covering the entire structure was conformally deposited using atomic layer deposition (ALD) " 

Check out the details below and in the Open Access paper!

Template-assisted selective epitaxy of III–V nanoscale devices for co-planar heterogeneous integration with Si (Open Access)

H. Schmid, M. Borg, K. Moselund, L. Gignac, C. M. Breslin, J. Bruley, D. Cutaia and H. Riel
Appl. Phys. Lett. 106, 233101 (2015); http://dx.doi.org/10.1063/1.4921962 

Schematic (a) and SEM images (b)–(d) illustrating stacking of Si and III-V NWs. (b) SEM image shows a tilted view of three stacked template structures. (c) SEM cross-section image of the Si NW stack and (d), TEM image of the GaAs NW stack (Appl. Phys. Lett. 106, 233101 (2015); http://dx.doi.org/10.1063/1.4921962)

III–V nanoscale devices were monolithically integrated on silicon-on-insulator (SOI) substrates by template-assisted selective epitaxy (TASE) using metal organic chemical vapor deposition. Single crystal III–V (InAs, InGaAs, GaAs) nanostructures, such as nanowires, nanostructures containing constrictions, and cross junctions, as well as 3D stacked nanowires were directly obtained by epitaxial filling of lithographically defined oxide templates. The benefit of TASE is exemplified by the straightforward fabrication of nanoscale Hall structures as well as multiple gate field effect transistors (MuG-FETs) grown co-planar to the SOI layer. Hall measurements on InAs nanowire cross junctions revealed an electron mobility of 5400 cm2/V s, while the alongside fabricated InAs MuG-FETs with ten 55 nm wide, 23 nm thick, and 390 nm long channels exhibit an on current of 660 μA/μm and a peak transconductance of 1.0 mS/μm at VDS = 0.5 V. These results demonstrate TASE as a promising fabrication approach for heterogeneous material integration on Si.

SEM images illustrating epitaxial filling of complex nano structures. (a) Evolution of the growth during filling of three templates, each having a lithographically pre-defined constriction. (b) Formation of an InAs cross-junction for the later fabrication of a Hall structure. The InAs film thickness is 23 nm (Appl. Phys. Lett. 106, 233101 (2015); http://dx.doi.org/10.1063/1.4921962).

The fabrication steps of TASE : a (100)-oriented SOI substrates (Soitec) with a device layer thickness of 25–50 nm were patterned using e-beam lithography and reactive ion etching. A 30-nm-thick SiO2 layer covering the entire structure was conformally deposited using atomic layer deposition (ALD) and annealed at 850 °C in Ar/H2. The SiO2 cap on one end of the Si structure was opened by patterning polymethylmethacrylate (PMMA) by e-beam lithography and buffered hydrofluoric acid (BHF) etching to expose the Si device layer. Next the Si was back-etched to the desired length using either XeF2 dry etching followed by tetramethylammoniumhydroxide (TMAH) wet etching or TMAH etching only, to result in well-defined {111} planes. The orientation of the {111} planes with respect to the channel direction was controlled by the alignment of the channel patterns. All structures reported here were patterned along the 〈110〉 direction. The as-prepared substrate was dipped in diluted (2.5%) HF to remove the native oxide on the exposed Si surfaces within the channels and was immediately loaded into the MOCVD reactor. Selective epitaxy of InGaAs was carried out using trimethylindium (TMIn), tertiarybutylarsine (TBAs), and trimethygallium (TMGa) at V/III ratio = 40 with TMIn/(TMIn+TMGa) = 0.5 at 580 °C. Chemical analysis was obtained from electron energy loss spectroscopy (EELS) analysis and indicated an In0.50Ga0.50As composition. InAs epitaxy was carried out at 520 °C using TMIn and TBAs with a V/III ratio = 80 and V/III ratio = 40 for the MuGFETs, respectively. Optionally, the dielectric template was removed after growth by wet etching in diluted HF, to expose the Si–III-V nano-structure on the SiO2 layer (BOX). 

2nd Area Selective Deposition workshop (ASD 2017), April 20-21, 2017

In collaboration with COST action HERALD, Eindhoven University will host the 2nd Area Selective Deposition workshop (ASD 2017), which will be held on April 20-21, 2017. The aim of this workshop is to bring together leading scientists and engineers from both academia and industry, to discuss the fundamentals of area selective deposition, as well as its applications.

Similar to last year’s successful workshop at IMEC, ASD 2017 will consist of one day of presentations and discussions. This scientific program will take place on April 21 in the city center of Eindhoven (90 minutes from Amsterdam), and will be preceded by a welcome reception at Eindhoven University on April 20. We are pleased to confirm the following invited speakers: Stacey Bent (Stanford University), John Abelson (University of Illinois at Urbana-Champaign), Rong Chen (Huazhong University), and Younghee Lee (University of Colorado at Boulder).

In addition to several invited presentations, this year’s program will include a few contributed presentations to feature recent developments in the field. The topics for these presentations will be selected based on abstracts received. Furthermore, there will be a poster session covering work related to nucleation, selective deposition, and nanopatterning. The abstract deadline is February 21. Note that this deadline is relatively tight.

The workshop is free, but registration for the scientific program and the welcome reception is mandatory. The registration deadline is April 12. Please see www.nanomanufacturing.nl/ASD2017 for more information about abstract submission and registration.

The ASD Program Committee is looking forward to your attendance.

Scott Clendenning (Intel Corporation), Annelies Delabie (IMEC), Dennis Hausmann (LAM Research), Rami Hourani (Intel Corporation), Gregory Parsons (North Carolina State University), and Adrie Mackus (Eindhoven University of Technology)

COST Action MP1402 - HERALD
Hooking together European research in Atomic Layer Deposition

Call for Papers on ALD & ALE Applications, at ECS Fall Meeting / Gothenburg Oct. 2023 ►►DEADLINE EXPIRES APRIL 21◄◄

Call for Papers on ALD & ALE Applications, at ECS Fall Meeting / Gothenburg Oct. 2023 ►►DEADLINE EXPIRES APRIL 21◄◄

The Electrochemical Society (ECS) conference is an international event running every spring and fall, and gathering 2000-4000 participants and 30-40 exhibitors both from academia and industry.

The conference has a strong focus on emerging technology and applications in both electrochemistry and solid-state science & technology.

This fall the event will be held as 244^th ECS Meeting on Oct. 8-12, 2023 in Gothenburg (Sweden).

The full program as well as information on travel assistance for students can be found on https://www.electrochem.org/244.

 

The organizers of symposium G01 on “Atomic Layer Deposition & Etching Applications, 19” encourage you to submit your abstracts on the following (and closely related) topics:

 

1.   Semiconductor CMOS applications: development and integration of ALD high-k oxides and metal electrodes with conventional and high-mobility channel materials;

2.   Volatile and non-volatile memory applications: extendibility, Flash, MIM, MIS, RF capacitors, etc.;

3.   Interconnects and contacts: integration of ALD films with Cu and low-k materials;

4.   Fundamentals of ALD processing: reaction mechanisms, in-situ measurement, modeling, theory;

5.   New precursors and delivery systems;

6.   Optical and photonic applications;

7.   Coating of nanoporous materials by ALD;

8.   MLD and hybrid ALD/MLD;

9.   ALD for energy conversion applications such as fuel cells, photovoltaics, etc.;

10. ALD for energy storage applications;

11. Productivity enhancement, scale-up and commercialization of ALD equipment and processes for rigid and flexible substrates, including roll-to-roll deposition;

12. Area-selective ALD;

13. Atomic Layer Etching (‘reverse ALD’) and related topics aiming at self-limited etching, such as atomic layer cleaning, etc.

 

Abstract submission

Meeting abstracts should be submitted not later than the deadline of April 21, 2023 via the ECS website: Abstract submission instruction

 

List of invited speakers

·   Johan Swerts, (Imec, Belgium) KEYNOTE: ALD challenges and opportunities in the light of future trends in electronics

·   Stephan Wege (Plasway Technology, Germany), Reactor design for combined ALD & ALE

·   Masanobu Honda (TEL, Japan), Novel surface reactions in low-temperature plasma etching

·   Barbara Hughes, (Forge Nano, USA), Dual Coatings, Triple the Benefit; Atomic Armor for Better Battery Performance

·   Juhani Taskinen, (Applied Materials-Picosun, Finland), ALD for biomedicine

·   Alex Kozen (Univ. of Maryland, USA), ALD for improved Lithium Ion Batteries

·   Malachi Noked (Bar-Ilan Univ., Israel), ALD/MLD for batteries

·   Yong Qin (Chinese Academy of Sciences), ALD for catalysis

·   Jan Macák, (Univ. of Pardubice, Czechia), ALD on nanotubular materials and applications

·   Bora Karasulu, Univ. of Warwick, UK), Atomistic Insights into Continuous and Area-Selective ALD Processes: First-principles Simulations of the Underpinning Surface Chemistry

·   Ageeth Bol (Univ. Michigan, USA), ALD on 2D materials

·   Pieter-Jan Wyndaele (KU Leuven-imec, Belgium), Enabling high-quality dielectric passivation on Monolayer WS₂ using a sacrificial Graphene Oxide template

·   Elton Graugnard (Boise State Univ., USA), Atomic Layer Processing of MoS₂

·   Han-Bo-Ram Lee (Incheon National Univ., Korea), Area-Selective Deposition using Homometallic Precursor Inhibitors

·   Ralf Tonner (Univ. Leipzig, Germany), Ab initio approaches to area-selective deposition

·   Nick Chittock (TU Eindhoven, Netherlands), Utilizing plasmas for isotropic Atomic Layer Etching

·   Heeyeop Chae (Sungkyunkwan Univ., Korea), Plasma-enhanced Atomic Layer Etching for Metals and Dielectric Materials

·   Charles Winter (Wayne State Univ., USA), New Precursors and Processes for the Thermal ALD of Metal Thin Films

·   Anjana Devi, Ruhr Univ. Bochum, Germany), Novel precursors dedicated for Atomic Layer Processing

 

Visa and travel

For more information, see: www.electrochem.org/244/visa-travel/

In addition, Mrs. Francesca Spagnuolo at the ECS (Francesca.Spagnuolo@electrochem.org) can provide you with an official participation letter from the site of the Electrochemical Society.

 

We are looking forward to meeting you in Gothenburg !

Applied Materials on Atomic Level Selective patterning technologies for 7 & 5 nm

Here is an interview with Prabu Raja, group vice president, fellow at Applied Materials and general manager for the Patterning and Packaging Group at Applied Materials, by Mark Lapedus at Semiconductor Engineering.

Prabu Raja, Group VP, Patterning & Packaging group, highlights Applied Materials Centris Sym3 Etch & Olympia ALD 2015 (Applied_Blog on Twitter)

The interview covers the upcoming hurdles like overlay and edge placement error in patterning at the 7 and 5 nm node and technologies to solve them:

• Extreme ultraviolet (EUV) lithography
• Self-aligned octuple patterning (SAOP)
• Atomic Layer Etching (ALE)
• Selective removal
• Atomic Layer Deposition (ALD)
• Selective deposition

Applied Materials Revolutionizes Etch with Breakthrough Selective Materials Technology https://t.co/MMsqJvEBgs pic.twitter.com/zbcrneqsgi

— Applied Materials (@Applied_Blog) June 29, 2016

Wayne State presented new ALD chemistries for low temperature tantalum and selective cobalt at ALD2016

Prof. Chuck Winter and his team at Wayne State presented new ALD chemistries for low temperature tantalum and selective cobalt at ALD 2016 Ireland this week. Both processes are very important for todays scaling of logic and memory technologies. Metallic tantalum can be used in workfunction engineering of HKMG high performance FinFET transitors as well as for Cu seed/barrier technology in BEOL. Cobalt is as tantantlum an option for Cu barrier/seed and also used selectivly to cap the Cu lines and vias from oxidising and reducing RC performance.

The best highlight talk went to Marissa Kerrigan from Wayne State as voted by attendees on novel Co recursor chemistry for selective Cobalt (Left Marissa Kerrigan, right Simon Elliott, photo by ALD2016.com).

“This opens up the prospect of using tantalum in layers just a few nanometers thick as the liner for interconnect wiring in the complex geometries of next-generation electronic chips,” said the University, which worked with German chemicals giant BASF on the project accoring to Electronic Weekly.

Marissa Kerrigan also from Wayne State announced novel ALD chemistry for metallic cobalt that showed excellent selectivity to copper (photo by ALD2016.com).

“The Wayne State processes for tantalum and cobalt are significant steps forward in controlled growth of ultra-thin metals,” said conference chair, Dr Simon Elliott of Ireland’s Tyndall National Institute. “Strong growth is projected for area-selective deposition: in the near future, it will allow higher-precision patterning of semiconductor chips, and in the longer term it will be an enabler for manufacturing nano-structured materials on demand.” according to the same article in Electronics Weekly.

Area selective ALD of hafnium nitride on Low-k by Veeco and Imec

Here is a recent Area Selective Deposition (ASD) paper by Veeco and Imec that got to be the Editor's Pick in JVSTA. ASD is important in scaling down semiconductor devices since it is a self aligned process meaning that you will not have an alignment issues with the previous patterning process when you continue to build your nano-electronic device layer by layer.

 

This paper is about growing hafnium nitride selectively by ALD on low-k dielectrics but not on copper. Hf3N4 is a decent high-k dielectric and can be transformed into HfSiON etc by annealing in oxygen atmosphere. Another option would be to let it act as a nucleation layer and barrier for e.g. a metal process by ALD, CVD or ELD. Here Imec and Veeco use vapor-deposited octadecanethiol as a masking layer on copper to enable area selective Hf3N4 atomic layer deposition on dielectrics studied by in-situ spectroscopic ellipsometry. 

 

This type of process could become an important tool in future bottom up fabricated process modules. As an example a process that is already in production is area selective CVD of Co on copper lines by using CoCOCp. Her Co metal only grows on the exposed copper lines and not on the low-k and thereby encapsulates the copper lines which reduces the risk for electromigration that leads to interconnect line fails.

 

Please check out the paper which is available as open sources : LINK

 

 

Wafer-scale single-domain-like graphene by defect-selective ALD of hexagonal ZnO

Korean researchers report defect-selective atomic layer deposition (ALD) for stitching grain boundaries of CVD graphene with ZnO to increase the connectivity between grains. In the present ALD process, ZnO with a hexagonal wurtzite structure was selectively grown mainly on the defect-rich grain boundaries to produce ZnO-stitched CVD graphene with well-connected grains.

Wafer-scale single-domain-like graphene by defect-selective atomic layer deposition of hexagonal ZnO

Kyung Sun Park, Sejoon Kim, Hongbum Kim, Deokhyeon Kwon, Yong-Eun Koo Lee, Sung-Wook Min, Seongil Im, Hyoung Joon Choi, Seulky Lim, Hyunjung Shin, Sang Man Koo and Myung Mo Sung

Nanoscale, 2015, Advance Article, DOI: 10.1039/C5NR05392G, Accepted 24 Sep 2015

Large-area graphene films produced by means of chemical vapor deposition (CVD) are polycrystalline and thus contain numerous grain boundaries that can greatly degrade their performance and produce inhomogeneous properties. A better grain boundary engineering in CVD graphene is essential to realize the full potential of graphene in large-scale applications. Here, we report a defect-selective atomic layer deposition (ALD) for stitching grain boundaries of CVD graphene with ZnO so as to increase the connectivity between grains. In the present ALD process, ZnO with a hexagonal wurtzite structure was selectively grown mainly on the defect-rich grain boundaries to produce ZnO-stitched CVD graphene with well-connected grains. For the CVD graphene film after ZnO stitching, the inter-grain mobility is notably improved with only a little change in the free carrier density. We also demonstrate how ZnO-stitched CVD graphene can be successfully integrated into wafer-scale arrays of top-gated field-effect transistors on 4-inch Si and polymer substrates, revealing remarkable device-to-device uniformity.

Area-selective ALD with high selectivity at TU Eindhoven

Here is a cool video for TU Eindhoven on Area-selective ALD with high selectivity just publishe in their AtomicLimits blog "Towards Area-Selective Atomic Layer Deposition with High Selectivity – Our perspective on area-selective ALD" by Adrie Mackus (LINK).