Adisyn Ltd Invests in ALD Technology from Beneq Graphene Device Manufacturing

Adisyn Ltd has taken a significant step toward advancing semiconductor technology with its recent investment in an Atomic Layer Deposition (ALD) machine from Beneq. On November 10, 2024, the company announced that its subsidiary, 2D Generation Ltd, ordered the specialized equipment to enhance graphene-coated interconnect technology, a breakthrough innovation in next-generation chip development. This strategic acquisition underscores Adisyn's commitment to driving innovation in critical markets such as defense, data centers, and cybersecurity. Through the collaboration between Adisyn and 2D Generation, alongside Beneq's cutting-edge ALD expertise, the partnership is set to address key challenges in semiconductor manufacturing, paving the way for faster, energy-efficient, and more reliable computing solutions.

Adisyn Ltd has invested in an Atomic Layer Deposition (ALD) machine from Beneq. On November 10, 2024, Adisyn announced that its subsidiary, 2D Generation Ltd, ordered a specialized ALD machine from Beneq to advance their semiconductor technologies, including graphene-coated interconnects. This acquisition aims to accelerate the development of next-generation chip technology, benefiting Adisyn's target markets such as defense applications, data centers, and cybersecurity.

2D Generation Ltd is an Israeli high-tech company specializing in graphene-based solutions for the semiconductor industry. Founded by entrepreneur and innovator Arye Kohavi, the company focuses on overcoming current technological limitations by developing faster, more energy-efficient computer processing solutions. 

A significant advancement by 2D Generation is their patented method for depositing graphene coatings at temperatures below 300 degrees Celsius. This breakthrough enables the next generation of semiconductors to achieve further miniaturization, reduced power consumption, less heat generation, and greater computational power. 

One of 2D Generation Ltd patent applications (US2024301554 AA) outlines a method employing ALD to apply graphene as a diffusion barrier or interfacial layer on non-metallic surfaces, such as dielectric or semiconductor layers. ALD is used to achieve precise, uniform deposition of graphene molecular precursor layers, enabling atomic-level control and ensuring high-quality graphene with minimal defects. The process operates at low temperatures (below 350°C), making it compatible with sensitive semiconductor manufacturing. The graphene is covalently bonded to the substrate using customized precursors containing tethering groups tailored for strong chemical interactions. These precursors, such as aromatic hydrocarbons with functional groups like trichlorosilyl or carboxylic acids, are designed to react with the substrate to form stable graphene layers. Precursor deposition methods include vacuum techniques like sublimation or evaporation, and the process may involve sequential cycles of different precursors to optimize uniformity, fill factor, and defect ratio. This approach addresses critical challenges in semiconductor interconnect scaling by providing a high-conductivity, robust diffusion barrier that prevents metal atom migration, enhances reliability, and supports higher current densities in advanced integrated circuits.

In July 2024, 2D Generation entered into a binding collaboration agreement with Adisyn Ltd, an Australian technology company, to develop high-performance, energy-efficient semiconductor solutions for AI and data centers. This partnership aims to leverage 2D Generation's semiconductor innovations alongside Adisyn's expertise in data center management and cybersecurity. 

Furthering their collaboration, in November 2024, Adisyn Ltd announced a binding agreement to acquire 100% of 2D Generation Ltd's issued share capital. This acquisition is expected to enhance Adisyn's capabilities in developing advanced semiconductor technologies, particularly in defense applications, data centers, and cybersecurity. 

Additionally, 2D Generation is a partner in the European Union's Connecting Chips Joint Undertaking, which includes research and innovation partners such as NVIDIA, IMEC, Valeo, Applied Materials, NXP, and Unity. This initiative focuses on accelerating the development of next-generation semiconductor chips to meet the growing demands of generative AI and other advanced technologies.  

Beneq, founded in 1984 and headquartered in Espoo, Finland, is a global leader in Atomic Layer Deposition (ALD) technology, offering equipment and research services for semiconductor fabrication, batch production, research, and spatial ALD applications. Acquired in 2018 by Qingdao Sifang SRI Intellectual Technology Co. Ltd., Beneq focuses on industrial ALD thin film solutions and transparent displays. Its product portfolio includes automated ALD systems for high-capacity wafer production, batch production tools for diverse substrates, flexible research equipment, and roll-to-roll ALD systems. Beneq also provides coating, R&D, spare parts, and system upgrades, with offices in the US, China, and Japan. Qingdao Sifang SRI Intellectual Technology Co., Ltd., established in 2018 and headquartered in Qingdao, China, specializes in the development and manufacturing of advanced semiconductor process equipment. Supported by significant investments, including a Series B funding round in 2024 involving SAIC Motor Corporation, the company has achieved key milestones, such as developing China's first domestic high-energy ion implanter. 

Sources:

Patbase

www.beneq.com

Presentation - Adisyn Ltd (ASX:AI1) - Listcorp.

New Generation Atomic Layer Deposition Machine Procured | INN

New Method for Precision Doping in 2D Semiconductors Enables Next-Gen CMOS Integration

Researchers have achieved a breakthrough in doping two-dimensional (2D) semiconductors, paving the way for monolithic integration of p-type and n-type semiconductor channels on a single chip. This development holds promise for advancing complementary CMOS technology, allowing further transistor scaling and efficient interlayer connections.

The study focuses on 2H-MoTe2, a van der Waals material, and employs a precise substitutional doping technique. Unlike conventional methods such as ion implantation—which do not work well with 2D materials—this approach allows the targeted introduction of niobium (Nb) for p-type doping and rhenium (Re) for n-type doping, using a magnetron co-sputtering method followed by chemical vapor deposition (CVD). By precisely adjusting the concentration of these dopants, researchers produced wafer-scale films with consistent carrier properties, even enabling spatial control of the doped regions. This advance allows for the patterning of p-type and n-type channels on the same wafer in a single growth process, which is essential for CMOS device fabrication.

Using this novel technique, the team created a large-scale 2D CMOS inverter array that achieved impressive performance metrics. For instance, a typical inverter from this array demonstrated a voltage gain of 38.2 and low static power consumption, key parameters for efficient CMOS operation. The new doping method also exhibits high uniformity and reliability, essential for scaling up 2D materials in commercial semiconductor applications.

This innovation in 2D semiconductor doping introduces a promising pathway for integrating materials like 2H-MoTe2 into very-large-scale integration (VLSI) technology, further driving forward Moore's Law and the miniaturization of semiconductor devices.

Figure 1 from paper, Pan, Y., Jian, T., Gu, P. et al. Precise p-type and n-type doping of two-dimensional semiconductors for monolithic integrated circuits. Nat Commun 15, 9631 (2024). https://doi.org/10.1038/s41467-024-54050-2

Experimental

In the study, co-sputtering and CVD is used to create large-scale, precisely doped 2D 2H-MoTe2 films by transforming a molybdenum film doped with niobium or rhenium into 2H-MoTe2 through a process called tellurization. Here’s a breakdown of how this process works:

Preparation of the Mo Film: Initially, thin Mo films are deposited on a silicon/silicon dioxide (Si/SiO2) substrate using magnetron co-sputtering. During this step, controlled amounts of Nb (for p-type doping) or Re (for n-type doping) are co-sputtered with the Mo film, resulting in a doped Mo layer.

Tellurization Process in the CVD Reactor: The Mo film, now doped with Nb or Re, is placed in a CVD furnace along with solid tellurium (Te) lumps. Under a controlled flow of carrier gases (argon and hydrogen), the CVD chamber is heated to high temperatures (around 650°C). The Te vapor reacts with the Mo, leading to the formation of 1T'-MoTe2.

Phase Transformation to 2H-MoTe2: At the elevated temperatures within the CVD system, the 1T'-MoTe2 structure undergoes a phase transformation into the more stable 2H phase, producing the final doped 2H-MoTe2 film. This phase is crucial because 2H-MoTe2 has semiconducting properties suitable for integrated circuits.

Doping Incorporation: During the CVD tellurization, Nb and Re atoms from the initial Mo film become substitutionally incorporated into the MoTe2 lattice. This incorporation determines the semiconductor type (p-type or n-type) and carrier concentration of the resulting 2H-MoTe2 film.

Large-Scale Uniformity: By controlling the initial dopant concentration and maintaining consistent conditions in the CVD process, the researchers achieved uniform doping across large-scale wafers, crucial for creating reliable semiconductor devices.

Source: Precise p-type and n-type doping of two-dimensional semiconductors for monolithic integrated circuits | Nature Communications

Chipmetrics Secures €1 Million from Business Finland to Drive Global Expansion in Semiconductor Metrology

Helsinki, Finland – 6 November 2024 – Chipmetrics Oy, a pioneering leader in 3D thin film semiconductor metrology, announces that it has been awarded 1 million euro from Business Finland’s Young Innovative Company (YIC) funding programi. The fund’s purpose is to support promising Finnish startups that demonstrate potential for substantial global growth and innovation, with funding from it awarded exclusively to startups of less than five years of age with outstanding business potential. The funding represents state-level recognition of Chipmetrics’ progress and level of maturity as it steps up its efforts to enable the semiconductor industry to transition to 3D chips. It will primarily be used to amplify the company’s business development activities and support rapid international expansion. 

Chipmetrics' core range of advanced semiconductor metrology solutions already enjoy strong support in markets such as Japan and Korea, with the next business goal being expansion beyond these markets globally. "This is a pivotal moment for Chipmetrics. With Business Finland’s support, we can enhance our product offerings and scale our operations to meet the growing demands of the semiconductor industry,” said Mikko Utriainen, CEO of Chipmetrics at Chipmetrics about the new opportunities the additional support will enable. “Our goal is to drive innovation that will not only benefit our clients but also contribute to the technological advancements in 3D thin-film deposition through better metrology solutions." “When considering who to fund with the Young Innovative Company funding, we require that the company is innovative, it has scalable business model, strong international business plans for rapid growth and they are already able to demonstrate some international sales. We believe Chipmetrics ticks all these boxes very well.” said Marko Kotonen, Senior Advisor at Business Finland.  

The Young Innovative Company funding program is a phased support system intended to accelerate the global growth of promising Finnish companies. The average company that received funding in 2024 was 4 years old with 13 employees, a 420,000+ EUR turnover from a scalable business and strong internationally experience management. Chipmetrics’ selection for this funding underscores its strong commitment to innovation, superior technology development, and its potential to impact the global semiconductor industry. Chipmetrics specializes in ALD, a segment of the semiconductor industry that itself is set to eclipse a trillion euroii by the end of the 2020s.  

About Chipmetrics Chipmetrics Oy develops and delivers metrology solutions for manufacturing processes for the semiconductor industry, focusing on innovative metrology chips and ALD measurement services. Its main product is the PillarHall® metrology chip for near-instantaneous thin film process conformality measurement. Founded in 2019, its head office is in Joensuu, Finland, with employees and sales partners in Japan, South Korea, USA, and Germany. For more information, visit www.chipmetrics.com. 

Press contact: Jonas Klar jonas.klar@chipmetrics.com pr@chipmetrics.com Chipmetrics Oy 

Applied Materials Delivers Advanced ALD 200 mm Batch Technology to United Monolithic Semiconductors (UMS) for RF and Power Device Manufacturing

Applied Materials (prev. Picosun Oy) announce that they have delivered ALD technology to United Monolithic Semiconductors (UMS) for RF and power devices manufacturing. UMS is a compound semiconductor foundry and device manufacturer located in Ulm, Germany and Villebon, France. UMS produces RF devices, such as amplifiers, detectors, high-electron-mobility transistors and complete transceiver systems.

"We see the investment in the ALD technology as a key step forward. ALD is everyday technology in silicon-based IC and memory components and there are real benefits also for the compound semiconductor devices. We want to be the forerunner in our specific application fields, so including ALD in our process portfolio is one important step in staying ahead of the competition.​" - Dr. Klaus Zieger, Manager Process & Tools, UMS

United Monolithic Semiconductors (UMS) is a leading European company specializing in the design, manufacture, and marketing of radio frequency (RF) and millimeter-wave integrated circuits (MMICs. Established in 1996 as a joint venture between Thales and Airbus Defence and Space, UMS has become a strategic supplier to the European defense and space industries.

UMS offers a comprehensive range of products and services, including amplifiers, attenuators, core chips, detectors, converters, transistors, mixers, multipliers, oscillators, phase shifters, power divider combiners, RF front-ends, and switches.These products cater to various applications across defense, security, space, telecommunications, automotive, industrial, medical, and instrumentation sectors.

The company's technological foundation is built on in-house Gallium Arsenide (GaAs) and Gallium Nitride (GaN) processes, enabling the development of state-of-the-art products and providing a robust platform for their foundry services. UMS is committed to continuous innovation, collaborating with major research and development centers and universities throughout Europe to advance technologies and products for future markets.

Applied™ Morpher™ Batch ALD

Applied™ Morpher™ Batch ALD product platform is designed to disrupt thermal batch ALD for the up to 200 mm wafer industries in IoT, Communications, Automotive, Power, and Sensors (ICAPS) markets. It enables fast, fully automatic, high throughput production of MEMS, sensors, LEDs, lasers, power electronics, optics, and 5G components with the leading process quality, reliability, and operational agility.

Applied Morpher Batch ALD adapts to the changing needs of your industry and the requirements of your customers, on all business verticals from advanced R&D to production and foundry manufacturing. The leading versatility in substrate materials, substrate and batch size, and the wide process range make Morpher truly a transformable, all-inclusive ALD tool to keep you spearheading your industry.

Applied Morpher Batch ALD is designed for fully automated handling of wafer batches in combination with a single wafer vacuum cluster platform. Revolutionary, wafer batch flipping mechanism enables integration of the system with semiconductor manufacturing lines where most of the processing takes place in horizontal geometry. It can be combined with Applied™ Picosun™ Morpher™ P, plasma PEALD single wafer process module, or the Applied™ Picosun™ Morpher™ T, thermal ALD single wafer process module.

With our dual-chamber, hot-wall reactor design with fully separated precursor conduits and inlets, we create the highest quality ALD films with excellent yield, low particle levels, and superior electrical and optical performance. The compact, ergonomic design with easy and fast maintenance ensures minimum system downtime and low cost-of-ownership.

Solid-State Batteries Move Closer to Mass Production as Global Manufacturers Ramp Up Pilot Production

Solid-state batteries (SSBs) are rapidly advancing toward commercialization, with major companies like Toyota, Nissan, and Samsung SDI beginning pilot production and targeting GWh-level output by 2027. These batteries promise enhanced safety and higher energy density, yet face significant challenges related to high production costs and complex manufacturing processes. Despite these hurdles, manufacturers are progressing towards cost reductions through scaling, with TrendForce projecting costs to fall to USD 0.084–0.098 per Wh by 2035. Japanese companies, led by Toyota, are pushing for early mass production by 2026, while Chinese and South Korean firms follow closely, seeking to meet domestic demand for electric vehicles and energy storage.

Read more (https://www.trendforce.com/presscenter/news/20241031-12346.html)

SSBs are advancing towards commercialization as companies like Toyota, Nissan, and Samsung SDI begin pilot production, aiming to achieve GWh-level output by 2027. SSBs promise higher safety and energy density but face hurdles in production cost, complex manufacturing, and supply chain immaturity. Currently, semi-solid-state batteries, which have achieved GWh-scale deployment in EVs, cost over CNY 1/Wh (≈ USD 0.14/Wh), but TrendForce expects costs to drop below CNY 0.4/Wh (≈ USD 0.056/Wh) by 2035 with production advancements. All-solid-state batteries (ASSBs), progressing from prototypes to engineering-scale production, may see prices fall to CNY 0.6–0.7/Wh (≈ USD 0.084–0.098/Wh) by 2035 if demand scales above 10 GWh. Sulfide-based SSBs are particularly promising due to their high ionic conductivity, attracting major manufacturers despite challenges with cost and moisture sensitivity. Though current SSBs are not yet competitive with liquid lithium-ion batteries, TrendForce predicts cost reductions through scaling and strong government and capital support.

Among the leading manufacturers of all-solid-state batteries (ASSBs), several companies are targeting mass production (MP) status by the late 2020s. Toyota from Japan is poised to be one of the earliest, planning to reach mass production by 2026, setting a rapid pace in the industry. Samsung SDI and SK On from South Korea are also aiming for mass production by 2027, along with Chinese companies like CATL and BYD, who are likewise on track for MP status around the same period. This timeline highlights a competitive landscape where Japanese and South Korean firms are pushing for an earlier rollout, while Chinese companies are closely following, aiming to capitalize on their domestic market’s significant demand for electric vehicles and energy storage. Japan’s early push, led by Toyota, suggests a strategic approach to secure a leadership position in advanced battery technology.

Atomic Layer Deposition (ALD) has become crucial for advancing solid-state batteries due to its ability to create uniform, pinhole-free, and conformal thin films on complex structures. For solid-state electrolytes (SSEs), ALD enables the deposition of materials like lithium phosphorus oxynitride (LiPON) with high ionic conductivity, which enhances overall battery performance by forming thin, conformal electrolyte layers. This technology also plays a significant role in interface engineering by modifying the interfaces between electrodes and electrolytes. ALD-deposited interlayers improve chemical compatibility, reduce interfacial resistance, and suppress unwanted reactions, thereby improving the durability and efficiency of solid-state batteries.

ALD is especially beneficial for the development of 3D battery architectures, where its conformal coating capability enables uniform deposition on high-aspect-ratio structures, increasing surface area and enhancing energy and power densities. In addition, ALD is used to apply protective coatings to electrode materials, which prevents degradation and enhances battery stability. Examples include ALD-grown lithium silicate films that serve as solid-state electrolytes with reliable ionic conductivity. Recent research highlights ALD’s essential role in producing high-performance ASSBs and SSBs, focusing on thin-film deposition precision and interface engineering to overcome challenges related to solid-state battery design and performance.

Key applications of ALD in sulfur-based SSBs include protective coatings on sulfur cathodes, enhancing solid electrolytes, and interface engineering. ALD can apply ultra-thin, conformal coatings on sulfur cathodes, which help to mitigate polysulfide dissolution—a common issue in sulfur-based systems that leads to capacity fading. By creating a barrier layer, ALD coatings help to prevent polysulfides from migrating, thereby enhancing cycle life and reducing degradation. For example, materials like Al2O3 and TiO2 deposited via ALD have been used to form stable interfacial layers that suppress undesirable reactions.

ALD is also utilized to improve the ionic conductivity of sulfide-based solid electrolytes, such as Li2S-P2S5, which are promising due to their high ionic conductivity and similarity to liquid electrolytes. ALD can deposit thin films of stabilizing materials on these electrolytes to prevent reactions with lithium and improve stability. Additionally, ALD helps create protective layers around sulfide electrolytes, which are highly sensitive to moisture and oxygen, reducing the need for stringent environmental controls.

Interface engineering is another important application of ALD, with the precision of ALD enabling the deposition of thin interlayers at the electrode-electrolyte interfaces, addressing the issue of poor contact and high interfacial resistance in sulfur-based SSBs. These interlayers help to form a stable “solid-solid” contact, minimizing interfacial impedance and enhancing ion transfer across the interface. Materials such as lithium phosphorous oxynitride (LiPON) or lithium silicate are often used in ALD processes to create these interlayers, leading to improved overall battery performance and stability.

Refernces:

https://www.frontiersin.org/journals/energy-research/articles/10.3389/fenrg.2018.00010/full

https://pubs.rsc.org/en/content/articlelanding/2021/na/d0na01072c

https://www.frontiersin.org/journals/energy-research/articles/10.3389/fenrg.2018.00010/full

https://www.eng.uwo.ca/nanoenergy/publications/2017/PDFs/Atomic-Layer-Deposited-Lithium-Silicates-as-Solid-State-Electrolytes-for-All-Solid-State-Batteries.pdf

Atomic Level Processing of Gold: Advances in Atomic Layer Deposition (ALD) and Atomic Layer Etching (ALE)

Atomic layer processing methods, including Atomic Layer Deposition (ALD) and Atomic Layer Etching (ALE), have advanced the precision with which metals like gold can be manipulated at the atomic scale. Traditionally, gold has been challenging to process due to its low reactivity, but recent developments have made it possible to deposit and etch gold with atomic-scale control. While Professor Seán Barry’s work has focused on pioneering methods for gold deposition using ALD, Professor Steven M. George and his team have recently demonstrated a successful thermal ALE technique for gold. Together, these breakthroughs represent a new frontier in gold processing, enabling nanoscale applications in electronics, nanotechnology, and catalysis.

Advances in Atomic Layer Deposition (ALD) of Gold: Professor Seán Barry’s Work

Atomic Layer Deposition (ALD) relies on self-limiting surface reactions to grow thin films with atomic precision, and it is ideal for materials where control over layer thickness and uniformity is essential. However, gold presents unique challenges in ALD due to its inertness and lack of reactive sites. Despite this, Professor Seán Barry and his team have developed a plasma-enhanced ALD (PEALD) approach that overcomes these hurdles by using a specialized gold precursor and plasma activation.

Plasma-Enhanced ALD (PEALD) Method

Barry’s team utilized a trimethylphosphine-supported gold(III) precursor, specifically Me₃AuPMe₃, in combination with oxygen plasma to deposit gold layers. The plasma serves to activate the precursor and facilitate the deposition reaction, which would otherwise be hindered by gold’s low reactivity.

Low-Temperature Deposition

The process is achievable at temperatures around 120–130°C, considerably lower than traditional thermal ALD processes. This temperature range minimizes the risk of precursor decomposition, allowing the deposition of smooth and uniform gold films without unwanted by-products.

Deposition Rate and Film Quality

The deposition process achieved a growth rate of approximately 0.5 Å per cycle, providing exceptional control over film thickness. Barry’s PEALD method allows for uniform, conformal gold coatings that are valuable in microelectronics, sensing devices, and other applications where thin films of noble metals are required.

University of Helsinki Unveils Thermal ALD Process for Gold Coating in 3D Applications

The University of Helsinki has developed a groundbreaking thermal Atomic Layer Deposition (ALD) process for gold using the precursor Me₂Au(S₂CNEt₂) with a broad process window (120–250°C), achieving uniform and highly conductive films. This innovation addresses the limitations of plasma-enhanced ALD, which can struggle with coating complex 3D structures. By utilizing ozone as a co-reactant, the researchers achieved continuous gold films with a growth rate of 0.9 Å/cycle at 180°C and low resistivity, ideal for advanced applications requiring precise, conductive coatings. This follows an earlier Helsinki breakthrough in Ruthenium ALD, marking another step forward in atomic-level metal deposition techniques.

Breakthrough in Atomic Layer Etching (ALE) of Gold: Professor Steven M. George’s Method

Building on the advances in ALD for gold, Professor Steven M. George’s recent work on thermal ALE offers a complementary technique to precisely remove gold layers. Published in May 2024, George’s ALE method for gold uses a novel two-step thermal process involving chlorination and ligand addition. This approach bypasses the need for plasma, instead relying on a purely thermal cycle to achieve atomic-level etching of gold.

The study demonstrates a thermal atomic layer etching (ALE) process for gold using sequential reactions: chlorination with sulfuryl chloride (SO₂Cl₂) to form gold chloride, followed by ligand addition with triethylphosphine (PEt₃) to produce a volatile etch product, AuClPEt₃. This method achieved consistent etching at 0.44 ± 0.16 Å per cycle at 150°C on gold films. Mass spectrometry confirmed AuClPEt₃ as the main etch product, while analysis showed that ALE maintained nanoparticle smoothness without surface roughening. The approach was also effective on copper and nickel, offering a versatile ALE pathway for metals through controlled chlorination and ligand-addition reactions. LINK: https://pubs.acs.org/doi/10.1021/acs.chemmater.4c00485

Two-Step Thermal ALE Process

Chlorination: The gold surface is initially chlorinated using sulfuryl chloride (SO₂Cl₂), which forms gold chloride (AuCl) on the surface. This step primes the gold for the ligand addition reaction.

Ligand Addition with Triethylphosphine (PEt₃): After chlorination, triethylphosphine (PEt₃) is introduced to bind with the gold chloride, creating a volatile product, AuClPEt₃, which desorbs from the surface, effectively removing one atomic layer of gold.

Etch Rate and Temperature Control

The ALE process operates in a temperature range of 75 to 175°C, with the optimal and most consistent etch rate of 0.44 ± 0.16 Å per cycle occurring at 150°C. This repeatable, self-limiting reaction cycle ensures precise control over the etching process, which is critical for applications demanding high accuracy.

Experimental Observations and Mass Spectrometry

Quartz crystal microbalance (QCM) measurements tracked mass changes during each ALE cycle, while in situ quadrupole mass spectrometry (QMS) on gold nanopowder confirmed that AuClPEt₃ was the primary volatile product. The intensity of the AuClPEt₃+ ion peaked early in each PEt₃ dose, indicative of a self-limiting reaction where gold is etched in controlled increments.

Structural Integrity of Gold Nanoparticles

Analysis using X-ray photoelectron spectroscopy (XPS) and transmission electron microscopy (TEM) showed that the ALE process did not roughen the surface of gold nanoparticles. This smoothness is crucial for applications in electronics and photonics, where surface quality affects device performance. Additionally, powder X-ray diffraction (XRD) revealed slight broadening of diffraction peaks post-ALE, indicating sintering and suggesting that gold redistribution could contribute to the formation of larger nanoparticles.

Combined Implications of ALD and ALE for Gold

The complementary nature of Barry’s PEALD for gold deposition and George’s thermal ALE for gold etching offers an unprecedented level of control over gold at the atomic level. Together, these methods enable:

High-Precision Patterning: Combined ALD and ALE allow for nanoscale patterning of gold films with atomic precision, benefiting fields such as semiconductor manufacturing and nanotechnology.

Surface Engineering: The smoothness and control over film morphology achieved through these processes make it possible to engineer gold surfaces with specific properties, crucial for sensors, catalysis, and plasmonic devices.

Enhanced Flexibility in Fabrication: The ability to alternate between deposition and etching at the atomic scale provides unparalleled flexibility, especially for creating multilayer structures or complex geometries in microelectronics and MEMS devices.

Sources:

https://pubs.acs.org/doi/10.1021/acs.chemmater.4c00485

Previous Articles on Gold ALD:

BALD Engineering - Born in Finland, Born to ALD: Thermal Atomic Layer Deposition of Gold

BALD Engineering - Born in Finland, Born to ALD: Thermal Atomic Layer Deposition of Gold: Mechanistic Insights, Nucleation, and Epitaxy

BALD Engineering - Born in Finland, Born to ALD: University of Helsinki present a thermal ALD gold process

BALD Engineering - Born in Finland, Born to ALD: Picosun and Carleton Strike Gold with ALD

Intel Sets Record with 2D TMD Transistors for Next-Gen Electronics

Intel researchers have achieved record-breaking performance in transistors using ultra-thin 2D transition metal dichalcogenides (TMDs) like MoS₂ and WSe₂ as channels. These monolayer materials are ideal for scaled devices but present challenges in integration due to their lack of atomic “dangling bonds.” By developing a specialized gate oxide atomic layer deposition (ALD) process and low-temperature gate cleaning, Intel built GAA NMOS and PMOS transistors with record subthreshold slopes and high drain currents. Specifically, they achieved a subthreshold slope of <75 mV/dec and Idmax >900 µA/µm in MoS₂ NMOS transistors, and a slope of 156 mV/dec with Idmax = 132 µA/µm in WSe₂ PMOS devices. These advancements highlight the promise of 2D TMDs for next-gen electronics and the need for further research to overcome integration challenges.

The images above are TEM characterizations of the record GAA NMOS device across the gate, showing a healthy, conformal GAA architecture with 43nm-wide monolayer MoS2 channel and conformal HfO2 with a thickness of ~4.0nm.

Record Performance with 2D Channels: Ultra-thin transition metal dichalcogenides (TMDs), such as MoS2 and WSe2, are called monolayer, or 2D, materials because they’re one just atomic layer thick. They are being extensively studied for use as the channel in extremely scaled devices because of their excellent electrical performance. However, interfacing them with other materials in a device structure is difficult because at the atomic level there are no available “dangling bonds” to use. Thus, 2D channels have been a challenge to optimize.

Intel researchers will describe how they used 1) a unique gate oxide atomic layer deposition (ALD) process and 2) a low-temperature gate cleaning process to build GAA devices that demonstrated breakthrough performance for MoS2- and WSe2-based GAA NMOS and PMOS transistors, respectively. This includes record subthreshold slope (<75mv/dec) and drain current (Idmax>900 µA/µm at <50nm gate length) in sub-1nm-thick monolayer MoS2 GAA NMOS transistors. Also, using ruthenium (Ru) source and drain (S/D) contacts, they achieved record subthreshold slope (156mV/dec) and drain current (Idmax = 132µA/µm) in a ~30nm gate-length WSe2 PMOS device. The researchers say these results both underscore the potential of 2D TMDs for use in next-generation electronics, and highlight the critical need for continued research to address the remaining scientific and technological challenges.

Sources:

https://www.ieee-iedm.org/press-kit

(Paper #24.3, “Gate Oxide Module Development for Scaled GAA 2D FETs Enabling SS<75mV/d and Record Idmax>900µA/µm at Lg<50nm,” W. Mortelmans et al, Intel)

Seiichi Iwamatsu, the Inventor of Atomic Layer Etching: The Conception of Cycled Exposures of Silicon to Halogens and Pulses of Heat, Ions, and More

Seiichi Iwamatsu, the Inventor of Atomic Layer Etching: The Conception of Cycled Exposures of Silicon to Halogens and Pulses of Heat, Ions, and More

Fred Roozeboom University of Twente, Jonas Sundqvist AlixLabs, Dmitry B. Suyatin AlixLabs, Kuniyuki Kakushima Institute of Science Tokyo (Tokyo Institute of Technology)

ECS-PRiME 2024 in Honolulu

The history of Atomic Layer Deposition (ALD) has been extensively researched in the VPHA-project (www.vph-ald.com/) initiated in 2013 by R. Puurunen [1]. It is commonly accepted that Atomic Layer Deposition (ALD) was conceived in the Baltic area as a unique ultrathin-film growth method based on the repeated, self-terminating gas-solid half-reactions of at least two volatile compounds on a solid substrate surface. Originally, in the 1960’s, the Russians Alekskovski and Kol'tsov [2]) named this method Molecular Layering and exactly 50 years ago, in 1974 the Finnish inventors Suntola and Antson [3] patented the method as Atomic Layer Epitaxy. This fact has been officially celebrated at the 24th ALD Conference in Helsinki (Aug. 5, ’24 ald2024.avs.org).

Atomic Layer Etching (ALE) has lagged behind ALD. For long [4,5] the first patent published on ALE was thought to have been initiated by Max Yoder [6]. In 1987 he conceived the idea on diamond etching with intermittent pulsing of nitrogen dioxide and noble gas ions mixed with hydrogen gas. However, it was Seiichi Iwamatsu (Fig. 1) of Seiko Epson, Japan, who filed in 1981 an application on Si-etching by repeated exposure to iodine (I2) chemistry at moderate temperatures (20 °C to 100 °C) followed by a light or heat pulse up to ~ 300 °C [7]; see Fig. 2. This patent was followed by several others on ALE [8]. One of these patents disclosed quasi-ALE (named “digital etching”) via Si-surface modification by “lamination” of a single Cl-atomic layer from exposure to Cl2 gas, followed by a removal step carried out by Ar+-ion bombardment to etch off “one atomic layer or at most three atomic layers by controlling the kinetic energy” [9].

This presentation will highlight the groundbreaking work and background of the Japanese inventor Seiichi Iwamatsu. Born in 1939 in Kyoto to a family of doctors - his father being a practicing physician- he grew up and studied in Osaka, after which he spent many years as a ‘master inventor’ (over 1200 patents filed in his name) for Seiko Epson (~1970-1990) and others afterwards. He played key roles in thin-film technology and e-beam lithography. He also contributed to the success story of Seiko’s quartz watch, a masterpiece in micromachining a miniature tuning fork from crystalline fused silica, tuning/trimming it to 32,768 Hz (=215 Hz), packaging it in a hermetically sealed case and integrating it with flip-flop frequency dividing and counting electronic circuitry and a step motor [10].

From the above it is clear that Mr. Iwamatsu can be recognized as the original inventor of Atomic Layer Etching.

Source: Late G-5068 - Seiichi Iwamatsu, the Inventor of Atomic Layer Etching: The Conception of Cycled Exposures of Silicon to Halogens and Pulses of Heat, Ions, and More https://ecs.confex.com/ecs/prime2024/meetingapp.cgi/Paper/199461

----------------------------------------------------

Acknowledgement

The authors would like to thank Dr. Masanobu Honda (Tokyo Electron Miyagi Ltd., Japan) for his support in retrieving some of the historic facts mentioned herewith about Dr. Iwamatsu.

References

[1] R.L. Puurunen, Chem. Vap. Deposition 20, pp. 332–344 (2014); doi:10.1002/cvde.201402012.

[2] V.B. Alekskovski and S. I. Kol'tsov, Some characteristics of molecular layering reactions, Abstract of Scientific and Technical Conference, Goskhimizdat, Leningrad, 1965, p. 67 (in Russian).

[3] T. Suntola and J. Antson, FIN 52359, priority Nov. 29, 1974, US Patent 4,058,430, Nov. 15, 1977.

[4] K.J. Kanarik, et al., J. Vac. Sci. Technol. A 33, 020802 (2015); doi/10.1116/1.4913379.

[5] W.M.M. Kessels, www.atomiclimits.com/ March 2, 2020.

[6] M.N. Yoder, Atomic Layer Etching, US Patent 4,756,794, July 12, 1988; assigned to US Navy.

[7] S. Iwamatsu, Atomic Layer Etching Method, JPS5898929A / JPH0379862B2; priority Dec. 9, 1981, published June 13, 1983; assigned to Seiko Epson Corp.

[8] https://worldwide.espacenet.com/patent/search/family/016189802/publication/JPH0472726A?q=iwamatsu%20seiichi%20atomic%20layer%20etching

[9] S. Iwamatsu, Digital Etching Process, JPH0472726A, priority: July 13, 1990, published March 6, 1992; assigned to Seiko Epson Corp.

[10] https://corporate.epson/en/technology/search-by-products/wearable/quartz-watch.html

Lam Research Sees Growth Opportunities in Etch and Deposition Technologies Despite NAND Downturn

In its Q1 2025 earnings call, Lam Research reported strong performance and emphasized growth opportunities, particularly in etch and deposition technology. CEO Tim Archer highlighted optimism for NAND spending recovery in 2025, supported by technology upgrades and a transition to molybdenum through Lam’s advanced Atomic Layer Deposition (ALD). Lam is positioned to capture opportunities in advanced semiconductor nodes like gate-all-around and EUV patterning, while its expanded offerings in high-bandwidth memory (HBM) and advanced packaging align with growing demand in AI and high-performance computing. Despite regulatory challenges in China, Lam continues to serve this market by focusing on upgrades and services. Looking ahead, Lam expects to outpace industry growth, driven by its strategic positioning across advanced technologies.

In its Q1 2025 earnings call, Lam Research Corporation (NASDAQ: LRCX) reported solid performance and reiterated optimism for growth in 2025, largely driven by demand for etch and deposition technologies. CEO Tim Archer emphasized Lam’s strategic positioning in an industry experiencing technological shifts, despite a prolonged downturn in NAND spending.

Lam anticipates a recovery in NAND spending in 2025, largely driven by technology upgrades rather than new capacity expansions. Key factors include a transition from tungsten to molybdenum in NAND structures, which improves performance by reducing resistivity. Lam is well-positioned in this area due to its extensive installed base and production wins, projecting an advantageous position as these upgrades scale into 2025.

NAND Technology Upgrades Set to Drive Etch and Deposition Demand in 2025

While the NAND segment has been in a prolonged downturn, Lam anticipates a recovery in 2025 as manufacturers upgrade to advanced nodes. The push toward 3D NAND layers exceeding 200 is essential to meet the growing demand for high-speed, high-capacity storage in data centers and client devices. Currently, about two-thirds of NAND capacity remains at older technology nodes, highlighting significant room for technology upgrades. Lam’s extensive installed base of NAND equipment positions it well to benefit as customers look to improve efficiency and performance.

Furthermore, Archer highlighted a shift from tungsten to molybdenum as a key materials change in NAND, addressing word line resistance challenges. This transition is particularly favorable for Lam, as it has already secured production wins in molybdenum deposition, which will scale up throughout 2025. These advancements are expected to enhance Lam's leadership position in NAND technology transitions.

Lam's product offerings mentioned in the reporting, along with their primary applications and strategic impacts.

Advanced Logic and Foundry Nodes: Key Growth Segments for Lam

Lam is also poised to benefit from shifts in advanced logic and foundry nodes, which are increasingly adopting gate-all-around architectures, backside power distribution, and advanced EUV patterning. These cutting-edge technologies require more intensive use of etch and deposition processes, aligning with Lam’s expertise and product offerings.

Archer noted the company's recent wins in selective etch tools and other innovations that support these advanced nodes, positioning Lam favorably as customers transition to architectures with greater power and performance needs. This expanding demand from foundry and logic customers offers a substantial growth opportunity for Lam’s advanced etch and deposition technologies.

Advanced Packaging Driven by AI Fuels Revenue Growth

The AI and high-performance computing boom has intensified demand for advanced packaging, particularly for high-bandwidth memory (HBM). Lam’s copper plating technology, SABRE 3D, has experienced substantial adoption, doubling its market share this year. This growth has been fueled by the rising complexity of 2.5D and 3D packages, which require high-performance interconnections to support AI-driven systems.

Lam anticipates this trend will continue into 2025 as the industry moves toward more advanced and intricate packaging solutions. According to Archer, advanced packaging will play a critical role in the semiconductor ecosystem for the foreseeable future, and Lam’s early investment in this technology has positioned it for continued market share gains.

Supporting Installed Base and Productivity in Memory Markets

Lam’s Customer Support Business Group (CSBG) has also shown growth, focusing on productivity enhancements and tool reuse. With Lam’s extensive tool installations in both DRAM and NAND, customers are prioritizing upgrades over entirely new systems, especially as they look to improve cost efficiency during NAND’s down cycle. This focus on tool reuse has led to recent market share gains for Lam, as existing tools are upgraded for better value than new installations.

As DRAM and NAND customers intensify efforts to reduce costs, Lam’s service-oriented model and productivity solutions, including equipment intelligence services, have seen greater adoption. This trend underscores Lam's ability to support its customers' evolving needs in an era of increased etch and deposition intensity.

Lam Research Leverages ALD for Moly Transition in NAND, Driving Next-Gen Semiconductor Performance

Lam Research's perspective on ALD is optimistic, particularly as it becomes increasingly essential in NAND technology upgrades. The company highlighted the industry's ongoing shift from tungsten to molybdenum (moly) for improved resistivity in 3D NAND structures, a transition that Lam’s ALD technology is well-positioned to support. Lam has already secured production wins for ALD applications with molybdenum, expected to ramp up significantly in 2025. This capability extends beyond NAND, with potential applications in DRAM and advanced logic/foundry nodes, underscoring ALD’s growing importance in meeting next-generation semiconductor demands.

Lam Research Adapts to Regulatory Challenges as China Revenue Set to Decline in 2025

In its Q1 2025 earnings presentation, Lam Research highlighted key developments and expectations for the China market. China accounted for roughly 37% of Lam's revenue in the September quarter, but the company anticipates this share will decrease to around 30% by December and potentially decline further in 2025. This projected downturn reflects both anticipated shifts in demand and the impact of U.S. export restrictions on advanced semiconductor equipment sales to China. Lam acknowledged the challenges posed by ongoing and potential new U.S. export controls, which could limit its ability to sell to certain advanced technology segments in China. Nevertheless, Lam remains committed to supporting its domestic Chinese customers within the boundaries of regulatory compliance, expecting demand in restricted segments to normalize as global WFE (wafer fabrication equipment) spending adjusts.

Much of Lam's business in China now focuses on servicing domestic fabs with tools for trailing-edge and specialty node processes, areas that generally remain unaffected by export controls. Through its Reliant product line, Lam continues to support these nodes, emphasizing upgrades and maintenance services as primary offerings in a market constrained by new advanced technology sales. Despite potential reductions in advanced equipment sales, the company is confident that its service and support model will help stabilize revenue in the region. By prioritizing productivity solutions and customer support, Lam is adapting to a complex regulatory environment while anticipating that China’s share of its revenue will gradually normalize amid a broader decline in WFE spending in the country.

Strategic Positioning in 2025 and Beyond

In summary, Lam Research is set to capitalize on a growing demand for etch and deposition technology driven by the industry’s shift to advanced architectures. Archer concluded the call with optimism, stating that the company is well-positioned to capture market share as the semiconductor industry increasingly relies on complex, three-dimensional structures. With its advanced product offerings, Lam expects to outperform overall wafer fabrication equipment (WFE) growth in 2025, strengthening its leadership across multiple semiconductor sectors.

3D Ferroelectric NAND for Ultra-High Efficiency Analog Computing-in-Memory by SK hynix

3D FeNAND with Ultra-High Computing-in-Memory Efficiency: AI models containing up to trillions of parameters require substantial memory resources to handle the vast amounts of data. Energy-efficient analog computing-in-memory (CIM) devices such as 3D vertical NAND architectures are emerging as potential solutions because they offer high areal density and are non-volatile. SK hynix researchers will detail how they achieved analog computation in ultra-high-density 3D vertical ferroelectric NAND (FeNAND) devices for the first time. They used gate stack engineering techniques to improve the analog switching properties of 3D FeNAND cells, and achieved an unprecedented ≥256-conductance-weight levels/cell. The 3D FeNAND arrays improved analog CIM density by 4,000x versus 2D arrays, and demonstrated stable multiply-accumulate (MAC) operations with high accuracy (87.8%) and 1,000x higher computing efficiency (TOPS/mm²) versus 2D arrays. This work provides an efficient method to implement the processing of hyperscale AI models in analog CIM chips for edge computing applications, where speed and low power operation are the critical requirements, not extreme accuracy.

 

Above:

(1)   is a comparison of 2D and 3D arrays for analog-CIM applications.

(2)   is a TEM analysis  of the 3D FeNAND, showing (a) a top-down view of the device; (b) a cross-sectional view at low magnification; (c) a cross-sectional view at high magnification; and (d) a schematic illustration of the FeFET cells in the 3D FeNAND array.

Source: 

IEDM 2024 Paper #38.1, “Analog Computation in Ultra-High Density 3D FeNAND for TB-Level Hyperscale AI Models,” J.-G. Lee and W.-T. Koo et all, SK hynix https://www.ieee-iedm.org/press-kit

4F² DRAM developed by a Kioxia using ALD IGZO

The new 4F² DRAM developed by a Kioxia-led team combines gate-all-around (GAA) IGZO (indium-gallium-zinc oxide) vertical channel transistors (VCTs) with a unique design that places transistors above high-aspect-ratio capacitors to reduce thermal stress and suppress electrical interference like "row hammer." This structure increases memory density and efficiency, providing a high on/off current ratio essential for low-power operation. The team demonstrated a 275Mbit array with this technology, indicating its potential to enable high-density, low-power DRAM for advanced computing applications.

Kioxia is traditionally known for its expertise in NAND flash memory rather than DRAM. They are one of the leading companies in the NAND space, focusing primarily on storage solutions. However, this new venture into DRAM with innovative 4F² cell structures signals an expansion of their research and development scope, possibly to leverage their materials and process expertise in a closely related area. It suggests Kioxia may be exploring ways to diversify its technology portfolio, potentially addressing high-density memory needs beyond traditional NAND storage

ALD offers atomic-level precision and is beneficial for creating uniform, conformal layers of IGZO in complex, high-aspect-ratio surfaces demonstrated here, which is particularly advantageous in advanced semiconductor applications. ALD works by exposing the substrate to alternating pulses of indium, gallium, and zinc precursors, separated by purges to prevent unwanted reactions. This controlled process achieves a smooth and consistent IGZO layer with excellent thickness control, crucial for sensitive electronic applications like DRAM devices.

New Type of 4F² DRAM: DRAM is the workhorse memory of electronic systems, but patterning the extremely small features of conventional silicon 6F² DRAM memory cells and suppressing “row hammer” electrical interference from nearby cells are major challenges. To overcome them, the industry has been actively developing denser 4F² DRAM designs made with different materials. A Kioxia-led team will describe a new type of 4F² DRAM, comprising GAA IGZO (indium-gallium-zinc oxide) vertical channel transistors (VCTs) and a new integration scheme, where the heat-sensitive transistors are placed on the top of high aspect-ratio capacitors instead of on the bottom, to reduce the thermal impact from BEOL processing below. The vertical architecture also fully suppresses row hammer interference, because the active region isn’t shared with adjacent cells. The InGaZnO VCT achieved more than 15µA/cell ON current and 1aA/cell OFF current. The researchers demonstrated the technology by successfully building a 275Mbit array with it, demonstrating its potential for future high-density, low-power DRAM technologies.

 

Above:

(a)   is a schematic of the oxide-semiconductor channel transistor DRAM. The InGaZnO VCT was integrated on a capacitor array, a different architectural scheme from silicon-based 4F2 DRAM devices.

(b)   is a cross-sectional TEM image of the InGaZnO VCT test structure, with the key technologies needed for DRAM applications described on the right nearby. The gate oxide and InGaZnO were formed in a 26nm-diameter vertical hole.

(c)   is a cross-sectional TEM showing the InGaZnO VCTs on high-aspect-ratio capacitors.

 Source:

IEDM2024 Paper #6.1, “Oxide-Semiconductor Channel Transistor DRAM (OCTRAM) with 4F² Architecture,” S. Fujii et al, Kioxia Corp./Nanya Technology Corp. https://www.ieee-iedm.org/press-kit

Intel's Breakthrough in RibbonFET Transistor Scaling Demonstrates Silicon Viability for Future Nodes

For the latest insights from the 2024 IEEE International Electron Devices Meeting (IEDM), including groundbreaking advancements in 2nm CMOS logic, extremely scaled transistors, monolithic CFET inverters, energy-efficient 3D computing-in-memory, and novel device technologies, you can explore the full press kit here.

Extremely Scaled Transistors from Intel: Intel researchers will show that silicon can continue to support the extreme gate length scaling which future technology nodes require. They will describe how they built RibbonFET CMOS transistors (Intel’s version of nanosheets) with 6nm gate lengths at 45nm contacted poly pitch (CPP, the spacing between adjacent transistor gates), with no degradation of electron mobility (how fast electrons can move through a material). The researchers will show that electron mobility doesn’t degrade until 3nm Tsi (silicon thickness), below which electron scattering due to surface roughness becomes an issue. They will describe how they achieved good short channel control (≤100mV/V at <4nm Tsi), with extremely low threshold voltage at these gate lengths through clever workfunction engineering. The work shows that 3nm is a practical scaling limit for RibbonFETs.

The image illustrates the behavior of drain-induced barrier lowering (DIBL) vs. silicon thickness (Tsi) at LG=18nm. It shows a reduction as Tsi is scaled from 10nm to 1.5nm; however, DIBL reduction saturates at Tsi <4nm, below which very little gain is obtained. PMOS DIBL is elevated vs. NMOS DIBL at the same Tsi. Also shown are TEM micrographs of a 1NR transistor with various Tsi values down to 1.5nm.

The series of images are (a) TEM micrograph and EDX scan of a completed 6nm RibbonFET device on a 1NR vehicle, showing a disconnected subfin; (b - d) are high-resolution cross-section TEMs for Tsi=5.5nm, 3.1nm and 1.7nm respectively, at 6nm gate length on a 1NR vehicle

Sources:

IEDM 2024 Press Kit Paper #2.2, “Silicon RibbonFET CMOS at 6nm Gate Length,” A. Agrawal et al, Intel https://www.ieee-iedm.org/press-kit

TSMC 2nm Platform Technology Featuring Energy-Efficient Nanosheet Transistors and Interconnects

TSMC’s New, Industry-Leading 2nm CMOS Logic Platform: In a late-news paper, TSMC researchers will unveil the world’s most advanced logic technology. It is the company’s forthcoming 2nm CMOS (i.e., N2), platform, designed for energy-efficient computing in AI, mobile, and HPC applications. It offers a 15% speed gain (or 30% power reduction) at >1.15x chip density versus the most advanced logic technology currently in production, TSMC’s own 3nm CMOS (N3) platform, introduced in late 2022.

The new N2 platform features GAA nanosheet transistors; middle-/back-end-of-line interconnects with the densest SRAM macro ever reported (~38Mb/mm²); and a holistic, system-technology co-optimized (STCO) architecture offering great design flexibility. That architecture includes a scalable copper-based redistribution layer and a flat passivation layer (for better performance, robust CPI, and seamless 3D integration); and through-silicon vias, or TSVs (for power/signal with F2F/F2B stacking). The researchers say the N2 platform is currently in risk production and scheduled for mass production in 2H’ 25. N2P (5% speed enhanced version of N2) targets to complete qualification in 2025 and mass production in 2026.

The cross-sectional image shows that the N2 platform’s Cu redistribution layer (RDL) and passivation provide seamless integration with 3D technologies.

Graph showing that the new N2 high-density cells gain 14~15% speed@power vs. N3E FinFlex 2-1 fin cells across the Vdd range; a 35% power savings at higher voltage; and a 24% power savings at lower voltage

The graph above compares two CMOS technology nodes, TSMC's N3E and N2, specifically for Arm's A715 core. N3E FinFlex (2-1 Fin) architecture, represented by the blue dotted line, operates at higher power but achieves higher speed than previous nodes. Operating at voltages between 0.5V and 0.9V, the N3E design can achieve significant performance levels but comes with a power increase. Now, N2 NanoFlex HD (High-Density) Energy-Efficient Cells as in the The N2 node, marked by the green dotted line, introduces "NanoFlex" cells that are optimized for energy efficiency. Compared to N3E, it achieves similar speeds but with substantially lower power consumption, marking a shift toward lower power designs in advanced nodes.

Key Improvements:

• When shifting from 0.6V to 0.55V in the N3E architecture, there's a 15% reduction in speed but a 24% reduction in power.
• For N2, at 0.85V, there's a 14% reduction in speed and a 35% reduction in power compared to similar performance points in N3E.
• These efficiency improvements are essential for high-performance applications in power-sensitive environments.

In summary, TSMC's N3E focuses on performance with FinFlex technology, while N2's NanoFlex HD cells target power efficiency, marking a clear trend in CMOS architecture evolution for balancing power and speed.

For the latest insights from the 2024 IEEE International Electron Devices Meeting (IEDM), including groundbreaking advancements in 2nm CMOS logic, extremely scaled transistors, monolithic CFET inverters, energy-efficient 3D computing-in-memory, and novel device technologies, you can explore the full press kit here.

Sources: 

IEDM Press kit Paper #2.1, “2nm Platform Technology Featuring Energy-Efficient Nanosheet Transistors and Interconnects Co-Optimized with 3DIC for AI, HPC and Mobile SoC Applications,” G. Yeap et al, TSMC https://www.ieee-iedm.org/press-kit

GM Ventures Invests $10 Million in Forge Nano to Boost EV Battery Technology with Atomic Armor

GM Ventures, the venture arm of General Motors, recently invested $10 million in Forge Nano, a materials science company known for its advanced battery technology. Forge Nano specializes in Atomic Layer Deposition (ALD), particularly its "Atomic Armor" technology, which enhances battery materials by applying ultra-thin coatings. This innovation improves the performance, lifespan, and charging speed of electric vehicle (EV) batteries. 

“GM Ventures’ primary goal is to bring disruptive technology into the GM ecosystem to improve products and processes,” said Anirvan Coomer, managing director of GM Ventures. “Forge Nano’s Atomic Armor technology has game-changing potential for our battery materials at significant scale. They have already demonstrated the ability to expand cathode capabilities, which is the most expensive battery cell component. This could unlock benefits for customers and the business.”

The investment is part of GM's broader strategy to secure a robust supply chain for its EVs, and the partnership will focus on optimizing battery cathode materials to improve energy density and reduce costs. With this funding, Forge Nano aims to expand its battery coating operations and develop lithium-ion battery prototypes at its Colorado facility. This collaboration is expected to boost the range and fast-charging capabilities of GM’s future EV batteries.

About Forge Nano:

Forge Nano is a materials science company specializing in advanced surface engineering technology, particularly Atomic Layer Deposition (ALD). Its proprietary technology, "Atomic Armor," applies ultra-thin coatings at the atomic scale to improve the performance and durability of materials, particularly for energy storage applications like electric vehicle (EV) batteries. Forge Nano's coatings help enhance battery life, efficiency, and fast-charging capabilities by preventing corrosion and boosting cathode material performance.

Founded in Colorado, Forge Nano has attracted significant investment from major corporations, including General Motors, Volkswagen, LG, and others. The company's solutions extend beyond the automotive industry, targeting sectors such as electronics, aerospace, and defense. With ongoing innovation, Forge Nano aims to revolutionize how materials perform in critical technologies such as semiconductors and batteries.

Sources: 

www.forgenano.com

Forge Nano Receives $10M Investment from GM Ventures to Pursue GM Battery Material Enhancements for Future Electric Vehicles - Forge Nano

ASM launches 200 mm PE2O8 silicon carbide epitaxy system

ASM has launched the PE2O8, a silicon carbide (SiC) epitaxy system designed to enhance power device production with improved yields and reduced costs. The PE2O8 targets key applications in electric vehicles, green energy, and AI data centers, addressing the need for chips with higher power performance in smaller form factors. Its dual-chamber design enables high throughput, process uniformity, and efficient maintenance, while supporting both 6" and 8" wafer processing. With advanced thermal control and recipe transfer capabilities, the PE2O8 system offers high reliability, making it ideal for SiC epitaxy on bare wafers and during chip fabrication.

ASM's PE2O8 is a high-productivity epitaxy system designed for silicon carbide (SiC) applications, enabling the production of power devices with higher yields and lower costs. It plays a crucial role in industries like electric vehicles, green energy, and AI data centers, where chips must meet high power specifications within smaller form factors. The PE2O8 system features dual reactors for easy chamber maintenance, cross-flow hot wall reactors for precise thermal control, and inductive heating for processing 6" and 8" wafers. It ensures process uniformity and recipe transfer from earlier platforms, making it highly reliable and cost-efficient for SiC epitaxy on bare wafers and in power device fabrication.

Raleigh, NC, USA, September 30, 2024 / New system extends ASM’s portfolio of industry benchmark single wafer silicon carbide epitaxy systems, the 6” PE1O6 and 8” PE1O8 systems, with a higher throughput, lower cost of ownership, dual chamber, single wafer, 6” and 8” compatible, silicon carbide epitaxy system.

Today at the 2024 International Conference on Silicon Carbide and Related Materials, ASM International N.V. (Euronext Amsterdam: ASM) introduced the PE2O8 silicon carbide epitaxy system, a new, dual chamber, platform for silicon carbide (SiC) epitaxy (Epi). Designed to address the needs of the advanced SiC power device segment, the PE2O8 is the benchmark epitaxy system for low defectivity, high process uniformity, all with higher throughput and low cost of ownership needed to enable broader adoption of SiC devices.

As the general electrification trend drives more power device manufacturers to utilize SiC for a growing number of high-power applications (such as for electric vehicles, green power, and advanced data centers) the expanded demand and requirements for lower cost for SiC is causing a transition from 6” to 8” SiC substrates. At the same time, SiC device manufacturers are designing higher power devices that will benefit from better SiC epitaxy.

Utilizing a unique design, the dual chamber PE2O8 system deposits SiC with ultra precise control, enabling benchmark higher yield and higher throughput. The highly compact, dual chamber design enables high productivity and low total costs of operation. Additionally, the system features an easy preventive maintenance approach helping to increase uptime and reduce the occurrence of unscheduled downtime. System deliveries have been ongoing to multiple customers globally, among them leaders in SiC power device manufacturing.

“We are at a critical inflection for silicon carbide power products, as our customers transition from 6” to 8” wafers”, said Steven Reiter, Corporate Vice President, and business unit head of Plasma and Epi at ASM. “Delivering a high-quality epitaxy process on larger wafers with defectivity control is critical, and we have been the industry benchmark for process uniformity with our novel chamber design. We have now extended our system capability to improve our process control and our value for customers with lower cost of ownership.”

Since 2022, ASM, through its new SiC Epi product unit has been developing and refining its single wafer SiC epitaxy system. With the structurally higher demand for electric vehicles and improvement of the overall SiC wafer and device yield, the equipment market for SiC epitaxy has grown substantially in recent years.

About ASM International

ASM International N.V., headquartered in Almere, the Netherlands, and its subsidiaries design and manufacture equipment and process solutions to produce semiconductor devices for wafer processing, and have facilities in the United States, Europe, and Asia. ASM International's common stock trades on the Euronext Amsterdam Stock Exchange (symbol: ASM). For more information, visit ASM's website at www.asm.com.

Sources:

PE2O8 SiC epitaxy | ASM