Sunday, July 26, 2015

Growth in Plasma ALD publication for first half of 2015

Plasma-ALD.com reports that there is a clear increase in Plasma ALD publication in the first had of 2015 as compared to 2014 "Through the first six months of 2015, I have collected 112 PEALD publications. Compared to the 51 for this same time period in 2014, this represents a 120% growth. Exciting news for the PEALD community. Now I need to find the time to review them all and get them into the plasma ALD Publication Database."


This confirms the general trend seen that ALD is being used more and more for low thermal budget applications in patterning as well as BEOL and non-semiconductor fields. Also I have heard directly from ALD OEMs that the sales in PEALD has increased lately. Today most OEMs offer a PEALD chamber technology. 

Another clear sign that PEALD is coming strong is that there is actually an after market in converting thermal ALD chambers to PEALD. One such company is Meaglow that offer Plasma upgrades of PEALD chambers as well as complete conversion kits from thermal ALD to PEALD.



Ultra-Thin Hollow Nanocages Could Reduce Platinum Use in Fuel Cell Electrodes

As reported by Georgia Tech : A new fabrication technique that produces platinum hollow nanocages with ultra-thin walls could dramatically reduce the amount of the costly metal needed to provide catalytic activity in such applications as fuel cells.



The technique uses a solution-based method for producing atomic-scale layers of platinum to create hollow, porous structures that can generate catalytic activity both inside and outside the nanocages. The layers are grown on palladium nanocrystal templates, and then the palladium is etched away to leave behind nanocages approximately 20 nanometers in diameter, with between three and six atom-thin layers of platinum.



Use of these nanocage structures in fuel cell electrodes could increase the utilization efficiency of the platinum by a factor of as much as seven, potentially changing the economic viability of the fuel cells.

“We can get the catalytic activity we need by using only a small fraction of the platinum that had been required before,” said Younan Xia, a professor in the Wallace H. Coulter Department of Biomedical Engineering at Georgia Tech and Emory University. Xia also holds joint faculty appointments in the School of Chemistry and Biochemistry and the School of Chemical and Biomolecular Engineering at Georgia Tech. “We have made hollow nanocages of platinum with walls as thin as a few atomic layers because we don’t want to waste any material in the bulk that does not contribute to the catalytic activity.”

The research – which also involved researchers at the University of Wisconsin-Madison, Oak Ridge National Laboratory, Arizona State University and Xiamen University in China – was scheduled to be reported in the July 24 issue of the journal Science.


Friday, July 24, 2015

Video of a Visionox rollable OLED display in production 2017

OLED-Info just uploaded this amazing video of a truly rollable OLED display soon to go into mass production 2017 at Visionox in Mainland China - I do wonder if they use an ALD barrier to reach 3 mm curvature.


Thursday, July 23, 2015

EUV, Atomic Layer Processes and KLA to solve all all Fab Issues at 7 nm and 5 nm

Here is yet another great article in Semiconductor Engineering by Mark Lapedus on the "The race toward the 7nm logic node. He systematically go through and summarize all important issues and technologies and news from SEMICON West from EUV via ALD to KLA ;-)


New technologies after finFETs and how the industry is likely to get there if it can resolve some very tough issues.

The race toward the 7nm logic node officially kicked off in July, when IBM Research, GlobalFoundries and Samsung jointly rolled out what the companies claim are the industry’s first 7nm test chips with functional transistors.

They’re not alone, of course. Intel and TSMC also are racing separately to develop 7nm technology. And in the R&D labs, chipmakers also are working on technologies for 5nm and beyond. Needless to say, the timing and certainty of 7nm and 5nm remain unclear.

In any case, there are two basic transistor candidates at 7nm—the finFETand the lateral gate-all-around nanowire FET, sometimes called the lateral nanowire FET. And at 5nm, the industry is leaning towards the lateral nanowire FET.

[...]
  • Patterning and mask making - EUV, LER
  • Fab flow and variation - CMP
  • Selective processes - ALD, MLD, ALE
  • Interconnects - RC
  • Inspection and metrology - KLA
While you´re at it you should also read this article by Mark Lapedus : 

What Will 7nm And 5nm Look Like? - Delays at 10nm raise questions about what’s next.

http://semiengineering.com/moores-law-slips-again/

Today, the lateral nanowire FET is the sole option at 5nm, according to Imec. Vertical FETs, TFETs and the other technologies have been pushed out to 3nm (!)

First Atomic Layer Etch experiments at Lund Nano Lab

An exciting day today in the middle of Swedish vacation times as we made the first experience with Atomic Layer Etching (ALE) at Lund Nano Lab.


Reza Jafari Jam instructing us and learning all the tricks on etching with the Oxford PlasmalabSystem 100.



We use a Oxford Instrument PlasmalabSystem 100 and the rather well studied Ar-plasma- Purge-Cl2-Purge sequence to etch silicon form the device layer of a 300mm FD-SOI wafer that we diced up in 10x10 mm coupons

 


Our Master student on ALE Sabbir Khan adjusting the first recipe that Dmitry Suyantin wrote before going on a well deserved vacation


The first plasma cycle - you can almost sense the saturation here ...



Unloading the first sample after 10 ALE cycles - looks pretty much like we have removed some Ångströms per cycle here - how many we will have to see when the elipsometer model for the stack is put to test.


Pristine 10x10 mm SOI coupon samples next to the etched one - elipsometer tells us we removed 2-3 Å but the fit is really bad so we need to get that reconfirmed later.

Stay tuned for more updates and yes we will move to etching III/V nanowires as soon as we can say that we master etching silicon layer by layer.

The 37th Int Symposium on Dry Process (DPS2015) in Japan November 5 & 6

The 37th International Symposium on Dry Process (DPS2015) will be held at Awaji Yumebutai International Conference Center, Awaji Island, in Japan, on November 5 & 6, 2015. This year there are a number of interesting talks by invited speakers on Atomic Layer Etching (ALE) form TU Eindhoven, Lam Research, Applied Materials. (Thanks Sabbir Khan for sharing)

The Symposium covers all aspects of the rapidly evolving fields of dry processes, including but not limited to plasma etching and deposition processes, diagnostics and modeling of plasmas and surfaces, and surface modifications by plasmas, for the applications in, e.g., microelectronics, power devices, sensors, environmental protection, biological systems, and medicine. The DPS has provided valuable forums for in-depth discussion among professionals and students working in this exciting field for more than three decades.


Invited speakers and tentative titles(Tentative)

  • Dr. Sebastian Engelmann (IBM Thomas J. Watson Research Ctr.)
    "Improving high aspect ratio processes for logic applications through gas chemistry and plasma discharge optimization"
  • Prof. Erwin Kessels (The Eindhoven University of Technology)
    "Atomic layer deposition and etching: progress and prospects"
  • Dr. Chris Lee (Lam Research Corporation)
    "Challenges of Atomic-layer processing: an industry perspective"
  • Dr. Hirokazu Ueda (Tokyo Electron Ltd. )
    "Conformal doping using a radial line slot antenna microwave plasma source"
  • Dr. Peter Ventzek (Tokyo Electron America, Inc.)
  • Dr. Ying Zhang (Applied Materials Inc.)
    "A New Frontier of Plasma Patterning: Atomic Layer Etch"

Wednesday, July 22, 2015

Oak Ridge researchers make scalable arrays of building blocks for ultrathin electronics

OAK RIDGE, Tenn., July 22, 2015--Semiconductors, metals and insulators must be integrated to make the transistors that are the electronic building blocks of your smartphone, computer and other microchip-enabled devices. Today's transistors are miniscule--a mere 10 nanometers wide--and formed from three-dimensional (3D) crystals.


Complex, scalable arrays of semiconductor heterojunctions -- promising building blocks for future electronics -- were formed within a two-dimensional crystalline monolayer of molybdenum deselenide by converting lithographically exposed regions to molybdenum disulfide using pulsed laser deposition of sulfur atoms. Sulfur atoms (green) replaced selenium atoms (red) in lithographically exposed regions (top) as shown by Raman spectroscopic mapping (bottom). Credit : Oak Ridge National Laboratory, U.S. Dept. of Energy

But a disruptive new technology looms that uses two-dimensional (2D) crystals, just 1 nanometer thick, to enable ultrathin electronics. Scientists worldwide are investigating 2D crystals made from common layered materials to constrain electron transport within just two dimensions. Researchers had previously found ways to lithographically pattern single layers of carbon atoms called graphene into ribbon-like "wires" complete with insulation provided by a similar layer of boron nitride. But until now they have lacked synthesis and processing methods to lithographically pattern junctions between two different semiconductors within a single nanometer-thick layer to form transistors, the building blocks of ultrathin electronic devices.

Now for the first time, researchers at the Department of Energy's Oak Ridge National Laboratory have combined a novel synthesis process with commercial electron-beam lithography techniques to produce arrays of semiconductor junctions in arbitrary patterns within a single, nanometer-thick semiconductor crystal. The process relies upon transforming patterned regions of one existing, single-layer crystal into another. The researchers first grew single, nanometer-thick layers of molybdenum diselenide crystals on substrates and then deposited protective patterns of silicon oxide using standard lithography techniques. Then they bombarded the exposed regions of the crystals with a laser-generated beam of sulfur atoms. The sulfur atoms replaced the selenium atoms in the crystals to form molybdenum disulfide, which has a nearly identical crystal structure. The two semiconductor crystals formed sharp junctions, the desired building blocks of electronics. Nature Communicationsreports the accomplishment.

"We can literally make any kind of pattern that we want," said Masoud Mahjouri-Samani, who co-led the study with David Geohegan. Geohegan, head of ORNL's Nanomaterials Synthesis and Functional Assembly Group at the Center for Nanophase Materials Sciences, is the principal investigator of a Department of Energy basic science project focusing on the growth mechanisms and controlled synthesis of nanomaterials. Millions of 2D building blocks with numerous patterns may be made concurrently, Mahjouri-Samani added. In the future, it might be possible to produce different patterns on the top and bottom of a sheet. Further complexity could be introduced by layering sheets with different patterns.

Added Geohegan, "The development of a scalable, easily implemented process to lithographically pattern and easily form lateral semiconducting heterojunctions within two-dimensional crystals fulfills a critical need for 'building blocks' to enable next-generation ultrathin devices for applications ranging from flexible consumer electronics to solar energy."


Tuning the bandgap


"We chose pulsed laser deposition of sulfur because of the digital control it gives you over the flux of the material that comes to the surface," said Mahjouri-Samani. "You can basically make any kind of intermediate alloy. You can just replace, say, 20 percent of the selenium with sulfur, or 30 percent, or 50 percent." Added Geohegan, "Pulsed laser deposition also lets the kinetic energy of the sulfur atoms be tuned, allowing you to explore a wider range of processing conditions."

It is important that by controlling the ratio of sulfur to selenium within the crystal, the researchers can tune the bandgap of the semiconductors, an attribute that determines electronic and optical properties. To make optoelectronic devices such as electroluminescent displays, microchip fabricators integrate semiconductors with different bandgaps. For example, molybdenum disulfide's bandgap is greater than molybdenum diselenide's. Applying voltage to a crystal containing both semiconductors causes electrons and "holes" (positive charges created when electrons vacate) to move from molybdenum disulfide into molybdenum diselenide and recombine to emit light at the bandgap of molybdenum diselenide. For that reason, engineering the bandgaps of monolayer systems can allow the generation of light with many different colors, as well as enable other applications such as transistors and sensors, Mahjouri-Samani said.

Next the researchers will see if their pulsed laser vaporization and conversion method will work with atoms other than sulfur and selenium. "We're trying to make more complex systems in a 2D plane--integrate more ingredients, put in different building blocks--because at the end of the day, a complete working device needs different semiconductors and metals and insulators," Mahjouri-Samani said.

To understand the process of converting one nanometer-thick crystal into another, the researchers used powerful electron microscopy capabilities available at ORNL, notably atomic-resolution Z-contrast scanning transmission electron microscopy, which was developed at the lab and is now available to scientists worldwide using the Center for Nanophase Materials Sciences. Employing this technique, electron microscopists Andrew Lupini and visiting scientist Leonardo Basile imaged hexagonal networks of individual columns of atoms in the nanometer-thick molybdenum diselenide and molybdenum disulfide crystals.

"We could directly distinguish between sulfur and selenium atoms by their intensities in the image," Lupini said. "These images and electron energy loss spectroscopy allowed the team to characterize the semiconductor heterojunction with atomic precision."


Institute of Solid State Physics at the Bulgarian Academy of Sciences installs ALD and PECVD

The European Seventh Framework Program has funded purchase and installation of several advanced process tool at the Institute of Solid State Physics at the Bulgarian Academy of Sciences. 
  • Beneq TFS 200 Atomic layer Deposition
  • PECVD Oxford Nanofab Plasmalab System 100
INERA Open Days will take place at the Institute of Solid State Physics (BAS) during October 16 – 17, 2015.


The planed event will be designed to ensure that the visitors get detailed information about the project and its progress. They will have the opportunity to visit laboratories, listen to presentations on scientific novelties in different research fields of nanotechnology and its applications and discuss current topics with scientists from the Institute and its Partners within the project.

For more information on the equipment purchased within the framework of the European project INERA click here: http://www.inera.org/research-equipment/




The newly purchased within the framework of the European project INERA, Beneq TFS 200 (above) is a flexible ALD platform designed for research and development. Direct thermal and plasma ALD operation and remote plasma-enhanced deposition (PEALD) are available in the TFS 200 as a standard option. The plasma is capacitively-coupled (CCP), which is the industry standard nowadays. The TFS 200 is capable of coating planar objects and complex 3D shapes with very high aspect ratio features. TFS 200 has unique precursor capabilities of temperature rating up to 400. A total of 6 different gas lines, 4 liquid sources and 3 hot sources fulflil the most demanding requirements.

Available precursors are: DEZ (Diethyl zinc), TMA (Trimethyl aluminum), BTBAS ((Bis(tertiary-butyl- amino)silane)), Ferrocene (bis(η5-cyclopentadienyl)iron), Cobaltocene (Bis(η5-cyclopentadienyl)cobalt), Nickelocene ((Bis(cyclopentadienyl) nickel(II)).

Preliminary tests of pristine and doped ZnO thin films on deposition Al2O3 were successfully performed.
 
 
 
The PECVD system of Oxford Instruments (above)“Nanofab Plasmalab System 100” is a modern multi-purpose tool for various CVD and PECVD processes. The system has a vacuum loadlock and is designed for 2” – 8” wafer or other substrates. The maximal temperature of the substrate holder is 1200 °C which is suitable for deposition of graphene. Both radio-frequency (MHz) and low-frequency (kHz) plasma can be generated in the reaction chamber. The system is equipped with 6 gas lines which allows a variety of chemical processes. In the framework of the project INERA the tool will be used for growth of graphene and carbon nanotubes. 


These modern equipments are installed in a clean room class 10 000 with an area of about 40 m2 (above).
 
 

Tuesday, July 21, 2015

Lab-scale roll-to-roll ALD on textile by Tyndall

ALD growth is unstoppable - There is no end to it "The area certainly seems to show no sign of slowing down" as Maryn Pemble just commented on recent post regarding the latest growth forecast on ALD. Little did I know then while reading it the Tyndall just demonstrated ALD on textile in a spatial roll to roll machine! 




Last year I sat in a meeting with one of Europe's leading coating companies on the topic of ALD on textile and we discussed this topic back and forth if there is a market for it and if it can be done in a roll to roll system. Guess who I will be calling tomorrow morning!


Professor Martyn Pemble, Tyndall National Institute, University College Cork, Ireland (source).

Here are some textile/fibre related posts from the past year - ALD on textile is coming that´s for sure but do check out the video down below from Martyn Pemble and co-workers at Tyndall before!

From Youtube: This movie shows a lab-scale roll-to-roll atomic layer deposition (ALD) system which has been constructed at the Tyndall National Institute, University College Cork, Ireland, by Dr Shane O'Brien and Dr Ian Povey, using funding from Enterprise Ireland and Science Foundation Ireland.




Dr O'Brien and Dr Povey are based in the Advanced Materials and surfaces Group led by Prof Martyn E Pemble. The movie shows the textile sample moving forwards and backwards under the coating heads which supply the ALD precursors. The process is an example of so-called spatial ALD, whereby the precursors are separated spatially rather than in a temporal mode.

For further information please contact Prof Pemble using martyn.pemble@tyndall.ie or go to:

... and did you have enough? No, no I didm´t think so! It turns out that Prof. Pemble is involved in yet another roll to roll ALD project with a team from Sao Paolo, Brazil - check it out!



Designed and built by our colleagues at the university of Sao Paolo, Brazil (Prof Roberto Faria, Mr Leonardo Dias-Cagnani and Ms Giovana Americo-Rosso), this system is currently being used to prepare organic photovoltaics (OPV) and organic LEDs (OLEDs) on flexible transparent polymeric materials. This work is funded by SFI International Strategic Cooperation Award (ISCA) Brazil for which Tyndall are the lead partners in the area of nano materials.




The Nucleation Dependent Growth Layer: A Structure Element in Electrocrystallization - The 10th William Blum Lecture 1969

I was scaning the internet on Kolschuetter and "Atomic Layer" hoping finding proof on the pre-1950´s discovery of ALD (sorry) and came across this rather interesing reviw paper for a lecture in 1969 - Bunching and debunching effects very fascinating indeed and just look how the images and graphs, which are so much more beautiful than today!

"This paper is a re-publication of the 10th William Blum Lecture, presented at the 56th AES Annual Convention in Detroit, Michigan, on June 16, 1969. Prof. Dr. Hellmuth Fischer discussed his work on the theory of plating and how the electrochemistry and use of additives in the bath led to different types of deposit structure"
 
Prof. Dr. Hellmuth Fischer
Recipient of the 1968 William Blum AES Scientific Achievement Award



Originally published as Plating, 56 (11), 1229-1233 (1968).

Editor’s Note: This paper is a re-publication of the 10th William Blum Lecture, presented at the 56th AES Annual Convention in Detroit, Michigan, on June 16, 1969.  A printable PDF version is available by clicking HERE.
ABSTRACT
For the first time, it has been shown by Eichkorn that layer growth (not of growth-spirals) depends on continued nucleation of monoatomic layers building up growth layers.  This has been done by determination of nucleation-overvoltage η and thickness of growth layers.  During formation of growth layers, overvoltage must surpass η and time dependent adsorption of foreign substances must control the motion rate of monoatomic layers.  Growth layers can develop to whiskers, columnar crystals, fiber textures, twinned or randomly dispersed structures.


Subsequent nucleation, outgrowth and "bunching" of atomic layers forming a macrostep.

 

Articles on ALD following SEMICON West 2015

Here are some interesting articles on ALD following SEMICON West 2015. I don´t know what you think but it seems to me that ALD really went one step further 2015! I will update as I find more and if you have seen anything interesting please let me know! (jonas.sundqvist@baldengineering.com)

Semicon West: Forget microelectronics it’s not even nano let’s call it atomtronics

The era of atomic level control of electrical properties have already begun, in that sense the so-called Moore’s law will continue but with the new way of doing things. The researchers in semiconductor manufacturing are both engineers and also equally good material scientists who always explored how to find a way around the technology barricades/walls and also design a manufacturing process in such a way that it can be manufactured in volumes at a cost feasible for business success. So it takes a huge amount of scientific as well as engineering talent and also business knowledge of the industry in this field of semiconductor research.

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Dealing With Atoms


To process chips at the atomic level, there are various solutions in the market today. For years, ALD has been used to scale the capacitor in DRAMs as well as to develop the high-k/metal-gate stack for logic devices. More recently, ALD is also being used to deposit films for the spacers in multiple patterning applications.

In total, the ALD business is expected to reach $920 million to $925 million in 2015, up from $830 million in 2014, according to Applied Materials. Applied Materials, ASMI, Lam, TEL and others compete in the ALD tool market.

ALD is a deposition technique that deposits materials one layer at a time. “ALD is the alternation of two different chemistries being introduced in a sequential manner,” said David Chu, strategic marketing director at Applied Materials. “Because the chemistries are being broken up, it’s self-limiting. That’s why it allows the technology to be conformal.”

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 Growth forecast for Wafer Fab Equipment and ALD according to Gartner

Good news of ALD - Gartner has forecasted a growth for the Advanced nodes to come!
Gartner says that the Worldwide semiconductor revenue is forecast to reach $348 billion in 2015, a 2.2 percent increase from 2014, but down from the previous quarter's forecast of 4.0 percent growth, according to Gartner, Inc.
Growth forecast for Wafer Fab Equipment according to Gartner (Graph from ASMi Investor Technology Seminar at SEMICON West)
 Continue reading : http://baldengineering.blogspot.se/2015/07/growth-forecast-for-wafer-fab-equipment.html

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Imec introduces self-assembled monomolecular organic films to seal ultra-porous low- k materials

Nano-electronics research center imec announced today at SEMICON West that it has demonstrated concept and feasibility for pore-sealing low-k dielectrics in advanced interconnects. The method, based on the self-assembly of an organic monolayer, paves the way to scaling interconnects beyond N5. 


RC plot and HAADF-STEM images illustrating the effectiveness of SAM sealing in preventing metal indiffusion into the ultra-porous low-k film integrated in a 45nm half pitch dual damascene test vehicle. This translates in a 30% decrease in the measured capacitance. (www.imec.be)
 Continue reading : http://baldengineering.blogspot.se/2015/07/imec-introduces-self-assembled.html

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UPDATE: ASM International technology briefing SEMICON West 2015

ASM International N.V.  announces that it will be hosting an analyst and investor technology briefing on Wednesday, July 15, 2015 at 8:00 - 9:30 a.m. (PDT) in San Francisco, US, coinciding with SEMICON West 2015. The presentation will be held in Room 301, Esplanade, Moscone Center.
 
ASMi is operating in a very close relationship with leading IDMs and Imec on CMOS scaling. In this technology seminar Han Westendorp, Vice President Corporate Marketing, will present "Advanced wafer processing with new materials". The presentation will include highlights of ASM's 
  • Advanced thermal ALD
  • Plasma enhanced ALD products and technologies
  • CVD, PECVD and epitaxy technologies
Continue reading: http://baldengineering.blogspot.se/2015/07/asm-international-will-be-hosting.html

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Lam Research Releases High-Productivity VECTOR(R) ALD Oxide Deposition System

Lam Research Corp a major global supplier of innovative wafer fabrication equipment and services to the semiconductor industry, today announced it has released its high-productivity VECTOR® ALD Oxide system on the Extreme platform. The new product uses atomic layer deposition (ALD) to create highly conformal dielectric films with an emphasis on advanced patterning, in particular spacer-based multiple patterning. One key challenge is managing thickness variability of the self-aligned spacers that define critical dimensions (CDs). By delivering superior CD control, VECTOR ALD Oxide has been winning volume-production decisions for multi-patterning applications. Now leveraging Lam's Extreme platform, the latest system meets productivity requirements for continued scaling, where additional steps increase process time, cost, and complexity. As a result, VECTOR ALD Oxide is gaining rapid adoption by a number of leading chipmakers for advanced multi-step patterning applications.


"Multiple patterning continues to be a key inflection for the industry, and spacer-based multi-patterning remains an enabling strategy for chipmakers for both current immersion and future EUV lithography schemes," said Sesha Varadarajan, group vice president, Deposition Product Group. "With this in mind, we are working closely with our customers to deliver cost-effective, extendible solutions required for further scaling, such as the high-productivity atomic-scale control from our VECTOR ALD Oxide product."
 
Continue reading: http://baldengineering.blogspot.se/2015/07/lam-research-releases-high-productivity.html

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Applied Materials announced a next-generation etch tool at SEMICON West

Applied Materials, Inc. announced a next-generation etch tool at SEMICON West, the Applied Centris(TM) Sym3(TM) Etch system, featuring an entirely new chamber for atomic-level precision manufacturing. To overcome within-chip feature variations, the Centris Sym3 system leapfrogs current tools to provide chipmakers with the control and precision needed to pattern and create densely packed 3D structures in advanced memory and logic chips.


Applied Materials Centris Sym3 - an entirely new chamber for atomic-level precision manufacturing 
 

Monday, July 20, 2015

JVSTA Special Issue on Atomic Layer Deposition Deadline Aug 30

Special Issue on Atomic Layer Deposition
JVST A is Soliciting Research Articles for Publication in a Special January/February 2016 Issue on Atomic Layer Deposition
 
Submission Deadline: August 30, 2015
This special issue is planned in collaboration with the 15th International Conference on Atomic Layer Deposition (ALD 2015) to be held in Portland, Oregon during June 28-July 1, 2015. The Special Issue will be dedicated to the science and technology of atomic layer controlled deposition of thin films. While a significant fraction of the articles are expected to be based on material presented at ALD 2015,research articles that are on ALD but were not presented at this conference are also welcome: the special issue will be open to all articles on the science and technology of ALD.

Papers will be reviewed using the same criteria as regular JVST articles and must meet JVST standards for both technical content and written English. To be published in JVST, the manuscript must:  

(1)   present original findings, conclusions or analysis that have not been published previously
(2)   be free of errors and ambiguities,
(3)   support conclusions with data and analysis,
(4)   written clearly, and
(5)   have high impact in its field.

Manuscript Deadline: August 30, 2015     Click Here to Submit   

Article Guidelines & Templates
In preparing your article, you should follow the online instructions for contributors.

Authors are encouraged to use the JVST templates. The easiest way to prepare your manuscript is to use the available JVST Article Template to delete and replace text as necessary.  This file and the template used to create it are available at the site above.  Online, you will have an opportunity to tell us that your paper is a part of the special issue by choosing "ALD Special Issue."

Acceptable manuscript file types are MSWord, LaTeX, and PDF. For the initial submission/review process, a single PDF or MSWord file including the figures is sufficient. However, once a paper is accepted, MSWord or TeX file of the text, any tables and the list of figure captions along with the separate figure files will be required for final production. Use of color in Figures is encouraged. Your FIGURES CAN APPEAR ONLINE IN COLOR FOR FREE. Prepare illustrations in the final published size, not oversized or undersized.

For any other details about manuscript preparation, please refer to the JVST A online instructions.

The Ferroelectric Memory Company - FCM from Dresden

The FeFET is a long-term contender for an ultra-fast, low-power and non-volatile memory technology. In these devices the information is stored as a polarization state of the gate dielectric and can be read non-destructively as a shift of the threshold voltage. The advantage of a FeFET memory compared to the Flash memory is its faster access times, much lower power consumption at high data rates, and the easy integration of the device with common high-k metal gate transistors in complementary metal-oxide-semiconductor (CMOS) technology. 

The basics of the idea of a were already laid in the early 2000s in the research department of the memory manufacturer Qimonda. The discovery of ferroelectricity in doped hafnium led there to the registration of several basic patents, which went to NaMLab gGmbH after the Qimonda insolvency.  

 

In 2013 the proof of principle of a hafnium based ferroelectric field effect transistor (FeFET) memory cell on 28nm technology platform was manufactured at Globalfoundries Fab1 and Fraunhofer CNT in Dresden. There is a hope that the successful commercialization of such an embedded NVM memory technology could have disruptive character.


During the last years the electrical properties of ferroelectric transistors were studied in detail. In the framework of a project together with GLOBALFOUNDRIES and Fraunhofer CNT, which was funded by the Free State of Saxony, silicon doped HfO2 layers were integrated into high-k metal gate transistors in 28 nm CMOS technology. Depending on the polarization state of the ferroelectric gate insulator a memory window in the range of ~1.2 V threshold voltage shift can be reached. Extrapolation of the measured memory window over time indicates a retention time of 10 years with a remaining memory window of 0.4 V. Functional devices with gate length down to ~30 nm were demonstrated.


Today Stefan Müller, Marko Noack and Jörg Andreasas a the team has started The Ferroelectric Memory Company - FCM and currently they are anchored to NaMLab gGmbH and benefits from a The EXIST Research Transfer-financing and support and mentorship by one of the leading semiconductor memory experts Prof. Thomas Mikolajick (Scientific director of NaMLab).

 

TEM of FeFET processed in 28 nm high-k metal gate CMOS Technology (left) and 2D TCAD-model for device simulation (right). (Picture from NaMLab)

 

































SolarWorld AG new world record for PERC-technology solar cells

SolarWorld AG has set a new world record for efficiency of industrially produced solar cells made using so-called PERC-technology (passivated emitter and rear cell). The CalLab of the Fraunhofer Institute for Solar Energy Systems has confirmed that the global manufacturer of premium-quality products surpassed its own record by reaching a new height of 21.7 percent in its solar cell efficiency. 
 
 
 
The cells, based on crystalline p-type silicon wafers, were manufactured using industrial production processes, meaning that they can be quickly placed into mass production. SolarWorld will offer modules with 300-watt and more featuring this technology beginning this fall. 
 
 
 

“SolarWorld has been the first company to rely on PERC in its cell production. With this new record, we expand our technological lead even further. We can offer customers more electricity production on the same area and at the highest quality and durability,” says Dr.-Ing. E. h. Frank Asbeck, CEO of SolarWorld AG. “And our researchers and developers already have an eye on the next efficiency improvements.” 
 
The passivation layer in PERC solar cells, which reflects light that would otherwise be lost is,  usually deposited by PECVD or ALD. I am waiting for a confirmation which process is used in the case of this world record.

Besi and Imec Present High-Accuracy Narrow-Pitch Bonding of 3D ICs using Thermocompression

As published by Imec at SEMICON WEST 2015 (San Francisco), world-leading nano-electronics research center imec and Besi, a global equipment supplier for the semiconductor and electronics industries announced that they have jointly developed an automated thermocompression solution for narrow-pitch die-to-wafer bonding, a method by which singulated dies are stacked onto bottom dies which are still part of a fully intact 300mm wafer. The solution features high accuracy and high throughput, paving the way to a manufacturable 2.5D, 3D, and 2.5D/3D hybrid technology.

   
Caption: 300 mm wafer with ~900 dies processed on Besi’s new 8800 TC bonder tool. Such an assembly can be finished within 1 hour.

3D IC technology, stacking multiple dies into a single device, aims to increase the functionality and performance of next-generation integrated circuits while reducing footprint and power consumption. It is a key technology to enable the next generation of portable electronics, such as smartphones and tablets, which require smaller ICs that consume less power.

One of the challenges to making 3D IC manufacturing an industrial reality is the development of a high-throughput automated process flow for narrow-pitch, high-accuracy die-to-die and die-to-wafer bonding. Thermocompression bonding (TCB) is a widespread process used by the industry for highly accurate die-to-package bonding. The method released the stress in the laminate layer and avoided stress to build up between the two stacked layers. Yet, more traditional approaches to thermocompression bonding come with long cycle times (>1 minute per die), meaning significant improvements in throughput are required to enable this stacking approach on a 300mm wafer.

Imec and Besi have developed an automated TCB process on 300 mm wafers for Besi’s new 8800 TC bonder tool. Imec and Besi demonstrated die-to-wafer bonding at high accuracy, sufficient for 50 µm pitch solder micro bump arrays and a throughput of >1000 UPH with a dual bond head configuration

“Collaborating with imec, leveraging their expertise on fine pitch bonding materials and processes, has enabled us to develop our 8800 TC bonder tool according to the needs of the semiconductor industry,” said Hugo Pristauz at Besi. “This collaboration has helped us to offer our customers a viable and effective solution for 2.5D/3D IC manufacturing, especially for the new C2W applications.”

Nanowires from TU/e give ‘solar fuel cell’ efficiency a tenfold boost

As published by TU Eindhoven - A solar cell that produces fuel rather than electricity. Researchers at Eindhoven University of Technology (TU/e) and FOM Foundation today present a very promising prototype of this in the journal Nature Communications. The material gallium phosphide enables their solar cell to produce the clean fuel hydrogen gas from liquid water. Processing the gallium phosphide in the form of very small nanowires is novel and helps to boost the yield by a factor of ten. And does so using ten thousand times less precious material.


Array of nanowires gallium phosphide made with an electron microscope. Photo: Eindhoven University of Technology.

The electricity produced by a solar cell can be used to set off chemical reactions. If this generates a fuel, then one speaks of solar fuels – a hugely promising replacement for polluting fuels. One of the possibilities is to split liquid water using the electricity that is generated (electrolysis). Among oxygen, this produces hydrogen gas that can be used as a clean fuel in the chemical industry or combusted in fuel cells – in cars for example – to drive engines.

Solar fuel cell

To connect an existing silicon solar cell to a battery that splits the water may well be an efficient solution now but it is a very expensive one. Many researchers are therefore targeting their search at a semiconductor material that is able to both convert sunlight into an electrical charge and split the water, all in one; a kind of ‘solar fuel cell’. Researchers at TU/e and FOM see their dream candidate in gallium phosphide (GaP), a compound of gallium and phosphide that also serves as the basis for specific colored leds.

A tenfold boost

GaP has good electrical properties but the drawback that it cannot easily absorb light when it is a large flat surface as used in GaP solar cells. The researchers have overcome this problem by making a grid of very small GaP nanowires, measuring five hundred nanometers (a millionth of a millimeter) long and ninety nanometers thick. This immediately boosted the yield of hydrogen by a factor of ten to 2.9 percent. A record for GaP cells, even though this is still some way off the fifteen percent achieved by silicon cells coupled to a battery.

Ten thousand times less material

According to research leader and TU/e professor Erik Bakkers, it’s not simply about the yield – where there is still a lot of scope for improvement he points out: “For the nanowires we needed ten thousand less precious GaP material than in cells with a flat surface. That makes these kinds of cells potentially a great deal cheaper,” Bakkers says. “In addition, GaP is also able to extract oxygen from the water – so you then actually have a fuel cell in which you can temporarily store your solar energy. In short, for a solar fuels future we cannot ignore gallium phosphide any longer.”

Reference
Anthony Standing et al., Efficient water reduction with gallium phosphide nanowires, Nature Communications (17 July 2015)
DOI: 10.1038/ncomms8824

Thanks to TG Techno to for posting this one! (http://tgtechno.com/nanotechnologyzone/)