Surface Passivation: A Cornerstone for Advancing Semiconductor Technologies

Modern semiconductor devices like transistors, solar cells, microLEDs, and thin-film transistors all rely heavily on effective surface passivation to enhance performance. As devices continue to evolve toward 3D architectures and smaller form factors, managing surface defects becomes critical to maintaining efficiency. Surface passivation, achieved through thin films deposited by atomic layer deposition (ALD) or similar techniques, minimizes charge carrier recombination at surface sites, thereby boosting the overall performance of semiconductor devices. The latest review paper by Bart Macco, published in the Journal of Vacuum Science and Technology A, provides a comprehensive analysis of surface passivation techniques across silicon, germanium, and III–V materials. The study highlights the importance of atomic-scale processing methods, such as ALD and atomic layer etching (ALE), in meeting the demands of advanced semiconductor architectures. It also explores the emerging trends in high-volume manufacturing of ALD Al₂O₃ layers, novel passivation stacks tailored for different semiconductor materials, and the growing role of in-situ cleaning processes. This review underscores how advancements in passivation methods are shaping next-generation semiconductor devices, addressing both performance and reliability challenges. For more details, the paper is open access and licensed under Creative Commons Attribution and you can also check out the recent post in AtomicLimiuts.com (links below).

Sources: 

Macco, B., et al. "Surface passivation approaches for silicon, germanium, and III–V semiconductors." Journal of Vacuum Science and Technology A.: Surface passivation approaches for silicon, germanium, and III–V semiconductors | Journal of Vacuum Science & Technology A | AIP Publishing

Surface passivation as a cornerstone of modern semiconductor technology – Highlighting a comprehensive review paper on surface passivation for silicon, germanium, and III–V materials – Atomic Limits

2025 Book - Emerging Atomic Layer Deposition for Hydrogen Energy

The book "Emerging Atomic Layer Deposition for Hydrogen Energy" highlights several key applications where Atomic Layer Deposition (ALD) will play a transformative role in advancing hydrogen energy systems. In hydrogen production, ALD is utilized to improve water-splitting catalysts, including both electrochemical and photoelectrochemical (PEC) methods. By coating electrodes with thin, uniform layers, ALD enhances the efficiency and stability of the catalytic process. ALD is also applied to photoelectrodes in solar-driven water splitting to improve light absorption, charge separation, and durability. Additionally, ALD is used to modify proton exchange membranes (PEMs), enhancing their chemical stability and proton conductivity in fuel cells and electrolyzers.

In hydrogen storage, ALD plays a significant role by coating hydrogen storage materials such as metal hydrides, preventing degradation and improving absorption-release cycles. It is also used to create nanostructured hydrogen storage systems, which increase surface area and improve hydrogen uptake capacity. In fuel cell technology, ALD is employed to create thin, dense electrolyte layers in solid oxide fuel cells (SOFCs) and to improve electrode interfaces, enhancing their long-term stability. For proton exchange membrane fuel cells (PEMFCs), ALD helps reduce the use of expensive platinum group metals (PGMs) by improving the performance and durability of non-PGM catalysts. Similarly, ALD enhances the efficiency of alkaline fuel cells by creating durable, high-performing catalyst layers.

ALD may be critical in improving the performance of catalysts and electrodes used in hydrogen energy systems. It enables the coating of non-precious metal catalysts, enhancing their activity and stability. ALD also provides protective layers on catalysts to prevent degradation in harsh chemical environments, ensuring longer device lifespans. In the development of gas diffusion electrodes (GDEs), ALD improves conductivity, hydrophobicity, and corrosion resistance, making them more efficient for fuel cell applications. Furthermore, ALD can be used to create defect-free membranes for hydrogen purification, which are essential for separating and purifying hydrogen in industrial processes.

Other notable applications include the use of ALD in hydrogen sensors, where thin films created by ALD increase the sensitivity and durability of sensing materials. ALD also plays a key role in corrosion protection for hydrogen infrastructure, such as pipelines and storage tanks, by providing thin, protective layers that resist chemical degradation. In solar-driven hydrogen production, ALD improves the stability and efficiency of photocatalysts and enhances the performance of light absorbers by adding anti-reflective and passivation layers. Additionally, ALD is being explored for use in hybrid energy systems that combine hydrogen storage with battery technologies, further demonstrating its versatility in hydrogen-related applications. Overall, ALD’s precise control over material properties makes it a critical enabling technology for advancing hydrogen energy solutions.

Source:

The authors of "Emerging Atomic Layer Deposition for Hydrogen Energy" are primarily affiliated with the University of Johannesburg, South Africa. Dr. Peter Ozaveshe Oviroh holds a PhD in Mechanical Engineering Science from the University of Johannesburg and focuses on advanced material synthesis and energy systems. Dr. Sunday Temitope Oyinbo is a Specially Appointed Researcher at Kyoto University of Advanced Science in Japan, with expertise in hydrogen energy and materials engineering. Dr. Sina Karimzadeh is a Postdoctoral Research Fellow at the University of Johannesburg, contributing to research on thin-film deposition and nanomaterials. Dr. Patrick Ehi Imoisili is a Senior Lecturer and Researcher at the same institution, specializing in materials science and renewable energy technologies. Professor Tien-Chien Jen, also affiliated with the University of Johannesburg, is an accomplished academic recognized as an ASME Fellow, ASSAf Fellow, and SARChI Chair, with extensive expertise in hydrogen energy systems, nanotechnology, and thermal-fluid sciences. Together, the authors bring a diverse range of expertise in materials engineering, hydrogen energy, and atomic layer deposition technologies.

Emerging Atomic Layer Deposition for Hydrogen Energy | springerprofessional.de

Scalable ALD Process for High-Performance MoS₂ Films on Flexible Substrates Unlocks Advanced Electronics Applications

This study by researchers from the University of Southampton (UK), LMU Munich (Germany), and VTT Technical Research Centre of Finland, presents a scalable Atomic Layer Deposition (ALD) method to grow large-area, atomically thin molybdenum disulfide (MoS₂) films with high electrical performance, addressing a key challenge for Transition Metal Dichalcogenides (TMDCs) in commercial semiconductor applications. The ALD process enables precise control over film thickness, stoichiometry, and crystallinity, starting with a MoO₃ layer grown via ALD, followed by a sulfurization process to convert it into MoS₂. This two-step approach decouples film properties, ensuring uniform growth on substrates up to six inches in size. The MoS₂ films are then transferred to flexible substrates using a chemical-free transfer process, resulting in highly uniform films with low surface roughness. Field-effect transistors (FETs) fabricated with these MoS₂ films demonstrate impressive mobility values (up to 55 cm²/Vs), subthreshold slopes as low as 80 mV/dec, and on/off ratios of 10⁷, making them suitable for advanced flexible electronics.

The process begins with 6-inch p-type silicon wafers, onto which a 285 nm layer of thermal SiO₂ is grown at 1000°C using a tube furnace. To enhance the chemical termination of the surface oxide, the wafers are treated in a UV/O₃ reactor for 10 minutes. The subsequent step involves the deposition of MoO₃ via a thermal atomic layer deposition (ALD) process using a Cambridge Nanotech Savannah S200 system. The ALD process utilizes bis(tert-butylimido)bis(dimethylamido) molybdenum as the molybdenum precursor and ozone as the oxidant. By conducting 15 ALD cycles at 250°C, a uniform MoO₃ film with a thickness of 1.31 ± 0.13 nm is achieved across the entire 6-inch wafer, ensuring excellent consistency. This initial MoO₃ layer provides precise control over the number of MoS₂ layers that are subsequently formed, making it a critical step in the overall process.

The study further highlights the integration of MoS₂ in ferroelectric field-effect transistors (FeFETs), which show a memory window of 3 V at ±5 V operation and stable multi-state switching capabilities. These FeFETs, utilizing a thin P(VDF-TrFE) layer as a ferroelectric gate dielectric, offer superior performance compared to traditional flexible memory devices. Electrical measurements confirm the devices’ scalability and uniformity over a 5 × 5 mm² area, with minimal device-to-device variation. The ALD-grown MoS₂ films also retain high stability under repeated bias stress, demonstrating their potential for use in flexible memory and neuromorphic applications. This process provides a commercially viable pathway for integrating high-quality 2D materials into next-generation electronics.

Sources:

Aspiotis, N., Morgan, K., März, B. et al. Large-area synthesis of high electrical performance MoS2 by a commercially scalable atomic layer deposition process. npj 2D Mater Appl 7, 18 (2023). https://doi.org/10.1038/s41699-023-00379-z

Breakthrough in Semiconductor Technology: Amorphous ALD Deposited Nanometal Film Enhances Miniaturization Efficiency

A joint research team from Ajou University in Korea and Stanford University in the US has developed a groundbreaking semiconductor material using an amorphous semi-metallic thin film. Unlike traditional metals that suffer from increased resistivity as they get thinner, this newly discovered material exhibits decreased resistivity when its thickness is reduced. This characteristic addresses a critical challenge in semiconductor miniaturization, where the narrowing of circuit lines impedes electron movement and hampers performance. The material is created by layering niobium (Nb) crystals on a sapphire lattice and covering it with amorphous niobium phosphide (NbP). The research, published in Science, demonstrates that this new material outperforms existing metals like copper and tantalum when the thickness drops below 10 nm, providing a promising solution for next-generation semiconductors.

This amorphous thin film is notable for its compatibility with current semiconductor fabrication processes and its ability to enhance performance without requiring high-temperature treatments. The team plans to further optimize the process using atomic layer deposition (ALD), a method that ensures precise control over film thickness at the atomic scale, making it ideal for advanced semiconductor miniaturization. Professor Oh Il-gwon, who led the research, emphasized the material's potential to overcome existing limitations in semiconductor technologies and its role in securing future industry leadership. This discovery is expected to revolutionize semiconductor wiring processes, improving both efficiency and production costs in the race for smaller, faster, and more efficient chips.

Surface conduction and reduced electrical resistivity in ultrathin noncrystalline NbP semimetal

Asir Intisar Khan https://orcid.org/0000-0003-4635-4667, Akash Ramdas https://orcid.org/0009-0002-4735-7069, Emily Lindgren https://orcid.org/0000-0003-4846-5686, Hyun-Mi Kim https://orcid.org/0000-0002-3916-5617, Byoungjun Won https://orcid.org/0009-0001-6665-1004, Xiangjin Wu, Krishna Saraswat https://orcid.org/0000-0003-1894-6315, Ching-Tzu Chen https://orcid.org/0000-0003-2260-1248, Yuri Suzuki https://orcid.org/0000-0002-6883-4293, [...], and Eric Pop https://orcid.org/0000-0003-0436-8534 +2 authorsAuthors Info & Affiliations

Science

2 Jan 2025

Vol 387, Issue 6729

pp. 62-67

DOI: 10.1126/science.adq7096

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Editor’s summary

Noncrystalline semimetal niobium phosphide has greater surface conductance as nanometer-scale films than the bulk material and could enable applications in nanoscale electronics. Khan et al. grew noncrystalline thin films of niobium phosphide—a material that is a topological semimetal as a crystalline material—as nanocrystals in an amorphous matrix. For films with 1.5-nanometer thickness, this material was more than twice as conductive as copper. —Phil Szuromi

Abstract

The electrical resistivity of conventional metals such as copper is known to increase in thin films as a result of electron-surface scattering, thus limiting the performance of metals in nanoscale electronics. Here, we find an unusual reduction of resistivity with decreasing film thickness in niobium phosphide (NbP) semimetal deposited at relatively low temperatures of 400°C. In films thinner than 5 nanometers, the room temperature resistivity (~34 microhm centimeters for 1.5-nanometer-thick NbP) is up to six times lower than the resistivity of our bulk NbP films, and lower than conventional metals at similar thickness (typically about 100 microhm centimeters). The NbP films are not crystalline but display local nanocrystalline, short-range order within an amorphous matrix. Our analysis suggests that the lower effective resistivity is caused by conduction through surface channels, together with high surface carrier density and sufficiently good mobility as the film thickness is reduced. These results and the fundamental insights obtained here could enable ultrathin, low-resistivity wires for nanoelectronics beyond the limitations of conventional metals.

Sources: 

Surface conduction and reduced electrical resistivity in ultrathin noncrystalline NbP semimetal | Science

Korean and American researchers develop new semiconductor material enhancing performance - CHOSUNBIZ

Driving Next-Generation CMOS Logic: TSMC’s Innovations in Transistor Technologies and AOSFET Advancements

TSMC leads in advanced CMOS logic technologies by continuously innovating dense transistors and interconnect stacks—two core building blocks of high-performance logic chips. The computing capability of any logic technology depends on how densely transistors are interconnected and their switching speed, which is affected by resistive and capacitive circuit loads. TSMC’s R&D efforts focus on developing novel, scalable transistor concepts to maintain cost-effective, energy-efficient solutions for leading-edge logic technology.

Recent advancements in transistor technology include innovations in amorphous oxide semiconductor field-effect transistors (AOSFETs). A 2024 study highlights a new evaluation framework for integrating AOSFETs into back-end-of-line (BEOL) processes. This framework measures performance through five key parameters, including drive current, leakage current, threshold voltage (VTH), subthreshold slope, and stability. The study demonstrates how a tungsten-doped In₂O₃ transistor with a 55 nm channel length and oxide capping layer improves device stability, showcasing progress in low-dimensional materials for next-generation transistors.

Enhancement-mode Atomic Layer Deposited W-doped In2O3 Transistor at 55 nm Channel Length by Oxide Capping Layer with Improved Stability

Intel Pushes Gallium Nitride (GaN) Technology to New Heights with 300mm GaN-on-TRSOI Substrates

Intel Foundry continues to redefine the future of semiconductor technology with groundbreaking advancements in gallium nitride (GaN) technology. At the IEEE International Electron Devices Meeting (IEDM) 2024, Intel showcased the industry’s first 300mm GaN-on-TRSOI substrates, setting a new benchmark for high-performance power and radio frequency (RF) electronics. This innovation is part of Intel’s larger commitment to solving critical challenges in AI, energy efficiency, and thermal management.

The use of 300mm GaN-on-TRSOI substrates enables superior performance by reducing signal loss and enhancing signal linearity. These substrates are engineered to support advanced integration schemes through backside substrate processing, offering significant benefits for applications in RF and power electronics. One of the standout achievements demonstrated was the fabrication of 30nm channel-length enhancement-mode GaN MOSHEMTs (metal-oxide-semiconductor high electron mobility transistors). These transistors achieved remarkable performance metrics, including an Ron x Coff of 80 femtoseconds and an fmax exceeding 500 GHz, making them ideal for cutting-edge RF switches.

Intel’s advancements in GaN technology are complemented by its focus on advanced memory integration, hybrid bonding, and modular system expansion. These innovations are designed to address the growing demands of AI and other high-performance computing applications, paving the way for more energy-efficient and thermally optimized systems. By pushing the boundaries of materials and integration technologies, Intel is positioning itself as a leader in driving semiconductor advancements for the trillion-transistor era.

Source: Intel IEDM 2024 Innovations

Intel Unveils 6 nm Gate Length Silicon RibbonFET CMOS and Breakthroughs in Semiconductor Scaling at IEDM 2024

Intel Corporation / Intel Foundry has demonstrated and extensively characterized gate-all-around Silicon RibbonFET CMOS transistors with a 6 nm gate length (LG). The study showcases nanoribbon silicon thickness (Tsi) scaling down to 3 nm, enhancing short-channel effects without compromising performance. Effective workfunction engineering mitigates threshold voltage increases caused by quantum confinement at scaled Tsi, enabling reduced threshold voltage at highly scaled gate lengths. Injection velocity of 1.13x10^7 cm/s is maintained at LG=6nm without degradation down to Tsi=3 nm, highlighting advancements crucial for continued gate length scaling and the ongoing realization of Moore's Law.

Intel Foundry made groundbreaking announcements at the IEEE International Electron Devices Meeting (IEDM) 2024, showcasing advancements that propel semiconductor technology into the next decade and beyond. Highlights include innovations in transistor and interconnect scaling, advanced packaging, and emerging materials to support the industry’s roadmap toward achieving 1 trillion transistors on a chip by 2030. Intel demonstrated a 25% capacitance reduction using subtractive ruthenium for interconnections, achieved a 100x throughput improvement in advanced packaging through Selective Layer Transfer (SLT), and advanced gate-all-around (GAA) transistor scaling with Silicon RibbonFET CMOS at a 6 nm gate length. Additionally, Intel unveiled new work on gate oxide modules for scaled 2D FETs, addressing the next phase of GAA scaling.

Among the key technical breakthroughs, subtractive ruthenium stands out as a metallization alternative to copper for interconnects, offering significant capacitance reductions at tight pitches while being cost-effective and scalable for high-volume manufacturing. SLT further revolutionizes advanced packaging with ultra-fast, flexible chip-to-chip assembly, enabling smaller, higher-density chiplets for AI and other demanding applications. For transistor scaling, Intel’s demonstration of Silicon RibbonFET CMOS at 6 nm gate length delivers industry-leading short-channel effects and performance, paving the way for continued scaling under Moore’s Law. Additionally, Intel’s progress with 2D GAA NMOS and PMOS transistors and gate oxide development signals readiness for post-silicon semiconductor technologies.

Intel also highlighted progress in gallium nitride (GaN) technology, demonstrating the first 300 mm GaN-on-TRSOI substrates for high-performance power and RF electronics. These developments, alongside Intel’s continued focus on advanced memory integration, hybrid bonding, and modular system expansion, underscore its commitment to addressing challenges in AI, energy efficiency, and thermal management. With these innovations, Intel Foundry continues to lead the charge in semiconductor advancements, ensuring a robust path forward for the trillion-transistor era.

Source: Intel IEDM 2024 Innovations

Decoupling from Dependence: The Global Semiconductor Industry Races to Diversify Amid Geopolitical Risks

The semiconductor industry is at a critical juncture, driven by the dual pressures of rising demand for advanced chips in artificial intelligence (AI) and the urgent need to mitigate geopolitical vulnerabilities. With Taiwan’s fabs, particularly TSMC, supplying over 90% of the world’s cutting-edge semiconductors, nations are rapidly investing in new fabs to reduce reliance on both Taiwan and China. While TSMC, Samsung, and Intel lead efforts to expand capacity in regions like the US, Europe, and Japan, these initiatives fall short of replacing Taiwan’s unparalleled output of 2 nm and below chips by 2030. Simultaneously, China’s struggle to compete at leading-edge nodes, compounded by export restrictions on critical tools, further underscores the fragility of the global semiconductor supply chain. These dynamics signal a transformative era as the free world works to establish more resilient and geographically diversified semiconductor ecosystems.

According to a recent article by FT (Source), the primary drivers for 2 nm technology development are the surging demand for custom and specialized chips, particularly in artificial intelligence (AI), and the need to create competitive alternatives to current large-scale semiconductor manufacturers. Rapidus, for instance, is targeting a niche in the AI market by producing bespoke chips that prioritize efficiency and can outperform more generic chips, such as those produced by Nvidia, in specific applications.

The motivation also includes addressing capacity limitations from dominant players like TSMC, which prioritizes large orders. Rapidus sees an opportunity to capture smaller customers who are willing to pay a premium for speed and customization. Additionally, geopolitical factors are influencing the push for advanced technology, with Japan aiming to reduce reliance on Taiwan's semiconductor manufacturing expertise and establish its own ecosystem for leading-edge production. 

This is why the semiconductor industry is advancing rapidly toward 3 nm and 2 nm process nodes, with leading players outlining production timelines and capacity expansions over the next five years. Below is a detailed overview of these developments, including plans from TSMC, Samsung, Intel, and Rapidus.

The forecast predicts a 540% growth in the global AI semiconductor market between 2020 and 2030, driven by increasing adoption across key segments such as servers, networking, edge devices, and PCs/smartphones. Servers are projected to dominate the market, reflecting the growing demand for AI in data centers and cloud computing, while networking and edge computing are expected to see rapid expansion, driven by real-time processing needs in IoT and automotive applications. Moderate growth is anticipated in the PCs/smartphone segment as AI integration in consumer electronics continues. Tokyo’s recent $65 billion investment in AI and semiconductor industries underscores the importance of this market, which is expected to exceed $400 billion by 2030, highlighting the transformative role of semiconductors in powering AI advancements across industries.

TSMC

Taiwan Semiconductor Manufacturing Company (TSMC) is enhancing its semiconductor fabrication capabilities globally, focusing on 3 nm and 2 nm and below nodes.

• 3 nm Production (Taiwan): TSMC began volume production of its 3 nm process technology in December 2022 at Fab 18, located in the Southern Taiwan Science Park (STSP). Fab 18 consists of eight phases, each featuring a cleanroom area of 58,000 square meters, roughly double the size of a standard logic fab. TSMC has invested over NT$1.86 trillion in Fab 18, creating more than 11,300 high-tech jobs.
  Source

• 2 nm Development (Taiwan): TSMC’s 2 nm process is scheduled for risk production in late 2024 and mass production in 2025. A new facility in Hsinchu Science Park is under construction, with equipment installation set for April 2024.
  Source

• 2 nm (Arizona, USA): TSMC is building a second fab in Arizona to produce 2 nm nodes, with production expected to begin in 2028. A third fab, focused on cutting-edge technologies, is planned for later this decade. This is part of a $40 billion investment, the largest foreign investment in Arizona's history.
  Source

Samsung

Samsung Electronics is expanding its semiconductor manufacturing capabilities in South Korea and the United States, focusing on 3 nm and 2 nm nodes.

• 3 nm Production (South Korea): Samsung began mass production of its first-generation 3 nm chips in the second half of 2022, using its proprietary Multi-Bridge Channel Field-Effect Transistor (MBCFET) technology, a Gate-All-Around (GAA) architecture. Second-generation 3 nm production began in 2023, offering improved energy efficiency and performance.
  Source

• 2 nm Development (South Korea): Samsung plans to start 2 nm production in 2025 for mobile devices, followed by high-performance computing in 2026 and automotive semiconductors by 2027. The 2 nm (SF2) process is expected to deliver a 12% performance increase, 25% power efficiency improvement, and 5% area reduction compared to 3 nm.
  Source

• Taylor Fab (Texas, USA): Samsung is constructing a $17 billion fab in Taylor, Texas. Initially planned for 4 nm production in late 2024, the fab may start directly with 2 nm technology in 2026 to align with Samsung’s broader roadmap.
  Source

Intel

Intel Corporation is investing in global semiconductor manufacturing, focusing on advanced nodes like Intel 3, Intel 20A, and Intel 18A.

• United States: Intel’s Fab 42 in Arizona produces 10 nm chips and is transitioning to Intel 7 and Intel 4 nodes. In Ohio, Intel is building two fabs with a $20 billion investment to produce Intel 18A by the decade's end.
  Source

• Europe: Intel’s Fab 34 in Ireland will produce Intel 4 technology using EUV lithography. In Germany, Intel delayed its is investing €17 billion to construct two fabs in Magdeburg, focusing on advanced nodes.
  Source

• Israel: Intel’s Fab 28 in Kiryat Gat, Israel, is transitioning from 10 nm to Intel 7 and Intel 4 processes. Intel has committed $10 billion to expand this facility.
  Source

Rapidus

Rapidus, a Japanese semiconductor start-up, aims to produce 2 nm chips, positioning itself as a significant player in the advanced semiconductor market.

• 2 nm Development: Rapidus plans to start trial production of 2 nm chips in April 2025, with mass production by 2027. The company is collaborating with IBM to integrate cutting-edge technology, including Extreme Ultraviolet (EUV) lithography.
  Source

• Manufacturing Facilities: Rapidus is building its IIM-1 fab in Chitose City, Hokkaido, Japan. The first EUV machine from ASML is expected to arrive in mid-December 2024.
  Source

• Strategic Approach: Rapidus is rethinking traditional manufacturing models by emphasizing smaller batch production with faster cycle times, aiming for greater efficiency and adaptability.
  Source

SMIC

China’s stake in leading-edge semiconductor manufacturing and AI is hindered by significant technological and geopolitical challenges. While domestic efforts, such as those by SMIC, have made strides in producing 7 nm chips, China remains far behind global leaders like TSMC, Samsung, and Intel, who are advancing toward 2 nm production. Critical dependencies on foreign equipment, such as ASML's EUV lithography machines, and U.S.-led export restrictions on advanced semiconductor tools and high-performance GPUs have further constrained its progress. Although China has invested heavily in AI development, its capabilities remain primarily focused on practical applications like surveillance and automation rather than leading innovation in foundational AI technologies. To conclude, China has an uphill battle to compete in the global semiconductor and AI industries.

Is the free world Decoupling from China and future risk of relying on Taiwan Fabs?

The global semiconductor industry is undergoing significant restructuring as it increasingly decouples from China and prepares for potential decoupling from Taiwan’s fabs. Geopolitical tensions, driven by concerns over China's ambitions toward Taiwan and its own restricted access to advanced chip-making technologies, have accelerated efforts by the US, Europe, and their allies to diversify supply chains and reduce dependency on both regions. Export controls targeting China, including restrictions on advanced chips and manufacturing tools, have prompted heavy investments in domestic semiconductor manufacturing in the US, Japan, South Korea, and Europe. Simultaneously, Taiwan’s pivotal role in leading-edge semiconductor production, dominated by TSMC, has highlighted vulnerabilities, spurring new fabs outside the island, such as TSMC’s facilities in Arizona and Samsung’s in Texas. These shifts reflect a broader trend toward creating more resilient, geographically dispersed semiconductor ecosystems that mitigate risks associated with reliance on any single region for critical technologies.

Current global plans for semiconductor manufacturing expansion aim to reduce dependency on Taiwan but fall short of ensuring sufficient non-Taiwan capacity for 2 nm and below nodes in the near term. Taiwan, led by TSMC, still dominates leading-edge semiconductor production, supplying over 90% of the world’s advanced chips. While significant investments are underway—such as TSMC's Arizona fabs, Samsung’s expansions in South Korea and Texas, and Intel's facilities in the US, Europe, and Israel—these efforts are unlikely to match Taiwan’s scale and technological leadership at 2 nm and below by 2027-2030.

For example, TSMC’s planned Arizona fab is projected to produce 2 nm chips by 2028, but its capacity will be a fraction of TSMC's output in Taiwan. Similarly, Samsung and Intel are progressing toward advanced nodes, but both face challenges in matching TSMC’s efficiency and yield at these cutting-edge technologies. Additionally, the complexity of EUV lithography and the industry's high R&D costs further limit the pace at which non-Taiwan fabs can scale to competitive capacities.

Adisyn Acquires 2D Generation: Pioneering Low-Temperature Graphene for Next-Gen Semiconductors

Israeli-based 2D Generation (2DG), which specializes in graphene-based solutions for semiconductors, has been acquired by ASX-listed Adisyn (ASX:AI1), a provider of tech services for SMEs in the Australian defense sector that has expanded its focus to the semiconductor industry through this acquisition.

Israeli-based 2D Generation (2DG), a pioneer in graphene-based solutions for semiconductors, has been acquired by ASX-listed Adisyn (ASX:AI1), an Australian defense tech services provider now expanding into the semiconductor industry. Adisyn, a founder of the Connecting Chips European Union Joint Undertaking alongside NVIDIA, Valeo, and Applied Materials, gains access to 2DG’s patented low-temperature graphene production technology. Unlike traditional methods requiring temperatures of around 1,000°C—unsuitable for delicate semiconductor chips—2DG’s process uses Atomic Layer Deposition (ALD) to grow graphene below 300°C, ensuring compatibility with chip manufacturing. This breakthrough addresses a critical industry challenge: as transistors shrink, heat generation in interconnects limits performance and reliability. Graphene’s superior conductivity and heat resistance make it a transformative material for interconnects, potentially unlocking faster, more efficient chips. 2DG’s CEO Arye Kohavi emphasizes the technology's importance for overcoming bottlenecks in chip design, with discussions already underway with industry giants like TSMC and Nvidia. As 2DG scales its ALD capabilities, it aims to integrate graphene into next-generation chips, potentially revolutionizing applications from EVs to AI systems and positioning the company as a key player in the semiconductor sector.

Adisyn Ltd (ASX: AI1) has announced the acquisition of a state-of-the-art Atomic Layer Deposition (ALD) machine from Beneq, a leader in deposition technology, to advance its subsidiary 2D Generation Ltd’s innovative semiconductor solutions. The ALD system will enable precise, ultra-thin graphene layering on semiconductor interconnects, addressing critical bottlenecks in chip manufacturing and paving the way for transformative advancements in high-performance computing, including generative AI, data centers, and defense applications. Scheduled for installation within the next 5-6 months, this equipment represents a crucial step in scaling production of graphene-coated interconnects to enhance speed, energy efficiency, and scalability in semiconductor technology.

Recently, 2D Generation has also partnered with M&T Semiconductor, a leading specialty semiconductor advisory firm founded by industry veterans Dr. Itzhak Edrei and Zmira Shterenfeld Lavie, to accelerate the development and commercialization of its groundbreaking graphene technology. This collaboration aims to secure strategic partnerships with semiconductor fabricators, fabless chipmakers, and equipment vendors while prioritizing licensing opportunities and potential buyouts. M&T brings decades of expertise from Tower Semiconductor, leveraging deep industry connections to advance 2DG’s patented sub-300°C graphene coating process, which addresses critical challenges in interconnect performance and scalability. With this partnership, 2DG is positioned to reshape semiconductor manufacturing and drive next-generation chip innovation.

M&T Semiconductor, founded in 2019, is a specialized advisory firm offering strategic consulting, mergers and acquisitions (M&A) services, and research and development (R&D) expertise in the semiconductor industry. Led by industry veterans Dr. Itzhak Edrei, former President of Tower Semiconductor, and Zmira Shterenfeld Lavie, former General Manager at Tower Semiconductor, M&T leverages over three decades of experience to assist clients in refining objectives, scouting technologies, and implementing processes.Their services encompass strategic consulting, M&A facilitation, technology scouting, and implementation, aiming to deliver tangible outcomes and foster partnerships within the semiconductor sector.

Sources:

2DG secures semiconductor advisor to develop initiatives - Adisyn Ltd (ASX:AI1) - Listcorp.

2DG a part of Adisyn to build new graphene for chip mfg

Kalpana Systems Unveils Roll-to-Roll Spatial ALD Tools for Solar, Batteries, and Packaging

Kalpana Systems, a Dutch thin film equipment manufacturer, has launched roll-to-roll spatial atomic layer deposition (sALD) tools, targeting industries such as solar PV, organic light-emitting diodes, batteries, and packaging. The technology focuses on depositing high-quality functional thin layers with atomic precision without causing sputter damage, with initial applications in barrier layer deposition. Since its founding in 2021, the company has developed its first operational machine, raising €3.5 million to transition from prototype to commercial production. The sALD technology supports high throughput industrial processes, enabling deposition of multiple layers with web speeds up to 10 m/min and is designed for integration with other deposition techniques. Two models, the K300 and K600, cater to different market needs, with specifications optimized for flexible electronics, solar cells, and high-speed applications like batteries and packaging.

The sALD equipment addresses stability and durability challenges faced by producers of perovskite and organic solar cells, offering cost-effective encapsulation methods. Both K300 and K600 models can process flexible substrates and are programmable for various operational parameters, making them versatile across roll-to-roll production processes. With lead times of 9–12 months, Kalpana Systems offers customizable customer onboarding support. Backed by investors such as Fairtree Elevant Ventures and SIG InnoVentures, the company emphasizes the uniqueness of its roll-to-roll technology in delivering high volume, rapid production, and wide market adoption. These innovations position Kalpana Systems as a competitive player in thin film deposition, advancing the development of efficient and scalable manufacturing solutions.

Kalpana Systems, founded in 2021 and headquartered in Delft, Netherlands, specializes in high-throughput spatial Atomic Layer Deposition (sALD) technology for thin film coatings on flexible substrates.Their innovative Superspatial ALD technology enables cost-effective production of thin films, facilitating the transition from technological promise to commercial application. The company's solutions are designed to advance sectors such as solid-state batteries, environmentally friendly packaging, and perovskite solar cells.

In July 2024, Kalpana Systems secured €3.5 million in a Series A funding round led by Fairtree Elevant Ventures, SIG InnoVentures, and the Energy Transition Fund Rotterdam.This investment aims to accelerate the development and commercialization of their sALD technology, positioning the company to meet the growing demand for advanced thin film deposition solutions across various industries.

China’s Semiconductor Growth Slows Amid Sanctions, Legacy Chips Drive Output While Advanced Tech Struggle - what about ALD?

China's semiconductor industry is at a crossroads, navigating both growth opportunities and significant challenges. As US sanctions restrict access to critical technologies like EUV lithography, China's ambitions in advanced chip manufacturing are stifled, particularly in areas like AI and next-generation devices. While the country remains a strong player in legacy chip production, driven by robust demand from multinational corporations and its booming EV sector, the lack of advanced capabilities limits its ability to compete globally in cutting-edge technologies. At the same time, Atomic Layer Deposition (ALD), a cornerstone for technologies like GAAFET, DRAM, and 3D NAND, is seeing robust growth globally, with leading OEMs like ASMI, TEL, Applied Materials, and Lam Research emphasizing its pivotal role in scaling advanced architectures. However, China’s ALD market is expected to pivot towards supporting legacy nodes, as geopolitical constraints and domestic manufacturing dynamics shape its future. This evolving landscape underscores a shift in focus, with global players capitalizing on innovation while China's market transitions towards domestic and legacy-driven demand.

China’s semiconductor industry experienced slowing growth in October, reflecting the impact of looming US sanctions on advanced chip manufacturing. While legacy chip production and the EV sector drove industrial growth, advanced semiconductor capabilities remain constrained by restrictions on critical lithography equipment, such as ASML's EUV tools. This has stifled China’s ambitions in leading-edge technologies used in smartphones and AI. Despite producing 353 billion IC units from January to October, a 24.8% year-on-year increase, most of this growth was in legacy chips, heavily demanded by multinational corporations and export markets. Advanced production, meanwhile, lags behind as companies like TSMC and Samsung tighten services to Chinese firms, reflecting a broader global effort to limit China's technological advancement. These restrictions have heightened China's dependence on imported chips, which reached $315 billion in the first 10 months of 2024.

This chart shows the production output of integrated circuits (in hundred million units). China's IC production reflects the semiconductor cycle. The Chinese government sees semiconductors as an important focus for domestic production based on its Made in China 2025 plan. Note: Data for February are the cumulative total of January and February combined.

In Applied Materials' Q4 2024 earnings call, CEO Gary Dickerson highlighted the company's advancements in ALD technology. He emphasized that ALD is crucial for enabling next-generation semiconductor architectures, particularly in the development of gate-all-around transistors and advanced packaging solutions. Dickerson noted that Applied Materials' leadership in ALD positions the company to meet the increasing demand for energy-efficient computing and artificial intelligence applications. Applied Materials reported strong Q4 2024 earnings, highlighting the significant role of China despite challenges from US restrictions. China contributed approximately 30% of revenue, normalized after elevated demand for DRAM and NAND earlier in the year. The company's revenue from ICAPS (IoT, communications, automotive, power, and sensors) nodes remains strong in China, though potential slowing in automotive and industrial sectors may impact future growth. Applied is focusing on advanced materials engineering for cutting-edge technologies like gate-all-around transistors and high-bandwidth memory, areas critical for AI and energy-efficient computing. While China remains a key market for legacy technologies, restrictions on leading-edge technology sales are reshaping Applied’s growth trajectory, emphasizing global collaboration and innovation outside China. Looking ahead, Applied anticipates steady ICAPS demand and continued contributions from China at current levels.

Is the China market gloomy in ALD Equipment demand - hwat does the Tier 1 OMEs report on future ALD demand?

ALD is increasingly vital in semiconductor manufacturing, particularly for Gate-All-Around Field-Effect Transistors (GAAFET), DRAM, and 3D NAND technologies. Leading equipment manufacturers—ASM International (ASMI), Tokyo Electron (TEL), Applied Materials (AMAT), and Lam Research (LAM)—have highlighted ALD's significance in these areas.

ASM International:

ASMI has reported strong demand for its ALD equipment, driven by applications in advanced semiconductor nodes. The company noted that artificial intelligence (AI) and high-performance computing are propelling the need for GAAFET structures, where ALD processes are essential for precise material deposition. ASMI's recent financial results reflect this trend, with increased bookings attributed to robust demand in these sectors. 

Tokyo Electron:

TEL has been focusing on developing ALD technologies to enhance its position in the 3D NAND market. The company announced advancements aimed at improving 3D NAND flash memory production, positioning itself as a competitor to Lam Research in this domain. TEL's efforts underscore the growing importance of ALD in fabricating complex 3D structures required for high-density memory applications. 

Applied Materials:

AMAT has emphasized its leadership in materials engineering, including ALD, to support next-generation semiconductor architectures like GAAFETs. The company highlighted that ALD is crucial for developing advanced transistors and packaging solutions, which are essential for energy-efficient computing and AI applications. AMAT's focus on ALD aligns with the industry's shift towards more complex device structures. 

Lam Research:

LAM has been at the forefront of ALD technology, particularly for memory applications. The company introduced the ALTUS® Max E Series, featuring an all-ALD low-fluorine tungsten fill process, addressing challenges in scaling 3D NAND and DRAM devices. This innovation enables the production of higher aspect ratio structures with improved performance, demonstrating ALD's critical role in advancing memory technologies. 

In summary, leading OEMs recognize ALD as a pivotal technology for advancing semiconductor manufacturing, especially in GAAFET, DRAM, and 3D NAND applications. The continuous development and adoption of ALD processes are essential to meet the industry's evolving demands for higher performance and greater efficiency. 

China's demand for ALD equipment reflects a mixed outlook, influenced by geopolitical restrictions and market dynamics. Advanced semiconductor manufacturing in China faces constraints due to limited access to critical tools like EUV lithography, stifling progress in leading-edge applications like AI and smartphones. However, the market for legacy chip production remains robust, with strong output driven by demand from multinational corporations and export markets. Leading OEMs like Applied Materials and Lam Research report sustained engagement in the Chinese market, particularly in legacy nodes and AI-driven technologies, though future growth may slow due to challenges in automotive and industrial sectors. Despite these hurdles, Tier 1 OEMs, including ASML, have seen better-than-expected sales in China, highlighting its continued relevance in the global semiconductor landscape. Given that ALD is expected to have double digit growth for GAAFET, DRAM and NAND in leading edge nodes and memory going 3D the China market may be less important looking ahead and will transform to a legacy market for domestic and possibly Korean ALD OEMs.

Sources:

Applied Materials, Inc. (AMAT) Q4 2024 Earnings Call Transcript | Seeking Alpha

https://www.techedt.com/chinas-chip-production-slows-in-october-as-us-sanctions-loom

https://en.macromicro.me/collections/4345/mm-semiconductor/316/cn-china-output-of-integrated-circuit