Ferroelectric HfO2 Based Materials and Devices: Current Status and Future Prospects

Ferroelectric Hafnium Oxide Based Materials and Devices: Assessment of Current Status and Future Prospects [OPEN ACCESS]

J. Müller, P. Polakowski, S. Mueller and T. Mikolajick

ECS J. Solid State Sci. Technol. 2015 volume 4, issue 5, N30-N35

Abstract

Bound to complex perovskite systems, ferroelectric random access memory (FRAM) suffers from limited CMOS-compatibility and faces severe scaling issues in today's and future technology nodes. Nevertheless, compared to its current-driven non-volatile memory contenders, the field-driven FRAM excels in terms of low voltage operation and power consumption and therewith has managed to claim embedded as well as stand-alone niche markets. However, in order to overcome this restricted field of application, a material innovation is needed. With the ability to engineer ferroelectricity in HfO₂, a high-k dielectric well established in memory and logic devices, a new material choice for improved manufacturability and scalability of future 1T and 1T-1C ferroelectric memories has emerged. This paper reviews the recent progress in this emerging field and critically assesses its current and future potential. Suitable memory concepts as well as new applications will be proposed accordingly. Moreover, an empirical description of the ferroelectric stabilization in HfO₂ will be given, from which additional dopants as well as alternative stabilization mechanism for this phenomenon can be derived. 

Comparison of the two major flavors of FRAM. 1T-1C: (a) Working principle illustrating the sensing margin / switched polarization P_sw derived from switched charge Q_sw and non-switched polarization P_nsw in the P-E-hysteresis. (b) DRAM-like architecture of FRAM adding a plateline to word- and bitline for bipolar ferroelectric switching. (c) TEM-micrograph and related P-E-hysteresis of a FE-HfO₂ based deep trench capacitor array proving the concept of 3D-integration capability. To illustrate the advantage of this area enhancement, the polarization density is calculated with respect to the lateral footprint of a comparable planar capacitor. 1T: (d) Illustration of the working principle by a graphical representation of the charge neutrality condition in a MFIS stack. Position 1 and 2 of the insulator-semiconductor loadline represents the transition from the ON-state to the OFF-state of the FeFET or vice versa. Accordingly, the gate voltage difference to turn on/off the FeFET can be approximated by 2 · V_C = 2 · E_c · d_FE, i.e. the memory window MW. (e) Disturb resilient AND architecture of the FeFET. (f) TEM-micrograph and related I_D-V_G-hysteresis of a FE-HfO₂ based 28 nm high-k metal gate transistors proving the concept of advanced 1T FRAM scalability

The recent success of smartphones and tablet computers has accelerated the R&D of fast and energy efficient non-volatile semiconductor memories, capable of replacing the conventional SRAM-DRAM-Flash memory hierarchy. These so called emerging memories usually leverage on the fact that certain materials possess the capacity for remembering their electric, magnetic or caloric history. For the extensively investigated ferroelectrics this ability to memorize manifests in atomic dipoles switchable in an external electric field. This unique property renders them the perfect electric switch for semiconductor memories. Consequently, only a few years after the realization of a working transistor the first ferroelectric memory concepts were proposed.

However, more than 60 years and several iterations later it is now clear that the success or failure of FRAM is mainly determined by the proper choice and engineering of the ferroelectric material. Perovskite ferroelectrics and related electrode systems underwent an extensive optimization process to meet the requirements of CMOS integration and are now considered the front up solution in FRAM manufacturing. Nevertheless, those perovskite systems require complex integration schemes and pose scaling limitations on 1T and 1T-1C memory cells that until now remain unsolved. This creates an unbalance between memory performance on the one side and manufacturing and R&D costs on the other side. This dilemma has ever since restricted FRAM to niche markets. 

With the recent demonstration of ferroelectricity in HfO₂-based systems (FE-HfO₂) a CMOS-compatible, highly scalable and manufacturable contender has emerged, that significantly expands the material choice for 1T and 1T-1C ferroelectric memory solutions as well as nanoscale ferroelectric devices. 

In this paper we will review and expand the current understanding of ferroelectricity in HfO₂, as well as discuss future prospects of ferroelectric HfO₂-based devices with respect to scaling, reliability and manufacturability. Opportunities and drawbacks of this disruptive development in ferroelectric material science will be critically examined. 

Continue reading in the full paper with Open Access here.

Highly Selective Directional ALE of Silicon by LAM Research (OPEN ACCESS ARTICLE)

LAM Research, Intel and others are pumping out great publications on Atomic Layer Etching (ALE) at the moment. Here is a good one on Si etchning from LAM Reasearch and I think this is also the first time I come across the term EPC as in "Etching per Cycle" as corresponding to GPC "Growth per Cycle" in ALD. Also the concept of an ALE window is explained. Check out the abstract below or go for the complete article by following the link:

Highly Selective Directional Atomic Layer Etching of Silicon (OPEN ACCESS)

Samantha Tan, Wenbing Yang, Keren J. Kanarik, Thorsten Lill, Vahid Vahedi, Jeff Marks and Richard A. Gottscho

Abstract

Following Moore's Law, feature dimensions will soon reach dimensions on an atomic scale. For the most advanced structures, conventional plasma etch processes are unable to meet the requirement of atomic scale fidelity. The breakthrough that is needed can be found in atomic layer etching or ALE, where greater control can be achieved by separating out the reaction steps. In this paper, we study selective, directional ALE of silicon using plasma assisted chlorine adsorption, specifically selectivities to bulk silicon oxide as well as thin gate oxide. Possible selectivity mechanisms will be discussed. 

As the IC industry approaches sub 10 nm devices, the need for atomic scale fidelity has been recognized. In the field of deposition, atomic layer deposition (ALD) emerged. The driving forces for advancement of ALD were among others conformal deposition in high aspect ratio structures and deposition of dielectrics and metals with atomic layer control. The idea that an analogous technology for removal of material might exist was proposed over 10 years after the discovery of ALD. The number of publications on this so called atomic layer etch (ALE) increased significantly in recent years and now ALE is transitioning from the lab to the fab.

One highly desirable quality of ALE is selectivity. Recently, Hudson et al. verified that a directional oxide ALE process can etch SiO₂ selective to Si₃N₄. Ikeda et al. showed that thermal ALE of germanium can be selective to silicon or SiGe. Thermal etching is isotropic and not directional. Etching of 3D devices requires directionality and selectivity. FinFET gate etching for instance requires overetches of 40 nm and more to clear the silicon between the fins while gate oxide is exposed. As fin heights increase to achieve the required I_on currents while CD's are shrinking further, the amount of overetch is expected to increase even more. During extended plasma exposure, species from the plasma can penetrate into the fin silicon and cause lattice damage and undesired fin recess. This drives the need for new etching approaches such as ALE. 

ALE processes are comprised of single unit steps which repeat in cycles. These single unit steps use the simplest possible chemistry to realize specific surface processes such as activation and removal. In analogy to ALD, ALE single unit steps should have as much self-limitation as possible. Self-limitation or saturation eliminates the influence of transport phenomena which are the root cause of aspect ratio dependent etching or ARDE on a microscopic scale.⁸ On an atomic scale, saturation of the single unit steps should lead to atomic level smoothness of the etching surface.⁵

Another important concept which can be adapted from ALD is the existence of an ideal process window. Figure 1a illustrates the so called “ideal ALD window,” which is defined as the region of nearly ideal ALD behavior between non-ideal regions.³ The graph shows “growth per cycle” or GPC as a function of surface temperature which for chemical surface reactions represents the available energy to overcome reaction barriers. The analogy of an ideal process window for ALE with ion based removal is shown in Fig. 1b. Here, “etch per cycle” or EPC is shown as a function of ion energy. The material to be etched is activated in a first step and the activated layer is removed in a second step by energetic ions. For instance, silicon can be activated by chlorine molecules or radicals and the resulting surface layer of SiCl_x can be removed by low energy noble gas ions. This particular embodiment of ALE is directional since the removal step is directional due to the use of ions that have been accelerated by a plasma sheath or ion beam source. There are other embodiments of ALE as well. For instance, in the absence of directionality in both, the activation and removal step, the result is isotropic ALE. In this case, surface temperature can be used as control variable of the removal step.

Fig. 1. a. Ideal process window for ALD adapted from. Ref. 3 b. Ideal process window for direction ALE. The region called “incomplete removal” in Figure 1b is characterized by ion energies that are insufficient to completely remove the activated surface layer. Under the conditions labeled “ideal ALE window,” the ion energy is chosen to be high enough to remove the activated layer but not the bulk silicon material. A third process regime is labeled “sputtering” and designates a region where the ion energy is high enough to remove bulk material.

The concept of an “ideal ALE window” can be extended to explain etch selectivity. In Fig. 2, material A exhibits an ALE window while material B does not. In the case of material B, the bonding energy of the adsorbed layer is significantly lower than for the bulk material. In this case, the adsorbed species would be removed as atomic species (EPC equals zero) and the removal of the bulk material realized only if the energy reaches the energy needed to sputter the bulk material. If this sputter threshold energy is higher than at least part of the energy range for ideal ALE of material A, high selectivities can be obtained. 

Fig. 2. Schematic of EPC for material A (e.g. silicon) and material B (e.g., silicon oxide) as a function of ion energy.. Hypothetically, infinite etch selectivity can be reached in the energy range that etches material A and not material B.

ASM Pulsar 2000 ALD reactor from Intel for sale on ebay US $74,999.99

ASM Pulsar 2000 ALD reactor from Intel for sale on ebay “This unit was Intel surplus. It is being sold as-is. All we have is the reactor portion.”

You can only imagine how this one maybe was part in the pre development for the introduction of ALD HfO2 at 45 nm. It makes me thinking of the fantastic experience when I started to work on  one of these fresh out of university in the Infineon 200 mm DRAM line in Dresden. I had mine pimped up and could run both high-k and metal nitrides (Al2O3, HfO2, TiN, HfN, TiAlN) I later was forced to sell mine to an US East Cosat company making VR goggles with a Ta2O5 layer.  

This beauty is for sale for only US $74,999.99 on ebay (I got 10x more for mine in 2006...) - Anyone up for crowd founding? I have clean room space!

Check out the pictures below and read this press release from 2000 and the firstt sell of a Pulsar 2000 on a Polygon ASM mainframe to a Japanese customer : 

"ALCVD is an enabling technology which can be scaled down to well below 0.07 um."

ASM International Sells First Atomic Layer CVD Module Attached to Polygon Platform

 

Left side showing the cold source cabinets where you typically find TMA, TiCl4, H2O in small sice bubblers that can be cooled to 15-18 C with a petier element.

 

The right side showing the fantastic integration of the hot source in a furnace directly on to the outer chamber of the reactor - no cold spots here! Perfectly made for delivering HfCl4 and other low vapour pressure solids into the cross flow chamber via inert gas valves.

Here the lid from the outer chamber and the inner chamber has been removed revealing the inside of the cross flow chamber. You can see the gas inlets on the far away side and can imagine the ALD pulse train coming towards you - The Pulsar!

 

Here the hot source furnace (HIG Source) has been opened up showing the hook up connections for the stainless steel ampole containing e.g. solid HfCl4.

 

Here is a patent drawing of the solid precursor sublimator that looks pretty much as the one I used to use if my memory is right. Inside was a quartz crusible with a lid that s at same time the filter for particles that could come from the solid precursor (System for controlling the sublimation of reactants US 7601225 B2)

 

Observation of Nanoscale Processes in Lithium Batteries

Observation and Quantification of Nanoscale Processes in Lithium Batteries by Operando Electrochemical (S)TEM

B. L. Mehdi, J. Qian, E. Nasybulin, C. Park, D. A. Welch, R. Faller, H. Mehta, W. A. Henderson, W. Xu, C. M. Wang, J. E. Evans, J. Liu, J. -G. Zhang, K. T. Mueller, and N. D. Browning
Nano Lett., 2015, 15 (3), pp 2168–2173

 

An operando electrochemical stage for the transmission electron microscope has been configured to form a “Li battery” that is used to quantify the electrochemical processes that occur at the anode during charge/discharge cycling. Of particular importance for these observations is the identification of an image contrast reversal that originates from solid Li being less dense than the surrounding liquid electrolyte and electrode surface. This contrast allows Li to be identified from Li-containing compounds that make up the solid-electrolyte interphase (SEI) layer. By correlating images showing the sequence of Li electrodeposition and the evolution of the SEI layer with simultaneously acquired and calibrated cyclic voltammograms, electrodeposition, and electrolyte breakdown processes can be quantified directly on the nanoscale. This approach opens up intriguing new possibilities to rapidly visualize and test the electrochemical performance of a wide range of electrode/electrolyte combinations for next generation battery systems.

Sol Voltaics makes record-breaking III-V nanowire solar cell

As reported in Compund Semiconductor: Sol Voltaics, based in Lund, Sweden, has announced that it has doubled the previously reported world-record for photovoltaic (PV) conversion efficiency using a GaAs nanowire array (NWA).

As independently verified by Fraunhofer-ISE, Sol Voltaics has demonstrated a 1-sun conversion efficiency of 15.3 percent in a GaAs NWA solar cell, representing a significant milestone towards providing the solar industry with an efficiency boosting tandem film.

This is the highest efficiency reported to date in a III-V NWA solar cell, and twice the prior record for GaAs NWA technology. Control of the high density of surface states of native GaAs is essential for PV applications, and these results, says Sol Voltaics, prove that it has has resolved this challenge in the growth of solar cell nanowires.

"The efficiency of our GaAs nanowires is a critical component of our low cost film. The use of III-V materials in the PV industry has always been a goal but the costs have been prohibitive. Using Sol Voltaic's Aerotaxy nanowire production methodology allows our III-V film to be produced at competitive cost at efficiencies that are industry changing," said Erik Smith, CEO of Sol Voltaics. "We look forward to working with industrial partners on the integration of our technology on to silicon cells so they may make the leap to 27 percent efficiency and beyond."

GaAs has been used in performance-category solar modules for years because of its high conversion efficiencies. The challenge has always been its high cost relative to other solar materials.

The low cost Aerotaxy process invented by Sol Voltaics' founder and Lund University professor Lars Samuelson, reduces the amount of GaAs and other expensive materials required to generate electricity. Nanowires are created by suspending active materials in gases intermingled in precisely controlled environment. The suspended materials bond to form larger, uniform structures: nanowires are literally grown in space.

Aerotaxy generates nanowires within milliseconds, according to the company, and can produce them on a continuous basis at comparatively low temperatures.

The finished nanowire film can be integrated into solar panels or stored indefinitely. A 2012 paper published in Nature details how Samuelson and his team manufactured GaAs nanowires with Aerotaxy.

Continuous gas-phasesynthesis of nanowires with tunable properties 

Magnus Heurlin, Martin H. Magnusson, David Lindgren, Martin Ek, L. Reine Wallenberg, Knut Deppert & Lars Samuelson

Nature 492, 90–94 (06 December 2012)

 

Aerotaxy growth of nanowires. a, Au agglomerate formation; b, Au agglomerate size sorting using a DMA; c, Au agglomerate compaction into spherical particles in a furnace; d, nanowire growth; e, nanowire deposition.

Semiconductor nanowires are key building blocks for the next generation of light-emitting diodes¹, solar cells² and batteries³. To fabricate functional nanowire-based devices on an industrial scale requires an efficient methodology that enables the mass production of nanowires with perfect crystallinity, reproducible and controlled dimensions and material composition, and low cost. So far there have been no reports of reliable methods that can satisfy all of these requirements. Here we show how aerotaxy, an aerosol-based growth method⁴, can be used to grow nanowires continuously with controlled nanoscale dimensions, a high degree of crystallinity and at a remarkable growth rate. In our aerotaxy approach, catalytic size-selected Au aerosol particles induce nucleation and growth of GaAs nanowires with a growth rate of about 1 micrometre per second, which is 20 to 1,000 times higher than previously reported for traditional, substrate-based growth of nanowires made of group III–V materials^{5, 6, 7}. We demonstrate that the method allows sensitive and reproducible control of the nanowire dimensions and shape—and, thus, controlled optical and electronic properties—through the variation of growth temperature, time and Au particle size. Photoluminescence measurements reveal that even as-grown nanowires have good optical properties and excellent spectral uniformity. Detailed transmission electron microscopy investigations show that our aerotaxy-grown nanowires form along one of the four equivalent 111B crystallographic directions in the zincblende unit cell, which is also the preferred growth direction for III–V nanowires seeded by Au particles on a single-crystal substrate. The reported continuous and potentially high-throughput method can be expected substantially to reduce the cost of producing high-quality nanowires and may enable the low-cost fabrication of nanowire-based devices on an industrial scale.

Issues and options for using selective ALD at 5nm

Here is a very good blog by Mark Lapedus on scaling down some additional nodes. Mark Lapedus is Executive Editor for manufacturing at Semiconductor Engineering.

One of the more interesting option for all us ALD freaks besides the NGLs, there is another emerging option—selective deposition. Below I have cut out that part and please do forward any good open avaialble information on this topic to me (jonas.sundqvist@baldengineering.com) or simply post a comment here!

Still in the R&D stage, selective deposition could be used to selectively deposit materials, namely metals on metals and dielectrics on dielectrics, on a device. “There are a lot of people thinking about
this today,” said Girish Dixit, vice president of process applications for Lam Research . “There are many areas that selective deposition could be used in, including doing edges or removing something at the expense of something.

Selective deposition involves the use of special chemistries and existing atomic layer deposition (ALD) tools. It also makes use of molecular layer deposition (MLD), which is similar to ALD. “With MLD,you are typically making something that is primarily an organic,composed of carbon, nitrogen, oxygen and hydrogen. In classic ALD, you are making inorganic materials. There are also hybrids,” said James Engstrom, a professor in the School of Chemical and Biomolecular Engineering at Cornell University. There are some differences between traditional ALD and selective deposition using ALD. “The difference is you somehow trick the ALD process, so that it grows on material A, but does not grow on material B,” Engstrom said.

Selective deposition doesn’t replace lithography, but it does solve a problem—edge placement error. “When you want one thing to line up with another, the ability to control the placement of a feature is getting to be outside the range, because the features are small,” said Gregory Parsons, a professor in the College of Engineering at North Carolina State University.

In a theoretical flow, a lithography tool would first pattern a surface. “So, if there is a pattern available on the surface that you want to selectively deposit, then your material that you are forming would then align to the pattern that is underneath the substrate,” Parsons said. “Instead of a physical mask to align, you would want to use the chemistry of the surface to do the alignment. And if the process can recognize that selective chemical difference, then we can deposit materials exactly where we want.”

Still, the technology is unproven and there are challenges. But if the technology works, it could possibly change the landscape in IC manufacturing. “Once the ball is rolling, and you can do selective deposition on anything, then the applications will expand,” Lam’s Dixit added.

Full Story here: http://semiengineering.com/issues-and-options-at-5nm/#.VQrjFVPwzdg.linkedin

Good papers on the topic:

The use of atomic layer deposition in advanced nanopatterning by Kessels et al

Atomic layer deposition (ALD) is a method that allows for the deposition of thin films with atomic level control of the thickness and an excellent conformality on 3-dimensional surfaces. In recent years, ALD has been implemented in many applications in microelectronics, for which often a patterned film instead of full area coverage is required. This article reviews several approaches for the patterning of ALD-grown films. In addition to conventional methods relying on etching, there has been much interest in nanopatterning by area-selective ALD. Area-selective approaches can eliminate compatibility issues associated with the use of etchants, lift-off chemicals, or resist films. Moreover, the use of ALD as an enabling technology in advanced nanopatterning methods such as spacer defined double patterning or block copolymer lithography is discussed, as well as the application of selective ALD in self-aligned fabrication schemes.

Qimonda’s late legacy: 28nm FeRAM using ALD Ferroelectric HfO2

Qimonda’s late legacy: 28nm FeRAM
By Julien Happich
Electronic Engineering Times Europe January 2015 27

CMOS-COMPATIBLE 28 NM FERAM could become commercially available within three to five years, according to research from a collaborative project between NaMLab at TU Dresden, the Fraunhofer Institute for Photonic Micro Systems (IPMS) and GlobalFoundries. Indeed, smashing all prior research claims on FeRAM and scalable to geometries an order of magnitude smaller than today’s 130nm FeRAM commercial offerings, the results are so promising that they are being included in the current version of the International Technology Roadmap for Semiconductors (ITRS).

A result of a sub-project called ‘Cool Memory’ at Saxonys’ cluster Cool Silicon, the technology relies on newly found ferroelectric effects in doped Hafnium oxide (HfO2). Considering that Hafnium oxide is already commonly used as a high-k gate dielectric in CMOS transistors, the processes are pretty much already in place for its ferroelectric variant, readily scalable with CMOS transistors. So why look at doped Hafnium oxide in the first place? We asked Dr. Thomas Mikolajiick, Professor for Nanoelectronic Materials and Director of the NaMLab, coordinator for Cool Silicon.

“This research goes back to 2007 at DRAM maker Qimonda, when a PhD candidate Tim Böscke was doing research to improve HfO2 as a high-k dielectric for capacitors in dynamic random access memories, using dopants to stabilize the material”, explained Mikolajiick. “At certain dopant concentrations and under specific treatments, Böscke noticed that strange peaks occurred in the CV characteristic of the material, and that it behaved as a ferroelectric. This was totally unexpected!

Full story as a PDF can be downloaded here.

FREE - Overview of Atomic Layer Etching in the Semiconductor Industry by LAM Research (JVSTA)

Overview of Atomic Layer Etching in the Semiconductor Industry

Keren J. Kanarik, Thorsten Lill, Eric A. Hudson, Saravanapriyan Sriraman, Samantha Tan, Jeffrey Marks, Vahid Vahedi and Richard A. Gottscho

 

Atomic layer etching (ALE) is a technique for removing thin layers of material using sequential reaction steps that are self-limiting. ALE has been studied in the laboratory for more than 25 years. Today, it is being driven by the semiconductor industry as an alternative to continuous etching and is viewed as an essential counterpart to atomic layer deposition. As we enter the era of atomic-scale dimensions, there is need to unify the ALE field through increased effectiveness of collaboration between academia and industry, and to help enable the transition from lab to fab. With this in mind, this article provides defining criteria for ALE, along with clarification of some of the terminology and assumptions of this field. To increase understanding of the process, the mechanistic understanding is described for the silicon ALE case study, including the advantages of plasma-assisted processing. A historical overview spanning more than 25 years is provided for silicon, as well as ALE studies on oxides, III-V compounds, and other materials. Together, these processes encompass a variety of implementations, all following the same ALE principles. While the focus is on directional etching, isotropic ALE is also included. As part of this review, the authors also address the role of power pulsing as a predecessor to ALE and examine the outlook of ALE in the manufacturing of advanced semiconductor devices. Download Free

 

European Researchers grow InGaN layers directly on Silicon by PA-MBE

Researchers from Spain, Germany and Italy grows InGaN layers grown directly on Silicon by PA-MBE.

Near-infrared emitting In-rich InGaN layers grown directly on Si: Towards the whole composition range

Pavel Aseev, Paul E. D. Soto Rodriguez, Víctor J. Gómez, Naveed ul Hassan Alvi1, José M. Mánuel, Francisco M. Morales, Juan J. Jiménez, Rafael García, Alexander Senichev, Christoph Lienau, Enrique Calleja and Richard Nötzel

Appl. Phys. Lett. 106, 072102 (2015); http://dx.doi.org/10.1063/1.4909515

The authors report compact and chemically homogeneous In-rich InGaN layers directly grown on Si (111) by plasma-assisted molecular beam epitaxy. High structural and optical quality is evidenced by transmission electron microscopy, near-field scanning optical microscopy, and X-ray diffraction. Photoluminescence emission in the near-infrared is observed up to room temperature covering the important 1.3 and 1.55 μm telecom wavelength bands. The n-InGaN/p-Si interface is ohmic due to the absence of any insulating buffer layers. This qualitatively extends the application fields of III-nitrides and allows their integration with established Si technology.

(a) HRTEM image of the In0.73Ga0.27N/SiNx/Si interface and (b) HAADF image of the InGaN layer, both taken along the [11–20] III-N zone axis. (c) Corresponding SEM image.

Alabama Graphite Finds Natural Graphene in USA

Alabama Graphite is pleased to announce that it has found naturally occurring flake graphene at its Coosa Property in Alabama, USA. The graphene was obtained using an innovative and cost effective process, by Dr. Nitin Chopra of The University of Alabama under our sponsored research partnership.

 

Graphite is made up of multiple layers of graphene stacked on top of each other. Graphene is a single layer of two dimensional (2-D) carbon atoms. Graphene is valued because it exhibits superior electrical, optical, mechanical and thermal properties. It is not only the strongest material known (200 times stronger than steel), but is also one of the most flexible.

“We believe that the discovery of naturally occurring single and multi-layer graphene, on the Coosa Property opens a completely new and unique business dimension for the Company,” stated Ron S. Roda, CEO of Alabama Graphite. “The biggest challenge today for commercial viability of graphene is cost. This presents a very exciting opportunity for our Company.”

“In my opinion, emerging technologies using graphene could greatly benefit from a cost effective processing methodology, with the potential for improved economics and increased production levels relative to any of the current methods used to create synthetic graphene,” commented Dr. Nitin Chopra. “The work done on the Company’s material has the potential to enhance the process of producing scalable, nano-manufactured graphene and graphene-based derivatives.”

Synthetic graphene is currently produced using a variety of expensive, tedious methods that do not lend themselves to large-scale production and are prone to produce defective graphene with uncontrolled flake size. Current synthetic methods for developing graphene include chemical vapor deposition (CVD), mechanical exfoliation, solution exfoliation, and chemo-mechanical methods. This implies higher costs including greater energy consumption, and extended manufacturing time.

The Company and Dr. Chopra continue to jointly develop methodologies to isolate graphene and graphene-based applications. Graphite flakes thinner than 100 nm are of significant interest because of their physical characteristics. Such thin graphite flakes ranging from one 2-D layer of carbon atoms (graphene) or multiple layers of 2-D carbon atoms stacked over each other (multi-layer graphene or graphite nanoplatelets) are of particular interest for developing advanced applications.

As shown in Figure 1 below, a moderately-sized (<5 μm, top right inset) single crystal flake of graphene, from the Coosa Property, is observed with a clearly visible carbon atom arrangement at high resolution (bottom right inset in Figure 1A). These flakes demonstrated very high quality Raman spectral features (G-band intensities, Figure 1B) with the ratio of disordered carbon signature to graphitic carbon signature of around ~0.15±0.05 (ID/IG). In addition, electron transparent flakes (bi-layer and multi-layer graphene) were observed in the analyzed samples.

 

 

Figure 1A) High resolution TEM image of single-layer graphene. Inset (top right) shows low-resolution image of single-layer graphene. Inset (lower right) shows atomic scale TEM image indicating arrangement of carbon atoms (red hexagons) with bond length closely matching that of C-C in graphene network.

 

Figure 1B) Raman spectra for various graphene flakes showing significantly large G-band peak intensity as compared to D and 2D band. This also corresponds to very low I_D/I_G ratio of ~0.15 ± 0.05

 
Rick Keevil, P. Geo., a Director of the Company and VP of Project Development, is a Qualified Person as defined by National Instrument 43-101, has approved the disclosure of the scientific or technical information concerning the Coosa Property contained in this press release.  

A cheap ellipsometer that can be integrated in ALD chambers for in-situ film growth monitoring

A cheap ellipsometer that can be integrated in ALD chambers for in-situ film growth monitoring from Film Sense. Thanks James Greer for posting this one in the ALD LinkedIn Group.

 

Innovative

By sampling discrete bands across the visible spectrum, the Film Sense FS‑1™ Banded Wavelength Ellipsometer realizes many of the benefits of spectroscopic ellipsometry without all the cost and complication.

Powerful

The film thickness and index of refraction of most transparent thin films can be determined with excellent precision and accuracy by a simple 1 second measurement. The multiple wavelength bands of the FS-1 enable the determination of additional sample parameters, such as multiple film thicknesses, surface roughness, and more.

Affordable

The FS‑1 offers the power of Banded Wavelength Ellipsometry™ (BWE), but at the price point of single wavelength ellipsometer and spectroscopic reflectometer systems. The FS‑1 is ideal for measurements in the research lab, classroom, in situ processing environments, industrial control, and more.

FS-1 Banded Wavelength Ellipsometer

FS-1 In Situ Monitoring Capabilities

• Sub-monolayer thickness precision, in real time
• Determine deposition rates and film optical constants n&k, at multiple process conditions, without breaking vacuum
• Monitor and control the deposition of multilayer film structures
• FS-API interface for external software control (LabVIEW™ compatible)
• Applicable to most thin film deposition techniques: Sputtering, ALD, MBE, MOCVD, e‑beam evaporation, etc.

 

Mounting Specifications

• Adapters for mounting the FS-1 light source and detector units to standard 2.75” or 1.33″ conflat vacuum flanges (windows not included)
• Easy to adjust tilt stages for beam alignment
• The FS-1 source and detector units are compact and light (≈1 kg each).
• Can be installed without breaking chamber vacuum

Hybrid copper / graphene nanowires

As published by Phys.org - A new process for coating copper nanowires with graphene has been published by Purdue University - an ultrathin layer of carbon – lowers resistance and heating, suggesting potential applications in computer chips and flexible displays.

Until now it has been difficult to coat copper nanowires with graphene because the process requires chemical vapor deposition at temperatures of about 1,000 degrees Celsius, which degrades copper thin films and small-dimension wires. The researchers have developed a new process that can be performed at about 650 degrees Celsius, preserving the small wires intact, using a procedure called plasma-enhanced chemical vapor deposition (PECVD)

Read more at: http://phys.org/news/2015-03-hybrid-nanowires-eyed-flexible.html#jCp

This illustration depicts a copper nanowire coated with graphene - an ultrathin layer of carbon - which lowers resistance and heating, suggesting potential applications in computer chips and flexible displays. Credit: Purdue University graphic

Chalmers and Thales reduce low-frequency noise in AlInN/GaN HEMTs by ALD/PEALD passivation

As reported by Semiconductor Today, researchers based in Sweden* and France** have been exploring various passivations for reducing low-frequency noise (LFN) in gallium nitride (GaN) high-electron-mobility transistors (HEMTs) with aluminium indium nitride (AlInN) barriers [Thanh NgocThi Do etal, IEEE Electron Device Letters, published online 6 February 2015]. The researchers claim that one of their passivation processes produced the best reported LFN for AlInN/GaNHEMTs.

Effects of surface passivation and deposition methods on the 1/f noise performance of AlInN/AlN/GaN HEMTs

Do, T., Malmros, A. ; Horberg, M. ; Rorsman, N. ; Kuylenstierna, D. ; Gamarra, P. ; Lacam, C. ; Poisson, M. ; Tordjman, M. ; Aubry, R.

Electron Device Letters, IEEE  (Volume:PP ,  Issue: 99 )

This paper reports on effects of Si3N4 and Al2O3 surface passivation as well as different deposition methods on the Low Frequency Noise (LFN) characteristics for AlInN/AlN/GaN High Electron Mobility Transistors (HEMTs). Two samples are passivated with Al2O3, deposited by two different methods: thermal Atomic Layer Deposition (ALD) and plasma-assisted ALD. The third sample is passivated with Si3N4 using Plasma-Enhanced Chemical Vapor Deposition (PECVD). The LFN of the three samples is measured under a bias condition relevant for amplifier and oscillator applications. It is found that the surface passivation has a major impact on the noise level. The best surface passivation, with respect to LFN, is the thermal ALD Al2O3 for which the noise current spectral density measured at 10kHz is 1×10-14 Hz-1 for a bias of Vdd/Idd = 10V/80mA. To the authors’ best knowledge this result sets a standard as the best reported LFN of AlInN/GaN HEMTs. It is also in the same order as good commercial AlGaN/GaN HEMTs reported in literature and thus demonstrates that AlInN/GaN HEMTs, passivated with thermal ALD Al2O3, is a good candidate for millimetre-wave power generation. 

Drain noise current spectra of the three AlInN/AlN/GaN HEMTs versus frequency at 10V, 17mA operating point. (Semiconductor Today, Electron Device Letters, IEEE  (Volume:PP ,  Issue: 99 ) )

* Microwave Electronics Laboratory, Department of Microtechnology and Nanoscience (MC2), Chalmers University of Technology, , Sweden
** The Wide Band Gap Materials Laboratory and the GaN process Laboratory of 3-5 Lab/Thales Research & Technology, Marcoussi, France

US-Ireland UNITE initiative developing 2D transition metal dichalcogenide materials

Ireland's Tyndall National Institute (based at University College Cork) says it is participating in a three-year US-Ireland collaborative project that aims to reduce power consumption and increase battery life in mobile devices. Under the auspices of the US-Ireland Research and Development Partnership (launched in 2006), researchers will explore new semiconducting materials enabling the further miniaturization of transistors.

 

Researchers in the Republic of Ireland (Tyndall National Institute & Dublin City University), Northern Ireland (Queens University Belfast) and the US (University of Texas at Dallas) - funded by €343,000 from Science Foundation Ireland (SFI), £319,859 from Invest Northern Ireland (InvestNI) and $420,000 from the US National Science Foundation (NSF) government agencies respectively - are collaborating to develop ultra-efficient electronic materials through the UNITE project 'Understanding the Nature of Interfaces in Two-Dimensional Electronic Devices'.

UNITE's principal investigators are professor Robert Wallace at the University of Texas at Dallas, professor Greg Hughes at Dublin City University, Dr David McNeill at Queens University Belfast and Dr Paul Hurley at Tyndall National Institute.

UNITE will create and test the properties of atomically thin, two-dimensional layers of transition metal dichalcogenide (TMD) semiconductors. The properties these materials have displayed to date suggest that they could facilitate extremely efficient power usage and high-performance computing.

"Materials that we are currently reliant on, such as silicon, are soon expected to reach the limit of their performance," says Hurley. "If we want to continue to increase performance, while maintaining or even reducing power consumption, it is important to explore these new TMD materials."

Specifically, UNITE is investigating the synthesis, device fabrication and characterization of 2D TMDs for applications in low-voltage tunnel field-effect transistors. The researchers will explore two separate routes to large-area synthesis through van der Waals epitaxy and atomic layer deposition (ALD). In parallel, characterization and understanding of the surfaces and interfacial regions between commercially available bulk crystals and technologically relevant contacts and insulators will be conducted. This will be accomplished using a combination of in-situ and ex-situ characterization covering questions such as: how can 2D semiconductor surfaces be functionalized to allow uniform and continuous oxide thin films to be formed by ALD; can capacitance-voltage based metrology be applied to metal-oxide-semiconductor systems on 2D semiconductor surfaces; what is the nature of conduction for metal contacts on 2D semiconductors; and how are the atomic-scale electrical properties related to larger-area contacts. The development of growth methods for large-area substrates will not only demonstrate the potential to move 2D semiconductor-based transistors from research to production, but will also provide a source of technologically interesting 2D semiconductor materials for basic study that are not commonly available through geological sources. Finally, the growth and characterization studies will be applied to the fabrication of a tunnel field-effect transistor based on 2D heterostructures.

It is reckoned that, if the UNITE team can understand the issues relating to large-area 2D synthesis, uniform insulator deposition, ohmic contact formation, and charge transport in single- or few-layer 2D semiconductors, then this knowledge will be relevant to a range of potential device architectures.

The application of such 2D TMD materials in transistors could hence not only prolong the battery charge life of portable devices and phones, but also have applications in larger more power-intensive operations such as data storage and server centres. This will have environmental benefits through the reduction of electrical energy consumed by information and communication technologies as well as benefitting consumers.

UNITE builds on the previous US-Ireland collaborative project 'FOCUS' between these academic research partners. The success of this project played a role in demonstrating why funders should back the new project, including training five graduate students in the USA and Ireland, as well as student exchanges between the institutes.

Spatial ALD at low temperature for flexible electronics encapsulation using a BENEQ R2R

A recent paper on Spatial ALD at low temperature for flexible electronics encapsulation using a BENEQ R2R system at Advanced Surface Technology Research Laboratory Team (ASTRaL), Laboratory of Green Chemistry, Lappeenranta University of Technology, Finland. Thanks Henrik Pedersen for finding this one!

Spatial atomic layer deposition: Performance of low temperature H2O and O3 oxidant chemistry for flexible electronics encapsulation

Philipp S. Maydannik, Alexander Plyushch, Mika Sillanpää, and David C. Cameron

Water and oxygen were compared as oxidizing agents for the Al2O3 atomic layer deposition process using spatial atomic layer deposition reactor. The influence of the precursor dose on the deposition rate and refractive index, which was used as a proxy for film density, was measured as a function of residence time, defined as the time which the moving substrate spent within one precursor gas zone. The effect of temperature on the growth characteristics was also measured. The water-based process gave faster deposition rates and higher refractive indices but the ozone process allowed deposition to take place at lower temperatures while still maintaining good film quality. In general, processes based on both oxidation chemistries were able to produce excellent moisture barrier films with water vapor transmission rate levels of 10−4 g/m2 day measured at 38 °C and 90% of relative humidity on polyethylene naphthalate substrates. However, the best result of <5 × 10−5 was obtained at 100 °C process temperature with water as precursor.

Schematic view of modified SALD TFS200R reactor with drum and N2 and precursor inlet, and exhaust ports. J. Vac. Sci. Technol. A 33, 031603 (2015); http://dx.doi.org/10.1116/1.49140

Close up inside the drum of the Beneq TFS 200R, which is  designed for research in Roll-to-Roll atomic layer deposition (ALD) and other forms of continuous ALD (CALD). (www.beneq.com)

Information from BENEQ.com: In the TFS 200R, the flexible substrate is fixed on a rotating cylinder within the reaction chamber. The cylinder itself is surrounded by a number of linear nozzles, each creating an isolated gas region over the full width of the substrate. As the cylinder is rotated, the substrate passes through different gas regions and is coated.

The Beneq TFS 200R, with its robust and modular structure, is designed to meet both industrial standards and the flexibility requirements of research today. Precursor containers are conveniently small, and they can be easily changed. Depending on the process needs, the TFS 200R can be equipped with up to 2 heated sources, type HS 80 and/or HS 180. Additionally, the system can be equipped with up to 8 gas lines and up to 4 liquid sources.