Researchers have a
method to synthesize graphene at the wafer-scale. Their work, published
in Applied Physics Letters, makes large-area synthesis of graphene
compatible with silicon microelectronics.
In the last decade, graphene has been intensively studied for its unique
optical, mechanical, electrical and structural properties. The
one-atom-thick carbon sheets could revolutionize the way electronic
devices are manufactured and lead to faster transistors, cheaper solar
cells, new types of sensors and more efficient bioelectric sensory
devices.
As a potential contact electrode and interconnection material,
wafer-scale graphene could be an essential component in microelectronic
circuits, but most graphene fabrication methods are not compatible with
silicon microelectronics, thus blocking graphene's leap from potential
wonder material to actual profit-maker.
“For integrating graphene into advanced silicon microelectronics,
large-area graphene free of wrinkles, tears and residues must be
deposited on silicon wafers at low temperatures, which cannot be
achieved with conventional graphene synthesis techniques as they often
require high temperatures,” explained Professor Kim Jihyun of Korea
University. Read more from Asian Scientist Magazine at:
http://www.asianscientist.com/2015/08/tech/korea-wafer-scale-graphene-silicon-microelectronics/
As reported by AZONano: A team of researchers from
Korea University, Seoul, has developed an easy and scalable technique for growing graphene, and have synthetically produced high-quality, multi-layer, wafer-scale graphene on silicon substrates. This latest breakthrough paves the way for using graphene in silicon microelectronics on a commercial scale. The study has been published in AIP Publishing’s journal Applied Physics Letters.
Wafer-scale (4 inch in diameter) synthesis of multi-layer graphene using
high-temperature carbon ion implantation on nickel / SiO2 /silicon.
CREDIT: J.Kim/Korea University, Korea
Full story:
http://www.azonano.com/news.aspx?newsID=33336
Wafer-scale synthesis of multi-layer graphene by high-temperature carbon ion implantation
Janghyuk Kim, Geonyeop Lee and Jihyun Kim
Appl. Phys. Lett. 107, 033104 (2015);
http://dx.doi.org/10.1063/1.4926605
Schematics of (a) E-beam evaporation of Ni on SiO2/Si substrate, (b) carbon ion implantation into Ni, (c) post-implantation activation annealing at various conditions, and (d) graphene synthesized on both sides of Ni layer. (e) Diagram of the post-implantation activation annealing conditions.
Citation: Appl. Phys. Lett. 107, 033104 (2015); http://dx.doi.org/10.1063/1.4926605
We report on the synthesis of wafer-scale (4 in. in diameter) high-quality multi-layer graphene using high-temperature carbon ion implantation on thin Ni films on a substrate of SiO2/Si. Carbon ions were bombarded at 20 keV and a dose of 1 × 1015 cm−2 onto the surface of the Ni/SiO2/Si substrate at a temperature of 500 °C. This was followed by high-temperature activation annealing (600–900 °C) to form a sp2-bonded honeycomb structure. The effects of post-implantation activation annealing conditions were systematically investigated by micro-Raman spectroscopy and transmission electron microscopy. Carbon ion implantation at elevated temperatures allowed a lower activation annealing temperature for fabricating large-area graphene. Our results indicate that carbon-ion implantation provides a facile and direct route for integrating graphene with Si microelectronics
Researchers have a
method to synthesize graphene at the wafer-scale. Their work, published
in Applied Physics Letters, makes large-area synthesis of graphene
compatible with silicon microelectronics.
In the last decade, graphene has been intensively studied for its unique
optical, mechanical, electrical and structural properties. The
one-atom-thick carbon sheets could revolutionize the way electronic
devices are manufactured and lead to faster transistors, cheaper solar
cells, new types of sensors and more efficient bioelectric sensory
devices.
As a potential contact electrode and interconnection material,
wafer-scale graphene could be an essential component in microelectronic
circuits, but most graphene fabrication methods are not compatible with
silicon microelectronics, thus blocking graphene's leap from potential
wonder material to actual profit-maker.
“For integrating graphene into advanced silicon microelectronics,
large-area graphene free of wrinkles, tears and residues must be
deposited on silicon wafers at low temperatures, which cannot be
achieved with conventional graphene synthesis techniques as they often
require high temperatures,” explained Professor Kim Jihyun of Korea
University. Read more from Asian Scientist Magazine at:
http://www.asianscientist.com/2015/08/tech/korea-wafer-scale-graphene-silicon-microelectronics/
%20(1).png)
