Silicon Nanowire Remains Favorite to Replace FinFET

VLSI 2015 is going on and there are a lot of interesting information flowing from there and especially on the future of CMOS scaling. Here is a good article on what´s next after FinFET by Peter Clarke. He is claiming that Silicon Nanowires is the most probable path, i.e., not III/V on silicon: Silicon Nanowire Remains Favorite to Replace FinFET. The article is based on the published information and opinions from ARM, Imec, and Prof. Asenov and tries to give insights to some of the major questions and possible issues:

• Vertical or Lateral?
• With or without EUV?
• What Material?

Below some of the statements made by the experts in the article by Peter Clarke. Please do read the article for the full story here (IHS Electronics360).

Prof. Asen Asenov of Glasgow University and CEO of Gold Standard Simulations

Asenov says, "I do not think that there is a real alternative to NWTs. They are a natural progression to FinFETs. Think of it like this: MOSFET—gate on the side of the channel; FinFET—gate on three sides of the channel; NWT or gate all around—gate on four sides of the channel." In a word, ultimate control of the current.

Aaron Thean, logic research director at IMEC.

"At IMEC we look at silicon, silicon-germanium and III-V channel materials but the preference is silicon." Other materials suffer from immaturity. "You have to ask what is the value proposition for these materials? SiGe improves mobility but there are issues of reliability. It is very difficult to passivate the surface." So for Thean, at least, progress is likely to be based in silicon with first-scaled FinFET. That means a taller fin, then movement to lateral nanowire transistors. But it still needs some level of innovation, he says.

Lucian Shifren, principal engineer at ARM.

"Gate-all-around silicon is most likely for a 'real' 7nm," Shifren says. He adds that the nominal 7nm would likely be a pseudo-scaled FinFET and that the nominal 5nm process would be gate-all-around.

New RASIRC Peroxidizer Delivers High Concentration Hydrogen Peroxide Gas into Semiconductor Processes

Today, RASIRC publicly announced the Peroxidizer, a high concentration hydrogen peroxide (H2O2) vaporizer designed specifically for the needs of next generation semiconductor processes, These include Atomic Layer Deposition (ALD), annealing, cleaning and etching. The Peroxidizer is the first commercial vaporizer capable of delivering concentrations greater than 5% H2O2 gas by volume from 30% H2O2 liquid source. Delivered droplet-free and at temperatures as low as 80C, H2O2 is a superior oxidant for use with new semiconductor materials and processes that are sensitive to high temperature and defects. The Peroxidizer delivers 10 times higher concentration than the previous technology it replaces.

The Peroxidizer eliminates problems associated with other oxidants used in semiconductor fabrication processes. Ozone and oxygen plasma are too aggressive, penetrating below the interface layer and damaging both surface structures and the bottom electrode. Both ozone and water have greater steric hindrance than H2O2, resulting in a less dense interface layer. In addition, plasma cannot deeply penetrate high aspect structures, resulting in non-uniform coatings. Water is less reactive than H2O2 gas. Water requires higher process temperatures, which makes it a poor choice with new materials, new precursors, and lower thermal budgets.

The Internet of Things requires low power and high performance semiconductor devices, which will only be enabled through new materials and 3D architectures, explains Jeffrey Spiegelman, RASIRC Founder and President. However, these new devices can only be processed at lower temperatures and their complicated physical structures make deposition and cleaning a new challenge for the semiconductor industry. The Peroxidizer is the first tool to enable stable and particle-free delivery of high concentration hydrogen peroxide gas, enabling lower process temperatures, greater use of new materials and high process throughput. It is really exciting to bring an old molecule to market in a completely new state.

The Peroxidizer is the latest innovation in high purity gas generating products from RASIRC. Its Stabilized Gas Delivery system was the first in the industry to deliver high purity, stable H2O2 gas by overcoming Raoults Law, which causes preferential selection of water molecules from H2O2 solution. The SGD used pre-humidification to ensure that the liquid H2O2 source remained at constant concentration while delivering H2O2 gas to process at a 50:1 water to H2O2 molar ratio. The Peroxidizer further reduces that ratio to 4:1, allowing as much as 5% H2O2 gas by volume to flow to process. The Peroxidizer eliminates the pre-humidification step by concentrating the liquid source until the molar ratio in the headspace reaches 4:1.

Atomic Layer Deposition (ALD)

H2O2 gas is more reactive than water at low temperatures. The Peroxidizer delivers H2O2 gas at temperatures as low as 80C, well below the H2O2 liquid boiling point. Low delivery temperatures enlarge the available thermal budget.

H2O2 gas achieves higher density nucleation than other oxidants. H2O2 has less steric hindrance than water or ozone because it decomposes into hydroxyls on surfaces. The resulting dense layer of hydroxyls creates an ideal surface for ALD.

High reactivity enables process engineers to use precursors that normally would not react with water or ozone. This reactivity also results in active removal of carbon.

The Peroxidizer delivers at a 4:1 water:H2O2 molar ratio, the most concentrated H2O2 gas delivery available and a 10x improvement over the previous generation from a 30% liquid source. Previous ALD studies frequently assumed that H2O2 was delivered at 4:1 ratio when in fact H2O2 delivery was much lower at 100:1. For the first time, ALD processes can use H2O2 with minimal interference from water vapor.

High concentration H2O2 gas enables lower temperature processing, new precursor choices, better removal of residual carbon from the surface, and better initiation on the surface of the wafer, stated Spiegelman. All these advantages make hydrogen peroxide gas a very exciting new molecule for the ALD community.

Annealing

High concentration H2O2 gas is well-suited for annealing applications where high speed deposition and low operating temperatures are required. H2O2 gas is a good oxidant that can penetrate deep structures. More aggressive oxidants like plasma and ozone can damage surface materials and sensitive structures. H2O2 gas reduces the required thermal budget, protecting against high heat exposure that causes film shrinkage.

The ability to replace water vapor and steam with hydrogen peroxide gas reduces time and operating temperature. This will enable next generation gap fill technology, a critical milestone for success with 3D structures, said Spiegelman.

Surface Preparation and Cleaning

Hydrogen peroxide gas enables dry in situ cleaning and surface preparation, eliminating the need for liquid baths and the contamination risk associated with transfers from bath to chamber. Less chemical is required for this dry process and no drying step is needed.

Hydrogen peroxide gas removes carbon-based contaminants on wafer surfaces while avoiding damage to device structures that can be caused by ozone or liquids. Organic hydrocarbons are oxidized, enabling their removal.

The Peroxidizer gives fabs a great alternative to their current cleaning technologies, said Spiegelman. The ability to deliver hydrogen peroxide as a gas instead of a liquid speeds the move away from wet processing to more effective dry cleaning, which will be needed to support Moores Law.

Versatility

With the Peroxidizer, process engineers can precisely control their processes. The Peroxidizer delivers hydrogen peroxide gas in concentrations from 12,500 to greater than 50,000 parts per million depending on flow rate. This correlates to 1.25 to 5+% gas by volume delivery to process. The Peroxidizer supports carrier gas flows from 5 to 20 SLM in vacuum to atmospheric pressure. The Peroxidizer is available immediately. For details and to order, contact RASIRC.

Original Source: http://www.newswire.com/press-release/new-rasirc-peroxidizer-delivers-high-concentration-hydrogen

Imec presents successors to FinFET for 7nm and beyond at VLSI Technology Symposium 2015

Leuven (Belgium)– June 17, 2015 – At this week’s VLSI 2015 Symposium in Kyoto (Japan), imec reported new results on nanowire FETs and quantum-well FinFETs towards post-FinFET multi-gate device solutions. 

The Technology roadmap as presented recently by Imec at the EWMOVPE workshop in Lund, Sweden.

As the major portion of the industry adopts FinFETs as the workhorse transistor for 16nm and 14nm, researchers worldwide are looking into the limits of FinFETs and potential device solutions for the 7nm node and beyond. Two approaches, namely Gate-All-Around Nanowire (GAA NW) FETs, which offer significantly better short-channel electrostatics, and quantum-well FinFETs (with SiGe, Ge, or III-V channels), which achieve high carrier mobility, are promising options. 

For the first time, imec demonstrated the integration of these novel device architectures with state-of-the-art technology modules like Replacement-Metal-Gate High-k (RMG-HK) and Self (Spacer)-Aligned Double-Patterned (SADP) dense fin structures. By building upon today’s advanced FinFET technologies, the work shows how post-FinFET devices can emerge, highlighting both new opportunities as well as complexities to overcome. 

Imec and its technology research partners demonstrated SiGe-channel devices with RMG-HK integration. Besides SiGe FinFET, a unique GAA SiGe nanowire channel formation during the gate replacement process has been demonstrated. The novel CMOS-compatible process converts fin channels to nanowires by sacrificial Si removal during the transistor gate formation. The process may even enable future heterogeneous co-integration of fins and nanowires, as well as Si and SiGe channels. The work also demonstrates that such devices and their unique processing can lead to a drastic 2x or more improvement in reliability (NBTI) with respect to Si FinFETs. 

Moreover, imec demonstrated Si GAA-NW FETs based on SOI with RMG-HK. The work compares junction-based and junction-less approaches and the role of gate work function for multi-Vt implementations. New insights into the improved reliability (PBTI) with junction-less nanowire devices have been gained.

Extending the heterogeneous channel integration beyond Si and SiGe, imec demonstrated for the first time strained Ge QW FinFETs by a novel Si-fin replacement fin technique integrated with SADP process. Our results show that combining a disruptive approach like fin replacement with advanced modules like SADF-fin, RMG-HK, direct-contacts can enable superior QW FinFETs. The devices set the record for published strained Ge pMOS devices, outperforming by at least 40% in drive current at matched off-currents.

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GLOBALFOUNDRIES, INTEL, Micron, Panasonic, Samsung, SK hynix, Sony and TSMC.

Video Picosun - PICOPLATFORM™ cluster tools

Picosun represents the cutting-edge in everything ALD – from the world class equipment design to the leading process quality, highest level after sales service and the best customer care.

PICOSUN™ ALD product portfolio provides fully automated, SEMI compliant high throughput production solutions in batch and cluster mode to global industries, and the most versatile and flexible R&D systems to research organizations and pilot manufacturing. 

LAM Research is gearing up for the upcoming Atomic Layering Weeks in Portland!

LAM Research is obviously gearing up for the upcoming Atomic Layering Weeks in Portland!

Every Atom Matters at These Conferences

June 15, 2015 

as posted in the LAM Research Blog : http://blog.lamresearch.com/blog-home/Post/428/Every-Atom-Matters-at-These-Conferences

Experts in the atomic-scale processing community will soon assemble at the AVS ALD 2015 Conference and the ALE Workshop to share advances in fundamental understanding and discuss recent progress in thin film device applications. Atomic layer deposition (ALD) and atomic layer etching (ALE) can provide chipmakers with advanced capabilities and process control that enable next-generation device manufacturing. As a leading provider of atomic-scale deposition and etch capabilities, Lam Research is pleased to be a platinum sponsor of both these AVS-hosted events. We will also share some of our work, as highlighted below.




One of the most important conferences on ALD, the International Conference on Atomic Layer Deposition, will take place this year June 28-July 1 in Portland, Oregon. Lam’s Dr. Adrien LaVoie will give an invited talk on ALD in high-volume manufacturing. Addionally, there will be four oral presentations and four poster presentations featuring work by Lam.

Optimizing Plasma Environment in PEALD to Suppress Parasitics and Enable Production-Worthy Processing

F.L. Pasquale, C. Baldasseroni, E. Augustyniak, S. Swaminathan, P. Ni, K. Leeser, D.C. Smith, S. Varadarajan, A. LaVoie
Monday, June 29, 1:30 PM

(Invited) ALD for High Volume Manufacturing: Latest Trends, Developments, and Market Applications

A. LaVoie

Monday, June 29, 3:00 PM

Plasma Effects on Conformality for Atomic Layer Deposition of Silicon Nitride

K. Kelchner, S. Tang, G. Yuan, D. Hausmann, J. Henri, J. Sims
Monday, June 29, 5:15 PM

Computational Modelling of Atomic Layer Deposition of Silicon Carbide

E. Filatova, S. Elliott (Tyndall National Institute); D. Hausmann (Lam Research)
Monday, June 29, 5:30 poster session

Towards Atomic Layer Deposition of Carbon-Containing Silicon-Based Dielectrics

R.A. Ovanesyan, R.J. Gasvoda (Colorado School of Mines); D.M. Hausmann (Lam Research); S. Agarwal (Colorado School of Mines)
Tuesday, June 30, 3:15 PM

Atomic Layer Deposition of Titanium Nitride Thin Film Using Unsymmetrical Dimethyl Hydrazine

S.V. Thombare, I. Karim, S. Gopinath
Tuesday, June 30, 5:30 PM poster session

Precursor and Process Effects on Conformality for Atomic Layer Deposition of Silicon Nitride Using Nitrogen (N2) Plasma

S. Tang, K. Kelchner, G. Yuan, D. Hausmann, J. Henri, J. Sims
Tuesday, June 30, 5:30 PM poster session

Wafer-Scale Selective Deposition of Nanometer Metal Oxide Features Via Selective Saturated Vapor Infiltration into Pre-Patterned Poly(Methyl Methacrylate) Template

E. Dandley (North Carolina State University); A. Yoon, Z. Zhu, L. Sheet (Lam Research); G. Parsons (North Carolina State University)
Wednesday, July 1, 8:15 AM

Plasma Enhanced Atomic Layer Deposition of SiO2 in Sub-Saturation Regime

P. Kumar, H. Kang, J. Qian, A. LaVoie
Wednesday, July 1, 8:30 AM






In recognition of ALE’s growing importance, an Atomic Layer Etching Workshop dedicated to this topic will be held on July 1-2 in Portland, Oregon, following ALD 2015. Dr. Eric Hudson will give an invited talk on ALE for self-aligned contacts. We will also share our work on the science and applications of atomic layer etching during the poster session.

Selective Removal of Native SiO2 Using XeF2

A. Hinckley, P. Mancheno (Univ. of Arizona); S. Lai (Lam Research); A. Muscat (Univ. of Arizona)
Wednesday, July 1, 6:00 PM poster session

Overview of Atomic Layer Etching

K.J. Kanarik, T. Lill, E.A. Hudson, S. Sriraman, S. Tan, J. Marks, V. Vahedi, R.A. Gottscho
Wednesday, July 1, 6:00 PM poster session

(Invited) Fluorocarbon-Based Atomic Layer Etching of Silicon Dioxide for Self-Aligned Contact

E.A. Hudson, R. Bhowmick, R. Bise, H. Shin, G. Delgadino, B. Jariwala, D. Lambert, S.J. Cho, S. Deshmukh
Thursday, July 2, 2:20 PM

SoLayTec garners repeat ALD orders from China for PERC production

Atomic layer deposition (ALD) equipment specialist SoLayTec, a subsidiary of Amtech Systems has secured orders from two China-based PV manufacturers. Image: SoLayTec.

Atomic layer deposition (ALD) equipment specialist SoLayTec, a subsidiary of Amtech Systems has secured orders from two China-based PV manufacturers.

Critically, SoLayTec has received its first follow-on order for its modular InPassion system from an existing customer, since first evaluating ALD technology in 2011. The customer entered volume production using the technology in 2014, resulting in a repeat order for production later in 2015. The company said that tool delivery was planned for June.

The second order is for an R&D evaluation with a new client with the expectation of taking the technology from lab to fab in the future. SoLayTec said that in principle the new customer would commence R&D activities with one module, which can handle at least 600wph. However, after pilot testing and validation, the tool can be upgraded to mass production by adding the other modules to reach a maximum throughput of 3,600wph.

Roger Görtzen, co-founder of SoLayTec and manager marketing and sales said: “Since 2011 SoLayTec is working very closely with this Tier one customer and SoLayTec is proud that they have accepted our InPassion ALD in full production last year. They started PERC research with our InPassion LAB tool in 2011 and moved towards mass production in 2014, starting with our InPassion ALD system with three modules (1800wph). This was accepted within three months after which they purchased another three modules upgrading the tool to 3600wph and at the same time showing the advantage of our modular tool set-up. So now SoLayTec has reached its next milestone by repeat orders. This clearly shows the equipment readiness for mass production for the PV market.”

ALD competed with PECVD and APCVD deposition techniques to provide tightly specified thicknesses of Al2O3 for surface passivation of both the front and real cell in a PERC configuration. Tighter deposition control can produce higher efficiency cells.

Financial details were not disclosed.

KAIST on BCP lithography for flexible nanoelectronics

Here is an impressive overview from Prof. Keon Jae Lee and co-workers at KAIST on directed block copolymer (BCP) self-assembly for applications for electronic and energy devices.

The semiconductor industry depend on conventional lithography (Optical Lithography) based on a light source, photoresist materials and photo masks. A number of alternative patterning techniques have been developed  to improve the pattern resolution. However, the limitation has been that of light diffraction which is wave length dependent and reducing the wave length has become a major cost issue for the new technologies of the light source. Another major drawback is that the leading technology is wafer based and there is a drive to integrate future device on flexible substrates and reduce the overall cost of lithography and device production by either large area panels (e.g. displays, solar cells) or roll to roll flexible foil production technologies.

The next-generation lithographic techniques on the nanometer scale are:

• electron-beam lithography (EBL) - low throughput
• nanoimprinting lithography (NIL) - requires a costly master template
• directed block copolymer (BCP) self-assembly - relies spontaneous microscopic phase separation of covalently linked polymer blocks

Performance Enhancement of Electronic and Energy Devices via Block Copolymer Self-Assembly

Hyeon  Gyun Yoo, Myunghwan Byun, Chang Kyu Jeong, and Keon Jae Lee 

Adv. Mater. 2015,
DOI: 10.1002/adma.201501592

The use of self-assembled block copolymers (BCPs) for the fabrication of electronic and energy devices has received a tremendous amount of attention as a non-traditional approach to patterning integrated circuit elements at nanometer dimensions and densities inaccessible to traditional lithography techniques. The exquisite control over the dimensional features of the self-assembled nanostructures (i.e., shape, size, and periodicity) is one of the most attractive properties of BCP self-assembly. Harmonic spatial arrangement of the self-assembled nanoelements at desired positions on the chip may offer a new strategy for the fabrication of electronic and energy devices. Several recent reports show the great promise in using BCP self-assembly for practical applications of electronic and energy devices, leading to substantial enhancements of the device performance. Recent progress is summarized here, with regard to the performance enhancements of non-volatile memory, electrical sensor, and energy devices enabled by directed BCP self-assembly.

JUST RELEASED - TEHCHET's 2015 Materials Market and Business Trends, Supply Chain Reports

IoT is growing those materials considered trailing edge. 3D devices is driving growth on the front end. Enabling packaging technologies paving the way for mid-high end device connectivity. Gases, Targets, CMP Consumables, WLP Polymers and Silicon Wafers Reports just released.

SoLayTec InPassion ALD for Al2O3 2015 Promotion Video

The In Passion Spatial ALD tool from SoLayTec is just one of the coolest ALD tools on the martket. These guys also produces the best promotion videos. Check out the latest one! What a concept - swapping chambers in full production.

SoLayTec is a spin-off company of the Dutch research organisation TNO and established in 2010. SoLayTec is part of the Amtech Group (Nasdaq ASYS). The company develops, delivers and services machines for atomic layer deposition (ALD) on solar cells worldwide. The SoLayTec ALD machines are designed for mass production in the solar market. In the field of solar cell ALD equipment, SoLayTec has a leading 

University of Cincinnati and Industry Partners Develop Low-Cost Tunable Window Tintings

As reported by University of Cincinnati - Technology developed by the University of Cincinnati and industry partners can do something that neither blinds nor existing smart windows can do. This patent-pending research, supported by the National Science Foundation, will lead to low-cost window tintings which dynamically adapt for brightness, color temperatures and opacity (to provide for privacy while allowing light in). 

Top view and side-view diagrams of the device construction.

Technology developed by the University of Cincinnati and industry partners can do something that neither blinds nor existing smart windows can do. This patent-pending research, supported by the National Science Foundation, will lead to low-cost window tintings which dynamically adapt for brightness, color temperatures and opacity (to provide for privacy while allowing light in). 

Full story here : http://www.uc.edu/news/NR.aspx?id=21741

Hooking together European research in Atomic Layer Deposition

Now the stand-alone HERALD Page is up (http://www.european-ald.net/). HERALD (COST action MP1402) aims to structure and integrate European research activity in atomic layer deposition (ALD), bringing together existing groups, promoting young scientists and reaching out to industry and the public. ALD is a unique technique for growing ultra-thin films that is enabling new developments in high-tech manufacturing sectors such as electronics, energy and coatings.

With interest growing worldwide, the time is right to coordinate European activity in this field, which until now has been fragmented, despite the presence of world-leading research groups and companies. The scientific collaborations in HERALD will cover new processes (precursor chemicals and equipment), fundamental understanding (metrology and modeling), innovative materials (nanoscale interfaces, 2D materials) and applications (semiconductor devices, photovoltaics, energy storage, sensors, protective coatings for organic elements and fibers). Networking activity will consist of bursaries for lab visits, topical workshops, conference support,  joint publications and marketing. It is intended to establish a framework for this activity in Europe that will outlast the duration of HERALD and ensure Europe's leading position into the future.

Upcoming HERALD events in 2015

Co-organised workshop (WG4)	Novel High k Application Workshop	9-10 March 2015	Dresden, DE
WG1 workshop	Workshop on ALD fundamentals and reaction mechanisms	8-9 Jun 2015	Eindhoven, NL
Training school (including WG5)	Atomic Layer Deposition: method and applications	6-7 Jul 2015	Brescia, IT
Co-organised conference (WG2)	20th Biannual European Conference on Chemical Vapour Deposition (EUROCVD20)	13-17 Jul 2015	Sempach, CH
WG3 workshop	Workshop on ALD applications for battery materials	15-16 Sep 2015	Gent, BE
Co-organised conference	Baltic ALD conference	28-29 Sep 2015	Tartu, ES
Action meeting, all WGs	Annual HERALD Day	30 Sep 2015	Tartu, ES
Co-organised workshop (WG4) and training school	ALD Symposium at SEMICON Europa	6-8 Oct 2015	Dresden, DE
Co-organised workshop (WG1)	Simulation of chemistry-driven growth phenomena for metastable materials	8-11 Nov 2015	Marburg, DE

Update: Technical program ALD 2015 in Moscow Russia, 21-23 Septmber 2015

ALD 2015 in Moscow Russia, 21-23 Septmber 2015, has quite an impressive line up of invited speakers

Call for abstracts

The deadline for abstract submission is July 30, 2015.

Please prepare your abstract according to the template. This document contains all styles necessary for abstract preparation. Name the file as "YourSurname.doc" and send by email to Organizing Committee. Please indicate by email what kind of presentation you prefer: oral or poster.

Dear Russian participants, we have to acknowledge that the expert conclusion on the possibility of publishing of your abstract in press is required since your abstract is planned to be included in the Abstract Book. Please, send its scanned version by email to the Organizing Committee along with Your abstract. Please note, that we cannot guarantee the publication of your work in case we do not get this conclusion.

Technical program

Click to download the Technical Program. Please note, that this is the first version of Technical Program and some changes are possible.

Invited speakers

• The origins of ML-ALD in the USSR-Russia: from V. B. Aleskovskiiיs “framework hypothesis” on the path to precise synthesis of solids, A.A. Malygin, St. Petersburg Technological University, Russia.
• Atomic Layer Etching Using Thermal Reactions: ALD in Reverse, Steven M. George, University of Colorado at Boulder, USA.
• How conformal is conformal? Exploring the limits of ALD film conformality with VTT’s lateral microscopic test structure, Riikka Puurunen, VTT, Finland.
• The nature of electron and hole traps responsible for localization and charge transport in high-k dielectrics, V.A. Gritsenko, Rzhanov Institute of Semiconductor Physics SB RAS.
• Atomic layer deposition of Ge2Sb2Te5 thin films for phase change memory, Cheol Seong Hwang, Seoul National University, Korea.
• Atomic layer deposition for rare earth oxides and thermoelectric thin films, Giovanna Scarel, James Medison University, USA.
• Plasma-assisted ALD: status and prospects, Erwin Von Kessel, Eindhoven University of Technology, Netherlands.
• In-Situ Studies of ALD on 2D Materials, Robert M. Wallace, University of Texas at Dallas, USA.
• ALD nanolaminates for solar cell application, Ingo Dirnstorfer, Namlab, Germany.
• Atomic layer deposition of transition metal dichalcogenides, two-dimensional semiconductors, Annelies Delabie, IMEC, Belgium.
• Ideal precursor for ALD: Dreams and Reality, I.K. Igumenov, A.V. Nikolaev Institute of Inorganic Chemistry, Russia.
• Ruthenium and Iridium thin deposition: summary and issues, V.Yu. Vasiliev, Novosibirsk state technical university and SibIS LLC, Russia.
• ALD of oxides for nanoelectronic devices: status and perspectives, Sabina Spiga, CNR-IMM-MDM, Italy.
• Gregory N. Parsons, North Carolina State University, USA.
• Gold Metal Films by Radical-Enhanced Atomic Layer Deposition, Sean Barry, Carleton University, Canada.
• The synthesis of two dimensional nanomaterials based on Atomic Layer Deposition, Hyungjun Kim, Yonsei University, Korea.
• Evgeni Gornev, SRIME, Russia. 

KAUST demonstrate ALD Passivation to stop Degradation of Nanorod Anodes in Lithium Ion Batteries

Researchers at King Abdullah University of Science and Technology (KAUST) demonstrate an effective strategy to overcome the degradation of MoO3 nanorod anodes in lithium (Li) ion batteries at high-rate cycling, which is achieved by conformal nanoscale surface passivation of the MoO3 nanorods by HfO2 using atomic layer deposition (ALD). The nanoscale HfO₂ layer was deposited on the prepared electrodes at 180 °C using atomic layer deposition system (Ultratech/Cambridge Nanotech Savannah).

 

 

Surface Passivation of MoO3 Nanorods by Atomic Layer Deposition toward High Rate Durable Li Ion Battery Anodes

B. Ahmed, Muhammad Shahid, D. H. Nagaraju , D. H. Anjum , Mohamed N. Hedhili, and H. N. Alshareef
Materials Science and Engineering, King Abdullah University of Science and Technology (KAUST), Thuwal, 23955−6900, Saudi Arabia
ACS Appl. Mater. Interfaces, Article ASAP
DOI: 10.1021/acsami.5b03395
Publication Date (Web): June 3, 2015

 

We demonstrate an effective strategy to overcome the degradation of MoO3 nanorod anodes in lithium (Li) ion batteries at high-rate cycling. This is achieved by conformal nanoscale surface passivation of the MoO3 nanorods by HfO2 using atomic layer deposition (ALD). At high current density such as 1500 mA/g, the specific capacity of HfO2-coated MoO3 electrodes is 68% higher than that of bare MoO3 electrodes after 50 charge/discharge cycles. After 50 charge/discharge cycles, HfO2-coated MoO3 electrodes exhibited specific capacity of 657 mAh/g; on the other hand, bare MoO3 showed only 460 mAh/g. Furthermore, we observed that HfO2-coated MoO3 electrodes tend to stabilize faster than bare MoO3 electrodes because nanoscale HfO2 layer prevents structural degradation of MoO3 nanorods. Additionally, the growth temperature of MoO3 nanorods and the effect of HfO2 layer thickness was studied and found to be important parameters for optimum battery performance. The growth temperature defines the microstructural features and HfO2 layer thickness defines the diffusion coefficient of Li-ions through the passivation layer to the active material. Furthermore, ex situ high resolution transmission electron microscopy, X-ray photoelectron spectroscopy, Raman spectroscopy, and X-ray diffraction were carried out to explain the capacity retention mechanism after HfO2 coating.

SEMICON West - Scaling Transistors: HVM Solutions Below 14nm; Getting to 5nm

Scaling Transistors: HVM Solutions Below 14nm; Getting to 5nm

Manufacturing at 14nm is a reality. Looking ahead, choices for materials and process modules have to be in their final stages in order for the industry to stay on track for introduction of the next node. At the same time, R&D efforts to get the industry to 5nm continue. This session covers how high-volume manufacturing (HVM) solutions are taking shape below 14nm – including the role that EDA tools will need to play – and summarizes R&D activities needed to get to 5nm.

Wednesday, July 15
2:00pm-4:30pm
Moscone North, Hall E, Room 133 
Session Sponsor:

 

Agenda

2:00pm-2:05pm Welcome and Session Overview

2:05pm-2:30pm An Steegen, Ph.D.
SVP, Process Technology
imec

2:30pm-2:55pm Christophe Maleville
SVP, DIgital Electronics BU
Soitec

2:55pm-3:20pm Raj Jammy, Ph.D.
Intermolecular

3:20am-3:45pm Harmeet Singh
Corporate Vice President
Lam Research

3:45pm-4:10pm Ofer Adan
Global Product and Technology Manager, Process Diagnostics and Control
Applied Materials

4:10pm-4:35pm Juan Rey
Sr. Director, Calibre Engineering
Mentor Graphics

Plasmonic nanostructures for color filtering and nano printing technologies

This is pretty cool technology coming out of Missouri University of Science and Technology and Sandia National Laboratories. Structural color filtering and printing technologies employing plasmonic nanostructures have recently been recognized as an important and beneficial complement to the traditional colorant-based pigmentation. In this demonstration a PVD stack of 100 nm silver / 45 nm SiO2 / 25 nm silver is used. The complete stack is deposited on a Kurt J. Lesker PVD tool and final protection by thin oxide. 

Check out Prof. Xiaodong Yang, at Department of Mechanical and Aerospace Engineering Missouri University of Science and Technology for more interesting nano structures like Photonic crystals and photonic crystal cavities

Structural color printing based on plasmonic metasurfaces of perfect light absorption (Open Access)

Fei Cheng, Jie Gao, Ting S. Luk & Xiaodong Yang

Scientific Reports 5, Article number: 11045 doi:10.1038/srep11045 

Published 05 June 2015

(a) Schematic view of four unit cells for triangular-lattice circular hole arrays fabricated on the silver-silica-silver three layer structure. (b) An example of SEM cross-section image of the metasurface structure with period (P) of 320 nm and hole radius (r) of 100 nm. (c–e) SEM images of three metasurfaces with different lattice geometrical parameters (c: P = 130 nm, r = 35 nm; d: P = 200 nm, r = 50 nm; e: P = 260 nm, r = 65 nm). Insets: Optical reflection microscopy images of the entire 20 × 20 μm2 circular hole arrays of triangular lattice. Scale bars: 500 nm.

Abstract

Subwavelength structural color filtering and printing technologies employing plasmonic nanostructures have recently been recognized as an important and beneficial complement to the traditional colorant-based pigmentation. However, the color saturation, brightness and incident angle tolerance of structural color printing need to be improved to meet the application requirement. Here we demonstrate a structural color printing method based on plasmonic metasurfaces of perfect light absorption to improve color performances such as saturation and brightness. Thin-layer perfect absorbers with periodic hole arrays are designed at visible frequencies and the absorption peaks are tuned by simply adjusting the hole size and periodicity. Near perfect light absorption with high quality factors are obtained to realize high-resolution, angle-insensitive plasmonic color printing with high color saturation and brightness. Moreover, the fabricated metasurfaces can be protected with a protective coating for ambient use without degrading performances. The demonstrated structural color printing platform offers great potential for applications ranging from security marking to information storage.

(a) The original athletics mark image adapted with permission from The Curators of the University of Missouri. (b) SEM image of the fabricated pattern containing six different triangular lattices and corresponding colors shown in panel e. (c) SEM image of the area outlined in panel f. (d) Optical microscopy image of a plasmonic reproduction of the original mark image shown in panel e, containing only yellow and green colors. (e) Optical microscopy image of the plasmonic print presenting another four distinct colors (symbol ‘&’: orange, character ‘S, T’: magenta, pickaxe shape: cyan and word ‘MISSOURI’: navy blue) besides two original colors shown in panel d. Scale bars: 10 μm (b, d and e); 2 μm (c).

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The success story of the European Semiconductor R&D Model!

I am pretty fed up with all these depressing statements and news that you can´t do leading edge semiconductor research in Europe and especially not in Germany or Sweden. Europe is failing and so on bla, bla, bla. That is why I was very happy to read about trouble elsewhere and I came to the conclusion that Europe is maybe the place to be in after all so that´s why I at the end tilted this blog - The success story of the European Semiconductor R&D Model! 

So here is what triggered me to write this:

"Rising costs and a consolidating industry are forcing companies to rethink where to place their dollars; Europe and Asia step up investments. " Says Mark Lapedus in a recent article in Semiconductor Engineering. 

He goes on stating how research and development is a sometimes forgotten but critical element in the semiconductor industry and paints a picture of how the R&D landscape is affected by all this and come with some interesting facts:

1) Asian and European R&D organizations are expanding their efforts while the United States is taking a step back. 

2) Sematech, a major R&D chip consortium in the U.S., is falling by the wayside, at least as a standalone organization.

According to Lapedus Sematech’s issues began showing up in March, when Intel confirmed it had exited from the R&D consortium followed by Samsung and TSMC. Leaving GlobalFoundries as one of the few remaining members in the organization.

As far as I know all these leading companies are Core members of Imec and have no plans of pulling out there. On the contrary they are steaming ahead scaling as fast as ever. 10 nm FinFET in the Pipeline, 7 and 5 nm programs and beyond are up and running at Imec.

Construction work at Imec, Leuven, June 2013.

I recently went to a MOVPE (same as MOCVD) Workshop in Lund Sweden (see picture below), and listenend to an interesting invited talk from Imec and there is a sold plan for III/V CMOS silicon 300 mm wafers. How solid is it you may ask - Imec is shuffling 300 mm integrated fort end test wafers through an Applied Materials MOCVD Centura advanced cluster tool since a while. According to Imec III/V channel material has been fabed on 300 mm. In addition, an interesting comment after the talk from Aixtron was "Intel and others are running III/V pre production".

The Imec Technology roadmap for CMOS scaling beyond 5 nm. Shown at the European Workshop on MOVPE 2015, in Lund, Sweden, in an invited talk, Bernardette Kunert, IMEC, Leuven, Belgium "Challenges for III/V in CMOS application".

Imec logic device roadmap - Device technology features. (Imec/ITF Korea 2015). Here you can see that at 5 nm there is an option for III/V channel material and possibly vertical Nanowire integration. Next time we will get updated from Imec will be at SEMICON West where An Steegen will give a presentation (http://www.semiconwest.org/node/13826)

Then lets´have a look on CEA/ Leti - also a European R&D organization. CEA/Leti together with ST Micro are steaming down a slightly different path than Imec focusing instead on SOI and FD-SOI technology and 3D stacked CMOS. Here a success has already been seen Globalfoundries Fab1 is putting up and running 20 nm FD-SOI technology. Samsung has signed a deal with ST Micro for the same - yet another european success story in Advanced CMOS scaling.

So to come to the point - when do you hear about scaled advance Logic device data on 300 mm coming out of CNSE or Sematech in New York the last years? How much has been invested there compared to the itty bitty 300 mm R&D Fabs in Europe? I may have missed certain findings but I am sure there is not much out there from Albany. OK they have a different task maybe, more focus on production and so on but at the end of the day much of the cool stuff still comes out of European R&D Pilot fabs.

Why is it so? Here are my thoughts and I would be interested in yours so please do not hesitate to use the comment field or drop me a private e-mail (jonas.sundqvist@baldengineering.com)

1) The management in Europe are Researchers and Innovators themselves - look at Imec, all the top level management, including the CEO Luc Van den Hove, are University Professors. They are not just holding the title here, they are leading research and students. I once took part in a series of workshops between Fraunhofer, TU Dresden and Imec top level managment and when it came to schedule the next meeting we had to adjust time in accordance to upcoming student exams in  Germany and Belgium - Would this happen in The US at that level?

Regarding the top management, I assume you have a similar situation at CEA/Leti and not to mention Fraunhofer - you can´t be taken serious in Fraunhofer unless your title starts with Herr Prof. Dr. Dr. In america they are all called Bill or George! Anything but Sue!

2) The track record. Imec and CEA/Leti has a long track record at their current locations and has not been forced to move - look at Sematech they had to move from warm Texas to Up State New York. People must have died the first weeks of winter out of frost bite. You just can´t move top notch researcher - not even in the US. 

3) Cross national Collaboration - in Europe all Universities are forced to collaborate with each other to become funded by the EU and in many cases also by the national funding organizations and it does´t matter if you fiddle around with coupons or shuffle 300 mm wafers - the same rules and incentives for everybody. In The US I have a sense that only the 4/6 inch wafer based National Labs and University Cleanrooms have to do this and that they are then financed partly by DARPA and Dr. Polla at IARPA - so the cool stuff is done on small wafers and then the industry steps in and scale it up. Please do correct me if I have the wrong picture here.

So a great success in European Semiconductor R&D that ends when it is time for production - then the Value Chain is sort of half broken - who cares we get to do the cool stuff and the Americans and Asians to shuffle the wafers in Mega Fabs and each wafer will travel at high speed and make multiple passes through an ASML super advanced Lithography tool.

ASML Lithography tool Installed at Imec 300 mm line in Leuven, Belgium (www.imec.be)

Simulation of a Multihole outlet Savannah ALD reactor

For those of you interested in ALD reactor simulations and especially the classic cross flow design you should definitely check out this publication. University of Wisconsin-Milwaukee, University of Alaska Anchorage and Macquarie University, Sydney.

Investigating atomic layer deposition characteristics in multi-outlet viscous flow reactors through reactor scale simulations

Mohammad Reza Shaeri,Tien-Chien Jen, Chris Yingchun Yuan, Masud Behnia

International Journal of Heat and Mass Transfer, Volume 89, October 2015, Pages 468–481

Available online 6 June 2015

The Atomic Layer Deposition system at the Laboratory for Sustainable and Nano-Manufacturing in Milwaukee was required in October 2009 from Cambridge Nanotech Inc. (Today Ultratech / Cambrideg Nanotech). The Model is a Savannah S100 with capabilities for 100 mm wafers up to 10 wafer batch processing in a single deposition (https://pantherfile.uwm.edu/cyuan/Facilities.html). Either this is actually a picture from 2009 when the tool was new or these guys take really good care of their equipment as indicated that the protective shipping foil is still on.

Abstract

In order to minimize the operational time of atomic layer deposition (ALD) process, flow transports and film depositions are investigated in multi-outlet viscous flow reactors through reactor scale simulations. The simulation process is performed on depositions of Al2O3 films using trimethylaluminum and ozone as the precursors, and inert argon as the purge gas. The chemistry mechanism used includes both gas-phase and surface reactions. Simulations are performed at a fixed operating pressure of 10 Torr (1330 Pa) and at two substrate temperatures of 250 °C and 300 °C, respectively. Flows inside the reactors are following the continuum approach; as a result, the Navier–Stokes, energy and species transport equations can be used to simulate transient, laminar and multi-component reacting flows. Based on the chemistry mechanism adopted in this study, the amount of oxygen atoms produced from the ozone decomposition is found to be the major reason for discrepancies in oxidation times and deposition rates at different ALD processes. A reactor with fewer outlets minimizes the ALD operational times by reducing both oxidation time and second purge time. In addition, higher deposition rates at a shorter time are obtained by using a reactor with fewer outlets. However, assigning a long enough time for the ozone exposure results in independency of ALD characteristics from the number of outlets such that the growth rates of around 3.78 angstrom/cycle and 4.52 angstrom/cycle are obtained for the substrate temperatures of and , respectively.

At Lund Nano Lab in Sweden we also operate a Savannah from about the same time and it is one of the more popular tools judging by the frequent user bookings. Since Ultratech came in the picture some things have happened. Today you get a slim white design Generation 2 and the delivery time in Europe can be as fast as 8 weeks which is pretty fast if you ask me. Check out the new product page at Cambridge Nanotech here.

The Savannah is available in three configurations: S100, S200, and S300 and is capable of holding substrates of different sizes (up to 300mm for the S300). 

Samsung and SNU identifies the next Super High-k

Here is another publication from Samsung on high-k screening in collaboration with Academia. This time in collaboration with researchers from the home base at Seoul National University. This is somehow a new behavior of Samsung who actually withdrew talks in front of ALD 2012 in Dresden on anything realting to high-k and DRAM development and I have not seen that much publishing from Samsung since then on these topics. Calculated results do usually not tend to interest me but this one is very, very interesting and I think it will take me some time to go there it - fully understand I will not.

"Except for c-BeO, we could not find any outstanding high-κ dielectrics with eitherEg or κ larger than those of the HfO2 thin films currently used in CPU or DRAM (Eg~6.0 eV and κ~20–25; see t-HfO2)"

Cubic BeO will probably be a hot ALD topic for the rest of 2015 and I do wonder if Prof. Wang will mention BeO in Portland at the AVS ALD 2015 in Portland when he gives his invited talk: 

Cheol Seong Hwang, Seoul National University

“Capacitor Dielectric and Electrodes for DRAM with sub-20 nm Design Rule”

Check out the paper - it is Open Access - thank you Samsung!

Novel high-κ dielectrics for next-generation electronic devices screened by automated ab initio calculations (Open Access)

Kanghoon Yim, Youn Yong, Joohee Lee, Kyuhyun Lee, Ho-Hyun Nahm, Jiho Yoo, Chanhee Lee, Cheol Seong Hwang and Seungwu Han

NPG Asia Materials (2015) 7, e190; doi:10.1038/am.2015.57
Published online 12 June 2015

The experimental band gap and dielectric constant for well-known oxides. The property region ideal for dielectrics is also shown.

Abstract:

As the scale of transistors and capacitors in electronics is reduced to less than a few nanometers, leakage currents pose a serious problem to the device’s reliability. To overcome this dilemma, high-κ materials that exhibit a larger permittivity and band gap are introduced as gate dielectrics to enhance both the capacitance and block leakage simultaneously. Currently, HfO2 is widely used as a high-κ dielectric; however, a higher-κ material remains desired for further enhancement. To find new high-κ materials, we conduct a high-throughput ab initiocalculation for band gap and permittivity. The accurate and efficient calculation is enabled by newly developed automation codes that fully automate a series of delicate methods in a highly optimized manner. We can, thus, calculate >1800 structures of binary and ternary oxides from the Inorganic Crystal Structure Database and obtain a total property map. We confirm that the inverse correlation relationship between the band gap and permittivity is roughly valid for most oxides. However, new candidate materials exhibit interesting properties, such as large permittivity, despite their large band gaps. Analyzing these materials, we discuss the origin of large κ values and suggest design rules to find new high-κ materials that have not yet been discovered.

Eg vs κ plot for computed structures for 1158 oxides. Each point is color coded according to the figure of merit (Eg·κ). The candidate oxides that have not yet been tested are indicated by the chemical formula. The rough boundary of material properties that are adequate for each device type is marked by dashed lines. CPU, central processing unit.

Worth to mention also in this context is that Han Jin Lim from Samsung Semiconductor R&D Center will give a tutorial at the AVS ALD2015 conference at the end of June in Portland.

Han Jin Lim, Samsung Electronics, “ALD Technologies and Applications in Semiconductor Device Fabrication”

Abstract:

As semiconductor devices of both memory and logic have been smaller than 20nm feature size and beyond, it is most important to acquire the conformal high-quality thin films that effect on the electrical performance enhancement in the three dimensional patterned scheme. ALD technology has been required in such critical steps as transistor and capacitor and also increased its applications including DPT (double patterning technology).

This talk consists of two parts. The first part covers the ALD in general. Those introduce the general ALD technologies including processes, precursors, reactants and equipment. The second part deals with its applications in semiconductor device fabrication. Major applications include oxide for transistor gate and DPT pattrening, nitide for transistor spacer, high-k dielectrics for transistor as well as capacitor, and metal electrode.

Samsung, NaMLab and KU Leuven present novel DRAM capacitor stack

There was a long time since I came across a publication on materials screening for the DRAM capacitor stack. That is why it is especially interesting to read of the joint work by NaMLab in Dresden , K.U. Leuven and Samsung. The team was able to enhance the properties of the high-k stack by replacing the Al2O3 interlayer with SrO to increase the overall k-value of the capacitor dielectric without degrading the barrier and leakage properties of the dielectric stack.

Introduction: For many years, the dynamic random access memory (DRAM) was the scaling driver in semiconductor industry. Continuous downscaling of the cell dimension led to the introduction of high-k materials in a three-dimensional cylindrical capacitor geometry with metal electrodes. Currently, the most common DRAM capacitor consists of a ZrO2/Al2O3/ZrO2 (ZAZ) stack. Intensive research is done on strontium titanate (STO) and Al doped TiO2 based capacitors, but here, the thickness scaling of the dielectric is difficult to reach due to the low band gap value of the TiO2 based dielectrics. Accordingly, additional research is necessary to scale the current ZrO2 based material stack.

Ultra-thin ZrO2/SrO/ZrO2 insulating stacks for future dynamic random access memory capacitor applications

Steve Knebel, Milan Pešić, Kyuho Cho, Jaewan Chang, Hanjin Lim, Nadiia Kolomiiets, Valeri V. Afanas'ev, Uwe Muehle, Uwe Schroeder and Thomas Mikolajick

J. Appl. Phys. 117, 224102 (2015); http://dx.doi.org/10.1063/1.4922349

(a) TEM micrograph of a ZAZ MIM film stack. The stack thickness is 10 nm. A distinct Al2O3 layer is visible in the center of the ZrO2 layer. ZrO2 grains stop growing at the Al2O3 interlayer. (b) TEM micrograph of a ZSrZ MIM film stack. Stack thickness is 5 nm. No distinct SrO layer is visible and the ZrO2 crystals are growing through the whole ZrO2 layer. (c) EDX line scan of the ZAZ film: a small Al peak can be seen in the center of the ZrO2 layer. (Inset) Zoom of the EDX line scan showing the Al peak and the background signal, which proves the position of the Al2O3 layer.

Citation: J. Appl. Phys. 117, 224102 (2015); http://dx.doi.org/10.1063/1.4922349

Aiming for improvement of the ZrO2-based insulator properties as compared to the state-of-the-art ZrO2/Al2O3/ZrO2 stacks beyond 20 nm dynamic random access memory (DRAM) technology applications, ultra-thin (5 nm) ZrO2/SrO/ZrO2 stacks with TiN electrodes deposited by physical vapor deposition are addressed. By replacing the Al2O3 interlayer with SrO, the effective dielectricpermittivity of the stack can be increased as indicated by electrical analysis. At the same time, no degradation of the insulating properties of the SrO-containing stacks and minor changes in the reliability, compared to an Al2O3 interlayer, are found. These results are indicating the possibility of further reducing the effective oxide thickness of the ZrO2-based stacks to come close to 0.5 nm for future DRAM capacitors.