SK Hynix & SNU demonstrate 28nm RRAM cell with ultra thin ALD Ta/Ta2O5 stack

Here is a impressive report by SK Hynix & Prof. Hwang and co-workers SNU on a RRAM device with Ta/Ta2O5 stacked RS layers with ultra-thin Ta2O5 thicknesses (0.5–2.0 nm) deposited by ALD. Woah that´s thin  - like the same order of thickness like native oxide, which makes me wonder if teh extra couple of ALD cycles was needed --> I need to study the paper more carefully!

Thickness effect of ultra-thin Ta₂O₅ resistance switching layer in 28 nm-diameter memory cell 

C.S. Hwang et al

Scientific Reports 5, Article number: 15965 (2015)
doi:10.1038/srep15965

(a) Schematic diagram and (b) TEM image of the TiN/Ta₂O₅/Ta/TaN device. Ta₂O₅ (0.5 nm) device, and (d) Ta₂O₅ (1.5 nm) device. Insets show the linear I-V plot. Scanning transmission electron microscopy (STEM) high angle annular dark field (HAADF) images of (c) 0.5 nm-thick device and (d) 2.0nm-thick device. 

Resistance switching (RS) devices with ultra-thin Ta₂O₅ switching layer (0.5–2.0 nm) with a cell diameter of 28 nm were fabricated. The performance of the devices was tested by voltage-driven current—voltage (I-V) sweep and closed-loop pulse switching (CLPS) tests. A Ta layer was placed beneath the Ta₂O₅ switching layer to act as an oxygen vacancy reservoir. The device with the smallest Ta₂O₅ thickness (0.5 nm) showed normal switching properties with gradual change in resistance in I-V sweep or CLPS and high reliability. By contrast, other devices with higher Ta₂O₅ thickness (1.0–2.0 nm) showed abrupt switching with several abnormal behaviours, degraded resistance distribution, especially in high resistance state, and much lower reliability performance. A single conical or hour-glass shaped double conical conducting filament shape was conceived to explain these behavioural differences that depended on the Ta₂O₅ switching layer thickness. Loss of oxygen via lateral diffusion to the encapsulating Si₃N₄/SiO₂ layer was suggested as the main degradation mechanism for reliability, and a method to improve reliability was also proposed.

ALD employed in nanographene charge trapping memory with a large memory window

A leading research centre for grapehene devices is Beijing National Laboratory for Condensed Matter Physics and Institute of Physics, Chinese Academy of Science. They have recently published a paper on Nanographene charge trapping memory. Here they use a 15 nm thick Al2O3, deposited by ALD, to act as a tunnelling layer and blocking layer, respectively (see abstract below).

According to the website: The research groups led by Prof. ZHANG Guangyu is recently focusing on graphene nanostructure fabrications and the related electrical transport studies and has:

Schematic of the graphene edge lithography. The process includes selectively ALD of Al₂O₃/HfO₂ on graphene edges, dry etching of the unprotected graphene and KOH etching of the metal oxides.(Image by ZHANG Guangyu et al )

• reported a highly anisotropic dry-etching technique in graphene basal plane for the first time [Advanced Materials 22, 4014, (2010)]] http://onlinelibrary.wiley.com/doi/10.1002/adma.201000618/pdf
• combined this technique with artificial-defects engineering for well-controlled top-down cutting of graphene nanostructures with zigzag-edges and sub-10-nm feature sizes [Advanced Materials 23, 3061, (2011)]. http://onlinelibrary.wiley.com/doi/10.1002/adma.201100633/pdf
• studied Raman scattering of graphene nanoribbons with Hydrogen-terminated zigzag edges and found the electron-phonon coupling in these unique structures [Nano letters 11, 4083-4088 (2011)]. http://pubs.acs.org/doi/abs/10.1021/nl201387x

Nanographene charge trapping memory with a large memory window

Jianling Meng, Rong Yang, Jing Zhao, Congli He, Guole Wang, Dongxia Shi and Guangyu Zhang

2015 Nanotechnology 26 455704
http://dx.doi.org/10.1088/0957-4484/26/45/455704

 Left, AFM images of nanographen films showing a high density of nanographen islands. Right, the stack and structure of the nanographene charge tarpping memory cell (PhysOrg: http://phys.org/news/2015-11-nanographene-memory-miniaturize.html)

(Left) Atomic force microscope image of the nanographene film with a high density of nanographene islands, which provide more charge-trapping sites to increase store capacity. (Right) Structure of the nanographene-based charge trapping memory. Credit: Meng, et al. ©2015 IOP Publishing

Read more at: http://phys.org/news/2015-11-nanographene-memory-miniaturize.html#jCp

(Left) Atomic force microscope image of the nanographene film with a high density of nanographene islands, which provide more charge-trapping sites to increase store capacity. (Right) Structure of the nanographene-based charge trapping memory. Credit: Meng, et al. ©2015 IOP Publishing

Read more at: http://phys.org/news/2015-11-nanographene-memory-miniaturize.html#jCp

Nanographene is a promising alternative to metal nanoparticles or semiconductor nanocrystals for charge trapping memory. In general, a high density of nanographene is required in order to achieve high charge trapping capacity. Here, we demonstrate a strategy of fabrication for a high density of nanographene for charge trapping memory with a large memory window. The fabrication includes two steps: (1) direct growth of continuous nanographene film; and (2) isolation of the as-grown film into high-density nanographene by plasma etching. Compared with directly grown isolated nanographene islands, abundant defects and edges are formed in nanographene under argon or oxygen plasma etching, i.e. more isolated nanographene islands are obtained, which provides more charge trapping sites. As-fabricated nanographene charge trapping memory shows outstanding memory properties with a memory window as wide as ~9 V at a relative low sweep voltage of ±8 V, program/erase speed of ~1 ms and robust endurance of >1000 cycles. The high-density nanographene charge trapping memory provides an outstanding alternative for downscaling technology beyond the current flash memory.

Nantero closes additional funding this summer for NRAM and adds ex TSMC Executive to the Board

I have noticed that Carbon Nanotube integration into semiconductor processing as an active device or sensor material has moved into a more mature phase lately. One example is the company Nantero who earlier this summer announced closing a $31.5 million Series E financing round from new and existing investors now adds Previous TSMC Executive Dr. Shang-Yi Chiang to its Advisory Board. 

According to the press relase Dr. Chiang was previously an Executive Vice President, Co-Chief Operating Officer and Senior Vice President of R&D at TSMC before announcing his retirement in October 2013. 

NRAM is based on forming a film of Carbon Nanotubes (CNT) that are deposited onto a standard silicon substrate that contains an underlying cell select device and array lines (typically transistors or diodes) that interface the NRAM switch. The NRAM acts as a resistive non-volatile random access memory NVRAM and can be placed in two or more resistive modes depending on the resistive state of the CNT fabric. When the CNTs are not in contact the resistance state of the fabric is high and represents a “0” state (see Figure below). When the CNTs are brought into contact, the resistance state of the fabric is low and represents a “1” state. (www.nantero.com)

“Nantero continues to attract the industry’s brightest and most innovative minds both internally and on an advisory basis,” said Greg Schmergel, Co-Founder, CEO and President of Nantero. “This added expertise will be instrumental in helping the company deliver a new generation of memory with the unique properties of DRAM-like speed, nonvolatility, and ultra-high-densities, for both standalone and embedded use.”

Additional information at the www.nantero.com  tells us: NRAM can enable a variety of exciting new features and products in both consumer and enterprise electronics. This new super-fast, ultra-high density memory can replace both DRAM and flash in a single chip, or enable new applications as a storage class memory, while also delivering the low power, high speed, reliability, and endurance needed to drive the next wave of electronics innovation.

• NRAM Advantages: Extremely Low Power, Super-Fast, High Density, High Endurance
• Limitless Scalability: Can Scale Below 5 nm to Enable Terabits of Memory in the Future
• Proven Technology: Successfully Used in Mass Production CMOS Fabs for Many Years
• Exciting Future Products: Virtual Screens, Next-Generation Enterprise Systems, Rolled-up Tablets, Instant-On Laptops, 3D Video Phones and other products needing huge amounts of fast memory

Here is also a video where the founders of Nantero tells us more about the revolutionary emerging memory technology they are commercializing - claiming scaling down to 5 nm and "unlimited storage capacity" for our future electronic gizmos.

 

Rice U. discovery may boost ReRAM memory technology

My favorite high-k metal oxide Ta2O5 is used again for a resistive RAM memory - this time with my least favorite material - Grrrraphene. Just can´t stand the hype I guess. Anyhow considering recent developments in cross bar Memory cell technology by Intel and Micron this could prove to be a future prospect.

A schematic shows the layered structure of tantalum oxide, multilayer graphene and platinum used for a new type of memory developed at Rice University. The memory device overcomes crosstalk problems that cause read errors in other devices. 

(Tour Group/Rice University)

PUBLIC RELEASE: 10-AUG-2015Rice U. discovery may boost memory technology

Rice University scientists make tantalum oxide practical for high-density devices

Scientists at Rice University have created a solid-state memory technology that allows for high-density storage with a minimum incidence of computer errors.

The memories are based on tantalum oxide, a common insulator in electronics. Applying voltage to a 250-nanometer-thick sandwich of graphene, tantalum, nanoporous tantalum oxide and platinum creates addressable bits where the layers meet. Control voltages that shift oxygen ions and vacancies switch the bits between ones and zeroes.

The discovery by the Rice lab of chemist James Tour could allow for crossbar array memories that store up to 162 gigabits, much higher than other oxide-based memory systems under investigation by scientists. (Eight bits equal one byte; a 162-gigabit unit would store about 20 gigabytes of information.)

Details appear online in the American Chemical Society journal Nano Letters. More details can be found here: http://www.eurekalert.org/pub_releases/2015-08/ru-rud081015.php

Intel and Micron Produce Breakthrough Memory Material & Arcitecture

According to the recent press release Intel and Micron are about to begin production on new class of non-volatile memory (NVM). TThe claim that this is "the first new memory category in more than 25 years."

Intel and Micron invented unique material compounds and a cross point architecture for a memory technology that is 10 times denser than conventional memory. (Photo: Business Wire)

• New 3D XPoint™ technology brings non-volatile memory speeds up to 1,000 times faster than NAND, the most popular non-volatile memory in the marketplace today.
• The companies invented unique material compounds and a cross point architecture for a memory technology that is 10 times denser than conventional memory².
• New technology makes new innovations possible in applications ranging from machine learning to real-time tracking of diseases and immersive 8K gaming.

New architecture... cross point architecture... think I heard that one before... an ants nest is also cross bar architecture...  hmmm not that interesting but more interesting so is what is this invented unique material and what processes are used for manufacturing? So we need to read the complete press release.

"The innovative, transistor-less cross point architecture creates a three-dimensional checkerboard where memory cells sit at the intersection of word lines and bit lines, allowing the cells to be addressed individually. As a result, data can be written and read in small sizes, leading to faster and more efficient read/write processes."

Transistor less - first clue! Continue reading... Cross Point Array Structure, Stackable, Selector, Fast Switching Cell, ... ??? What is the new unique material? How was it processed? How was it etched? Need to know... I´ll be back.

"Bulk switching characteristics"

BINGO! Peter Clarke at EE Times had it all in better detail - Intel, Micron Launch "Bulk-Switching" ReRAM.

"The prepared infographics suggest a resistive RAM with an in-built select diode allowing for a dense device structure. This would give it similarities to ReRAMs being developed by Crossbar Inc. (Santa Clara, Calif.) and other companies but would still leave a potential point of distinction — filamentary behavior." 

"Micron's Durcan said: "We are not the only companies thinking of bringing resistive elements to memory, but ours is unique." Intel's Cooke said the memory has the three attributes of: non-volatility, density and speed and that the memory scales in both the x-y plane and the z direction."

"Intel did confirm that 3D XPoint manufacturing is compatible with back-end-of-line (BEOL) processing, which opens up the possibility of deploying 3D Xpoint memory on top of a plane of logic and as an embedded non-volatile memory option."

In the commentary field Peter Clarke says: "I can only add that in the webcast press conference Rob Crooke and Mark Durcan emphasize repeatedly a switching electrical characteristic that occurred across the "bulk" of the memory cell material. They also talked about the cells being "completely different" to other non-volatile memories; "a fundamentally different switch" and a "fundamental discovery"

Check ou the Intel / Micron Webcast below

 

So still no information out there on the actual material stack and the deposition processes - obviously the whole ALD World is keeping their fingers crossed that this one like DRAM and modern CMOS can only be made by A-L-D!!!

Imec and Panasonic Demonstrate Breakthrough RRAM Cell

Imec and Panasonic Corp. announced today that they have fabricated a 40nm TaOx-based RRAM (resistive RAM) technology with precise filament positioning and high thermal stability. This breakthrough result paves the way to realizing 28nm embedded applications. The results were presented at this year’s VLSI technology symposium (Kyoto, June 15-19 2015).

Cross-sectional TEM of 40-nm Ir(TE)/Ta2O5/TaOx/TaN (BE) RRAM

One of today’s most promising concepts for scaled memory is RRAM which is based on the electronic (current-or voltage-induced) switching of a resistor element material between two metals. Imec and Panasonic developed a method that overcomes filament instability in RRAM, one of the critical parameters that impacts the memory state during read operation in resistive memory. 

The method was realized using a combination of process technologies such as low-damage etching, cell side oxidation, and an innovative encapsulated cell structure with an Ir/Ta2O5/TaOx/TaN stacked film structure featuring a filament at the cell center. With these methods, a 2-Mbit 40nm TaOx-based RRAM cell with precise filament positioning and high thermal stability was achieved. The memory array showed excellent reliability of 100k cycles and 10 years’ retention at 85°C. Additionally, the filament control and thermal stability technologies offer the potential to realize 28nm cell sizes.

Gosia Jurczak, director of imec’s research program on RRAM devices stated: “With these breakthrough results, we have proven the potential of this promising memory concept as embedded nonvolatile memory in 28nm technology node where conventional NOR Flash shows scaling limitations. This result is a confirmation of our leadership position in research and development on resistive memory.”

Air Products and SNU present low temperature ALD process for GST for PCRAM

Phase change random access memory (PCRAM) is one of the promising next-generation memory technologies because of its nonvolatile data retention property and rapid writing and reading speeds. Air Product and Seoul National University (SNU) now presents a stable and reliable  conformal ALDprocess for depositing the challenging GST material at low temperature. The Gb–Sb–Te films were deposited using a 200 mm shower head type ALD reactor from Quros (CN-1, Plus-200).

Combined Ligand Exchange and Substitution Reactions in Atomic Layer Deposition of Conformal Ge2Sb2Te5 Film for Phase Change Memory Application

Taeyong Eom, Taehong Gwon, Sijung Yoo, Byung Joon Choi, Moo-Sung Kim, Iain Buchanan, Sergei Ivanov, Manchao Xiao, and Cheol Seong Hwang

 

For phase change memories application, Ge–Sb–Te films were prepared by a stable and reliable atomic layer deposition (ALD) method. Ge(OC2H5)4, Sb(OC2H5)3, [(CH3)3Si]3Sb, and [(CH3)3Si]2Te were used to deposit various layers with compositions that can be described by combinations of GeTe2–Sb2Te layers including Ge2Sb2Te5 at a substrate temperature as low as 70 °C. A shift in composition of Sb–Te films from Sb2Te3 to Sb2Te composition was achieved by combining ligand exchange and substitution reaction between Sb in [(CH3)3Si]3Sb and Te in the Sb2Te3 layer. This surface-limited ALD process allowed highly conformal, smooth, and reproducible film growth over a contact hole structure, highlighting the feasibility of phase change memory applications.

Iridium Tantalum oxide based Resistive RAM from Panasonic

This is pretty cool for anybody who has been working with high-k for whatever application. More than 10 years ago there was focused research and development by many on high-k materials for logic, memory and capacitor applications and tantalum oxide was one of the contenders. Then two things happened Samsung went with a hafnium oxide based dielectric for their 90 nm DRAM (MIS stack) in 2004/2005 and Intel later introduced a hafnium oxide based HKMG technology for 45 nm logic in 2007. Since then it has been pretty boring looking at reverse engineering reports like the one below - always the same theme hafnium oxide and zirconium oxide, which due to the bloody lanthanide contraction is basically the same thing. That is why I was so happy to find this one a tantalum oxide based stack in a product for an emerging memory technology! Yay - Tantalum is back! I say back since STMicroelectronics had it all figured out already in 2003 in their Ta2O5 based 3D MIM capacitors and one of the earliest(?) patents on using ALD Ta2O5 in a MIM capacitor was granted in 1992(!) for VTT, Finland. Finally, not to forget the important of the metal electrode and metal in general the total awesomeness of using Iridium top electrodes in the case reported below! Just imagine how irritating this must be for Ruthenium.

The first High-k Ta2O5 MIM application patented 1992(!) and presented by VTT, Finland at SEMICON Europa in 1999. Slide as as given in the presentation "High-k fur Alle"

Introduction of High-k as given in the presentation "High-k fur Alle"

The resistive RAM (ReRAM) product of Panasonic has been investigated by TechInsights examines. The microcontroller (MN101LR series) is fabricated at Panasonic’s former Tonami fab using a 180nm CMOS process. As reported in EE Times:

"The Tonami fab is now operated as a joint venture with TowerJazz. Panasonic uses a binary transition metal oxide (tantalum oxide) as a variable resistance layer sandwiched between an upper electrode (iridium) and a lower electrode (tantalum based electrode). Panasonic’s ‘319 patent further describes the tantalum oxide as having two sub-layers[5], where a bottom tantalum oxide layer is formed by the reactive sputtering process of a Ta target to form an oxygen deficient layer (TaO1.43). This deposited tantalum oxide then undergoes an oxidation process to increase the oxygen content of its upper surface to form TaO2.45, which is close to the stoichiometric Ta2O5."

Panasonic ReRAM cell. (EETimes / TECHINSIGHTS)

This article also showcases details on the ADESTO CBRAM technolgy based on Silver and germanium sulfide, which are both unusual materials for a semiconductor fab. Possibly less of a problem for a fabless business model like ADESTO is using.

Ferroelectric HfO2 Based Materials and Devices: Current Status and Future Prospects

Ferroelectric Hafnium Oxide Based Materials and Devices: Assessment of Current Status and Future Prospects [OPEN ACCESS]

J. Müller, P. Polakowski, S. Mueller and T. Mikolajick

ECS J. Solid State Sci. Technol. 2015 volume 4, issue 5, N30-N35

Abstract

Bound to complex perovskite systems, ferroelectric random access memory (FRAM) suffers from limited CMOS-compatibility and faces severe scaling issues in today's and future technology nodes. Nevertheless, compared to its current-driven non-volatile memory contenders, the field-driven FRAM excels in terms of low voltage operation and power consumption and therewith has managed to claim embedded as well as stand-alone niche markets. However, in order to overcome this restricted field of application, a material innovation is needed. With the ability to engineer ferroelectricity in HfO₂, a high-k dielectric well established in memory and logic devices, a new material choice for improved manufacturability and scalability of future 1T and 1T-1C ferroelectric memories has emerged. This paper reviews the recent progress in this emerging field and critically assesses its current and future potential. Suitable memory concepts as well as new applications will be proposed accordingly. Moreover, an empirical description of the ferroelectric stabilization in HfO₂ will be given, from which additional dopants as well as alternative stabilization mechanism for this phenomenon can be derived. 

Comparison of the two major flavors of FRAM. 1T-1C: (a) Working principle illustrating the sensing margin / switched polarization P_sw derived from switched charge Q_sw and non-switched polarization P_nsw in the P-E-hysteresis. (b) DRAM-like architecture of FRAM adding a plateline to word- and bitline for bipolar ferroelectric switching. (c) TEM-micrograph and related P-E-hysteresis of a FE-HfO₂ based deep trench capacitor array proving the concept of 3D-integration capability. To illustrate the advantage of this area enhancement, the polarization density is calculated with respect to the lateral footprint of a comparable planar capacitor. 1T: (d) Illustration of the working principle by a graphical representation of the charge neutrality condition in a MFIS stack. Position 1 and 2 of the insulator-semiconductor loadline represents the transition from the ON-state to the OFF-state of the FeFET or vice versa. Accordingly, the gate voltage difference to turn on/off the FeFET can be approximated by 2 · V_C = 2 · E_c · d_FE, i.e. the memory window MW. (e) Disturb resilient AND architecture of the FeFET. (f) TEM-micrograph and related I_D-V_G-hysteresis of a FE-HfO₂ based 28 nm high-k metal gate transistors proving the concept of advanced 1T FRAM scalability

The recent success of smartphones and tablet computers has accelerated the R&D of fast and energy efficient non-volatile semiconductor memories, capable of replacing the conventional SRAM-DRAM-Flash memory hierarchy. These so called emerging memories usually leverage on the fact that certain materials possess the capacity for remembering their electric, magnetic or caloric history. For the extensively investigated ferroelectrics this ability to memorize manifests in atomic dipoles switchable in an external electric field. This unique property renders them the perfect electric switch for semiconductor memories. Consequently, only a few years after the realization of a working transistor the first ferroelectric memory concepts were proposed.

However, more than 60 years and several iterations later it is now clear that the success or failure of FRAM is mainly determined by the proper choice and engineering of the ferroelectric material. Perovskite ferroelectrics and related electrode systems underwent an extensive optimization process to meet the requirements of CMOS integration and are now considered the front up solution in FRAM manufacturing. Nevertheless, those perovskite systems require complex integration schemes and pose scaling limitations on 1T and 1T-1C memory cells that until now remain unsolved. This creates an unbalance between memory performance on the one side and manufacturing and R&D costs on the other side. This dilemma has ever since restricted FRAM to niche markets. 

With the recent demonstration of ferroelectricity in HfO₂-based systems (FE-HfO₂) a CMOS-compatible, highly scalable and manufacturable contender has emerged, that significantly expands the material choice for 1T and 1T-1C ferroelectric memory solutions as well as nanoscale ferroelectric devices. 

In this paper we will review and expand the current understanding of ferroelectricity in HfO₂, as well as discuss future prospects of ferroelectric HfO₂-based devices with respect to scaling, reliability and manufacturability. Opportunities and drawbacks of this disruptive development in ferroelectric material science will be critically examined. 

Continue reading in the full paper with Open Access here.

The City College of New York report on ultimate replacement for flash memory

As reported by The City College of New York:  The quest for the ultimate memory device for computing may have just taken an encouraging step forward. Researchers at The City College of New York led by chemist Stephen O’Brien have discovered new complex oxides that exhibit both magnetic and ferroelectric properties.

Combining both properties is very exciting scientifically for the coupling that can occur between them and for the devices that might ultimately be designed, in logic circuits or spintronics. Combining these two properties in a single material, however, has proved difficult until now.

Using an innovative inorganic synthesis technique, an interdisciplinary team led by Dr. O’Brien, associate professor of chemistry at The City College and a member of the CUNY Energy Institute at CCNY, prepared a mineral previously unknown in nature.

X‐ray and electron micrographs of new discovery together with model of the crystal structure (Picture from The City College of New York)

 

“It’s based on common elements: barium, titanium and manganese,” said Professor O’Brien, who’s also an established nanotechnology researcher.

Together with collaborators from Drexel University, Columbia, Brookhaven National Laboratory and China’s South University of Science and Technology, they solved the structure and observed both magnetic and ferroelectric behavior. What they uncovered was a new Hollandite crystal group designated “multiferroic.”

Their finding confirmed a prediction by scientists dating back nearly two decades of the ferroelectric nature of such inorganic substances.

On multiferroics and their possible application, Professor O’Brien said: “The Holy Grail in this field is the combination of both magnetic and ferroelectric elements at room temperature with a sufficient magnitude of interaction.”

This, he added, could lead to the “ultimate replacement for flash memory” or smaller memory devices with massive storage capacities.

This concurs with British physicist J.F. Scott, who is regarded as the "the father of integrated ferroelectrics." A researcher at Cambridge University, Dr. Scott believes that multiferroics might hold the future for the ultimate memory device.

The CCNY findings appear in the Nature online journal “Scientific Reports.”

About The City College of New York
Since 1847, The City College of New York has provided low-cost, high-quality education for New Yorkers in a wide variety of disciplines. More than 16,000 students pursue undergraduate and graduate degrees in: the College of Liberal Arts and Sciences; the Bernard and Anne Spitzer School of Architecture; the School of Education; the Grove School of Engineering; the Sophie Davis School of Biomedical Education, and the Colin Powell School for Civic and Global Leadership. U.S. News, Princeton Review and Forbes all rank City College among the best colleges and universities in the United States.

Ferroelectric deep trench capacitors based on Al:HfO2 for 3D nonvolatile memory applications

Ferroelectric deep trench capacitors based on Al:HfO2 for 3D nonvolatile memory applications

P. Polakowski, S. Riedel, W. Weinreich, M. Rudolf, J. Sundqvist, K. Seidel, J. Muller
Memory Workshop (IMW), 2014 IEEE 6th International
Date of Conference: 18-21 May 2014 Page(s): 1 - 4 Print ISBN: 978-1-4799-3594-9 Conference Location : Taipei, Taiwan DOI:10.1109/IMW.2014.6849367

 

Aiming for future nonvolatile memory applications the fabrication and electrical characterization of 3-dimensional trench capacitors based on ferroelectric HfO2 is reported. It will be shown that the ferroelectric properties of Al-doped HfO2 ultrathin films are preserved when integrated into 3-dimensional geometries. The Al:HfO2 thin films were deposited by ALD and electrical data were collected on trench capacitor arrays with a trench count up to 100k. Stable ferroelectric switching behavior was observed for all trench arrays fabricated and only minimal remanent polarization loss with increasing 3-dimensional area gain was observed. In addition these arrays were found to withstand 2∗109 endurance cycles at saturated hysteresis loops. With these report the 3D capability of ferroelectric HfO2 is confirmed and for the first time a feasible solution for the vertical integration of ferroelectric 1T/1C as well as 1T memories is presented.

 

Process flow scheme for the fabricated ferroelectric deep trench capacitors with high aspect ratio of 13:1 and the accordingly measured hysteresis loop of a 3D deep trench capacitor

IBM Zürich solves 40+ Year Old Challenge for Phase Change Materials

IBM Research reports in their News Blog on a breakthrough made in understanding and development of phase change memory cells by IBM Research in Zürich. "... for more than 40 years scientists have never measured the temperature dependence of crystal growth, due to the difficulties associated with the measurements which are taken at both a nanometer length and a nanosecond time scale. That was until earlier this year when, for the first time, IBM scientists in Zurich were able to take the measurements, which is today being reported in the peer-review journal Nature Communications."

 

 

The Binnig and Rohrer Nanotechnology Center is a unique facility for exploratory research. It is not a production or a pilot line with fixed processes or wafer sizes. Rather, it is a state-of-the-art exploratory cleanroom fabrication facility combined with "noise-free" labs shielded against external vibrations, acoustic noise, electromagnetic fields and temperature fluctuations.

 

Please see the abstract to the publication below and check out the blog more details including also an interview with the resreachers at The Binnig and Rohrer Nanotechnology Center in Zürich.

 

  

Abu Sebastian, Manuel Le Gallo und Daniel Krebs (Bild: IBM Research)

Crystal growth within a phase change memory cell

Abu Sebastian, Manuel Le Gallo, & Daniel Krebs,

Nature Communications Volume: 5, Article number: 4314 DOI:doi:10.1038/ncomms5314, 07 July 2014

In spite of the prominent role played by phase change materials in information technology, a detailed understanding of the central property of such materials, namely the phase change mechanism, is still lacking mostly because of difficulties associated with experimental measurements. Here, we measure the crystal growth velocity of a phase change material at both the nanometre length and the nanosecond timescale using phase-change memory cells. The material is studied in the technologically relevant melt-quenched phase and directly in the environment in which the phase change material is going to be used in the application. We present a consistent description of the temperature dependence of the crystal growth velocity in the glass and the super-cooled liquid up to the melting temperature.

 

 

The cross-sectional tunneling  electron microscopy (TEM) image of  a mushroom-type PCM cell  is shown in this photo.

 

WODIM 2014, the 18th Workshop on Dielectrics in Microelectronics, 9-11 June 2014 in Kinsale Cork Ireland.

Coming up next week - The 18th Workshop on Dielectrics in Microelectronics, which takes place from 9-11 June 2014 in Kinsale Co Cork Ireland. This event is hosted by Tyndall National Institute, UCC, Cork, and celebrates the 10th anniversary of the last time the workshop was held in Ireland.

 

 

The main objective of the workshop is to bring together specialists who work in the field of dielectrics and all aspects of their application in the field of micro and nanoelectronics. The forum is intended to provide an overview of the state of the art in this significant field, and to promote a relatively informal atmosphere for the discussion of the latest research results, where contributions from students are particularly encouraged. The workshop deals with a range of issues in the field of advanced and new dielectrics, such as: growth and deposition, modelling and simulation, physical and electrical properties, reliability and dielectric applications.

 

 

 Kinsale, Co Cork, Ireland, in one of the most beautiful coastal towns in Ireland.

 

One of the more interesting talks will be on Tuesday ;-)

09.40 “Fluorine Interface Treatments within the Gate Stack for Defect Passivation in 28nm HKMG Technology”

M. Drescher1, E. Erben2, M. Trentzsch2, C. Grass2, M. Hempel2, A. Naumann1, J. Sundqvist1, J. Schubert3, J. Szillinski3, A. Schäfer3, S. Mantl3

1 Fraunhofer IPMS-CNT, Königsbrückerstraße 180, 01099 Dresden, Germany, 2 Globalfoundries,
Wilschdorfer Landstraße 101, 01109 Dresden, Germany, 3 Forschungszentrum Jülich, Wilhelm-Johnen-Straße, 52428 Jülich, Germany

 

ITRS 2013 Emerging Research Devices on HfO2 based ferroelectric devices

ITRS 2013 Emerging Research Devices (ERD) Chapter has been updated on ferroelectric devices (page 13) referring to recent development using ferroelectric hafnium oxide.

From Page 12 : Notably, since 2011, ferroelectricity in a variety of doped and polycrystalline HfO2 has been reported. The HfO2 based FeFETs show promising write speed (down to a few ns), retention (projected to 10 years), and endurance (up to 1012), which all match the best performances of its perovskite counterparts (refer to ERD4a). [65,66,67,68,69], and HfO2-based FeFETs have been fabricated using standard high-k metal gate (HKMG) processes. The use of HfO2-based ferroelectrics significantly reduces the physical thickness of the gate stack, and in turn scales down the channel length to the current technology node [70]. Follow the typical HKMG process, SiO2 serves as the buffer layer between HfO2 and Si with a sub-nanometer thickness, yielding low depolarization field.

"In Ferroelectric FET memory, a ferroelectric dielectric forms the gate insulator of an FET. The main concern on FeFET memory lies in operation reliability. Operational reliability of the FeFET RAM is limited by the time dependant remnant polarization of the ferroelectric gate dielectric reflected in retention loss. Control of the ferroelectric-semiconductor interface is critical for FeFET properties. The scalability of FeFET memory beyond the 22nm generation is uncertain"

 

As a comparasion to RRAM, one of the main contenders for emerging memory technologies:

 

"RRAM include multiple device types and mechanisms with varying level of maturity. The survey is based on rating of the general field rather than specific types. Some recent breakthrough in RRAM significantly enhanced perceived potential of this technology, e.g., 32Gb array demonstration726. Overall RRAM assessment is similar or better than existing CMOS-based nonvolatile memories (Flash). A clear advantage of RRAM is scalability owing to the filamentary conduction and switching mechanisms. The simple device structure and fab-friendly materials also contribute to high rating in CMOS compatibility. One of the major concerns of RRAM is the operation reliability due to the stochastic nature and the defect-related mechanisms. Large variation of RRAM switching parameters has been commonly observed and is considered an intrinsic feature of RRAM mechanisms."

 

Refernces on FeFET:

[65] T. S. Boscke, J. Muller, D. Brauhaus, U. Schroder, and U. Bottger, "Ferroelectricity in hafnium oxide: CMOS compatible ferroelectric field effect transistors," IEDM 2011, pp. 24.5.1–24.5.4.
[66] M. Hyuk Park, H. Joon Kim, Y. Jin Kim, W. Lee, H. Kyeom Kim, and C. Seong Hwang, "Effect of forming gas annealing on the ferroelectric properties of Hf0.5Zr0.5O2 thin films with and without Pt electrodes," Appl. Phys. Lett., vol. 102, no. 11, p. 112914, 2013.
[67] J. Muller, et al, "Ferroelectricity in yttrium-doped hafnium oxide," J. Appl. Phys., vol. 110, no. 11, p. 114113, 2011.
[68] J. Muller, et al, "Ferroelectric Zr0.5Hf0.5O2 thin films for nonvolatile memory applications," Appl. Phys. Lett., vol. 99, no. 11, p. 112901, 2011.
[69] S. Mueller, J. Mueller, A. Singh, S. Riedel, J. Sundqvist, U. Schroeder, and T. Mikolajick, "Incipient Ferroelectricity in Al-Doped HfO2 Thin Films," Adv. Funct. Mater., vol. 22, no. 11, pp. 2412–2417, Jun. 2012.

[70] J. Muller, E. Yurchuk, T. Schlosser, J. Paul, R. Hoffmann, S. Muller, D. Martin, S. Slesazeck, P. Polakowski, J. Sundqvist, M. Czernohorsky, K. Seidel, P. Kucher, R. Boschke, M. Trentzsch, K. Gebauer, U. Schroder, and T. Mikolajick, "Ferroelectricity in HfO2 enables nonvolatile data storage in 28 nm HKMG," 2012 Symp. VLSI Tech., pp. 25–26, 2012

 

Emerging memory taxonomy according to ITRS 2013

For all of you working on emerging memory technologies such as ReRAM, FeRAM, PCM, MRAM etc. this classification scheme in the latest ITRS roadmap should be very useful. Please check out the  ERD - Emerging Research Devices Chapter.

"Figure ERD3 [inserted below] provides a simple visual method of categorizing memory technologies. At the highest level, memory technologies are separated by the ability to retain data without power. Nonvolatile memory offers essential use advantages, and the degree to which non-volatility exists is measured in terms of the length of time that data can be expected to be retained. Volatile memories also have a characteristic retention time that can vary from milliseconds to (for practical purposes) the length of time that power remains on. Nonvolatile memory technologies are further categorized by their maturity. Flash memory is considered the baseline nonvolatile memory because it is highly mature, well optimized, and has a significant commercial presence. Flash memory is the benchmark against which prototypical and emerging nonvolatile memory technologies are measured. Prototypical memory technologies are at a point of maturity where they are commercially available (generally for niche applications), and have a large scientific, technological, and systematic knowledge base available in the literature. These prototypical technologies are covered in Table ERD2 and in the PIDS Chapter. The focus of this section is Emerging Memory Technologies. These are the least mature memory technologies in Fig. ERD4, but have been shown to offer significant potential benefits if various scientific and technological hurdles can be overcome. This section provides an overview of these emerging technologies, their potential benefits, and the key research challenges that will allow them to become viable commercial technologies."

 

Figure ERD3, from the ERD Chapter 2013 - Emerging memory taxonomy (ITRS 2013, Chapter ERD) 

 

If you continue to read from page 8 on you will find a short description of all emerging memory technologies that are being considered by he ITRS. If you´re saturated on resistive technologies you can fast forward to page 12 and read about the new contender FeFET :-)

 

The new ITRS 2013 edition

The new 2013 edition is now released since about a month Follow this link to the Summary Files. However, not all areas/Chapters has been updated. As an example, for Front End Process (FEP) Chapter the status is as follows:

Updated FEP Roadmap tables are: High Performance Devices, Low Standby Power Devices, FeRAM, Thermal, Thin Film, Doping Process Technology, Starting Materials, and Surface Preparation.

 

"Likely to be updated" in 2014: Updates to DRAM, Floating Gate Flash Non-Volatile memory (NVM), Charge Trap Flash NVM, Phase Change Memory, Etch and CMP.

 

We can assume that Samsung, Hynix, Micron, Toshiba and the guys will have some interesting meetings ahead to conclude what to put in those tables :-)

What is The International Technology Roadmap for Semiconductors - ITRS?

"The International Technology Roadmap for Semiconductors is sponsored by the five leading chip manufacturing regions in the world: Europe, Japan, Korea, Taiwan, and the United States. The sponsoring organizations are the European Semiconductor Industry Association (ESIA), the Japan Electronics and Information Technology Industries Association (JEITA), the Korean Semiconductor Industry Association (KSIA), the Taiwan Semiconductor Industry Association (TSIA), and the United States Semiconductor Industry Association (SIA)."

 

"The objective of the ITRS is to ensure cost-effective advancements in the performance of the integrated circuit and the advanced products and applications that employ such devices, thereby continuing the health and success of this industry."

 

The International Technology Roadmap for Semiconductors is sponsored by the five leading chip manufacturing regions in the world: Europe, Japan, Korea, Taiwan, and the United States. (source : http://www.itrs.net/about.html)

Comments on Twitter:
2013 ITRS executive summary, in the autumn of Moore's Law.
The non-planar future: They 2013 International Technology Roadmap for Semiconductors (ITRS)
ITRS 2013- "The new era of scaling is 3D Power Scaling"
Scouting report for materials at end of the road: 2013 ITRS 

 

 

By V-NAND Samsung is set for more advanced products including terabit NAND flash memory

Recently this picture below was published on LinkeIn (I seen it posted by Yangyin Chen
陈杨胤, researcher at imec) and other social media and has been shared a great deal. Naturally there has been comments and questions if it will go on on heading for 128 terabit NAND flash memory 2025 or so.

 

 

To get a glimpse into how this scaling has been possible I checked out the Samsung information on V-NAND as they call their 3D-NAND technology. According to the information available on Samsungs web they have set the foundation for more advanced products including 512 gigabit (Gb) and one terabit (Tb) NAND flash memory, which we expect to develop within the next few years. structure. So single digit terabit should not be a problem. What about 128 TB? I don´t know, but I assume we will need that integrated into a Google lens to record our exiting lives in 3D-HD feeding real time in to Facebook accounts pretty soon :-)  

 

 

Samsung’s new V-NAND offers a 128 gigabit (Gb) density in a single chip, utilizing the company’s proprietary vertical cell structure based on 3D Charge Trap Flash (CTF) technology and vertical interconnect process technology to link the 3D cell array. By applying both of these technologies, Samsung’s 3D V-NAND is able to provide over twice the scaling of 20nm-class planar NAND flash.By making this CTF layer three-dimensional, the reliability and speed of the NAND memory have improved sharply. The new 3D V-NAND shows not only an increase of a minimum of 2X to a maximum 10X higher reliability, but also twice the write performance over conventional 10nm-class floating gate NAND flash memory. [Far East Gizmos]

Picture showing 3D stacking up to 24 layers (from Iter news http://itersnews.com/?p=68244)

 

   "An industry first, it represents a breakthrough in overcoming the density limit currently facing the planar NAND architecture and floating gates used in conventional flash memory, as well as yielding speed and endurance" 

Check out the promo video from Samsungs YouTube channel below.

Samsung 3D-VNAND Promo Video and scaling in 3D

Samsung has been mass-producing 3D NAND modules since August last year according to this source. Here is a most informative news on Samsung 3D-VNAND technology from iTers News discussing limits to 2D scaling beyond 10 nm and "3D scaling".



 

Here is a interesting presentation from Applied Materials on 3D NAND "Winning in 3D NAND" explaining quite some details on process requirements for going from 2D to 3D technology.

 

"Advantage of 3D NAND is that it doesn’t require leading-edge lithography…the burden will shift from lithography to deposition and etch."  Ritu Shrivastava, VP Technology, SanDisk, May 2013 (SemiMD) [Picture is a screenshot from Applied Materials presentation linked above]

HZDR in Germany is printing sub-50 nm nearly-discrete magnetic patterns using chemical disorder induced ferromagnetism

HZDR in Germany is printing nearly-discrete magnetic patterns using chemical disorder induced ferromagnetism. Materials in which the magnetic behavior can be tuned via ion-induced phase transitions may allow the fabrication of novel spin-transport and memory devices using existing lateral patterning tools.

 

Original publication:

 

Printing Nearly-Discrete Magnetic Patterns Using Chemical Disorder Induced Ferromagnetism

Rantej Bali et al

Nano Lett., 2014, 14 (2), pp 435–441

DOI: 10.1021/nl404521c

 

 

Abstract:

 

Ferromagnetism in certain alloys consisting of magnetic and nonmagnetic species can be activated by the presence of chemical disorder. This phenomenon is linked to an increase in the number of nearest-neighbor magnetic atoms and local variations in the electronic band structure due to the existence of disorder sites. An approach to induce disorder is through exposure of the chemically ordered alloy to energetic ions; collision cascades formed by the ions knock atoms from their ordered sites and the concomitant vacancies are filled randomly via thermal diffusion of atoms at room temperature. The ordered structure thereby undergoes a transition into a metastable solid solution. Here we demonstrate the patterning of highly resolved magnetic structures by taking advantage of the large increase in the saturation magnetization of Fe₆₀Al₄₀ alloy triggered by subtle atomic displacements. The sigmoidal characteristic and sensitive dependence of the induced magnetization on the atomic displacements manifests a sub-50 nm patterning resolution. Patterning of magnetic regions in the form of stripes separated by 40 nm wide spacers was performed, wherein the magnet/spacer/magnet structure exhibits reprogrammable parallel (↑/spacer/↑) and antiparallel (↑/spacer/↓) magnetization configurations in zero field. Materials in which the magnetic behavior can be tuned via ion-induced phase transitions may allow the fabrication of novel spin-transport and memory devices using existing lateral patterning tools.

 

[Based on original German News, Ionenstrahlen ebnen den Weg zu neuen Ventilen für die Spintronik and Rossendorfer arbeiten an Ventilen für Spintronik-Chips]

ARM is evaluating CeRAM technology for embedded NVM

ARM is evaluating CeRAM - correlated electron random access memory - technology for embedded NVM according to a recent statment from Symetrix:

"ARM is evaluating CeRAM technology as part of its strategy in embedded nonvolatile memory offerings and their discussions with Symetrix started over three months ago. Symetrix will provide its technology and the results from Symetrix programs ongoing at the University of Texas (Dallas) and the University of Colorado (Colorado Springs) to chip foundries engaged by ARM. Other chip companies are also working with Symetrix under similar terms."

 

EE Times also reported on this and CeRAM technology here: CeRAM Memory Gets ARM's Attention:

"CeRAM is based on a transition metal oxide, in this case nickel oxide (NiO). The premise is that, by cleaning up NiO through a suitable doping technique, it is possible to obtain electrically conducting NiO that can make very rapid, reversible, nonvolatile bulk transitions between its electrically insulating and conducting states. In the past, these transitions were possible only at a high pressure and temperature, but they now can be achieved at room temperature with low switching voltages and currents. Key to the operation is a reversible metal-to-insulator transition (MIT) that has its roots in the work of Sir Nevill Mott and John Hubbard. "

Here is a descriptive presentation from Symetrix that goes into detail on CeRAM and compares it to the more mainbstream ReRAM technology. In short:

1) CeRAM vs. Filament Technologies (ReRAM) according to Symetrix

• Control of material properties and proper device architecture are fundamental to this new paradigm. Evidence? No filament formation. (No electroforming)

• The CeRAM resistor is designed to exploit materials properties, surface properties, switching mechanism (endurance) and memory mechanism (retention).

• Optimizing CeRAM is a different science than building the perfect filament.

 

Unlike ReRAM, CeRAM is resistive memory which uses the same transition metal oxide (TMO), such as NiO, but strands are not used and electroplating. Instead CeRAM-memory quantum correlation effects observed positions of electrons, where it got its name. In the structure of the active region is allocated CeRAM TMO, which separates the two conductive layers TMO, whereas in the transition metal oxide ReRAM occupies entire domain between the metal layers.

2) CeRAM STATUS according to Symetrix:

THEORY: Confirmed with empirical results DONE

MATERIALS: Doping any TMO with any extrinsic ligand PATENTED

PROCESS: Create and isolate thin (5 nm) active region by simple spin-on or ALD PATENT FILED

ARCHITECTURE: Array only (no pass gate) PATENTED

3-D (STACKING) With only silicon friendly materials IN PROCESS

FPGA Architecture PATENT FILED

Further References on CeRAM:

Patents:
16 Patents by Symetrix (as assignee) on "correlated electron memory" as returned from Google Patent search.

Publications on CeRAM:

“A non-filamentary model for unipolar switching transition metal oxide resistance random access memories”, Kan-Hao Xue, Carlos Paz De Araujo, Jolanta Celinska, and Christopher McWilliams, J. Appl. Phys. 109, 091602 (2011)

“Material and process optimization of correlated electron random access memories”, Jolanta Celinska, Christopher McWilliams, Carlos Paz De Araujo, and Kan-Hao Xue, J. Appl. Phys. 109, 091603 (2011)

“Device characterization of correlated electron random access memories”, Christopher McWilliams, Jolanta Celinska, Carlos Araujo, and Kan-Hao Xue, J. Appl. Phys. 109, 091608 (2011)

“Operating Current Reduction in Nickel Oxide Correlated Electron Random Access Memories (CeRAMs) through Controlled fabrication Processes”, Jolanta Celinska, Christopher McWilliams, Carlos Paz De Araujo, and Kan-Hao Xue, Integrated Ferroelectrics, 124, 105-111 (2011)

“Re-Programmable Antifuse FPGA Utilizing Resistive CERAM Elements”, Christopher McWilliams, Carlos Paz De Araujo, Jolanta Celinska, and Kan-Hao Xue, Integrated Ferroelectrics, 124, 97-104 (2011)