The Future Paths for 3DNAND and ALD Opportunities

Here are brief summary of a recent interesting article in Semiconductor Engineering by Mark LaPedus on the topic of future paths for NAND Flash Memory, which is a big market for ALD with strong competition between ASM, Lam Research and others and high aspect ration Etch Technology from Applied Materials and Lam Research. I also and added some stuff that I found elsewhere.

What’s Next For NAND?

May 19th, 2016 - By: Mark LaPedus
http://semiengineering.com/whats-next-for-nand/

Scaling standard 2DNAND technology is coming to an end and all major NAND manufacturers are ramping 3DNAND today.  The NAND market leader (34%, see below) Samsung is in the lead a shipped their first 24 layer 128 gigabit chip in 2013 and have since then introduced a 32 layer are now since last year shipping the 3rd generation 48 layer chip offering a 256 gigabit storage capacity.

Intel and Micron has joined forces in NAND (joint 22% market share) and recently started shipping a 32 layer 3DNAND chip. The other duo, SanDisk (16%) and Toshiba (19%) as well as SK Hynix (10%) are trailing Samsung with their most current 48 layer chips.

Current NAND Flash Market share - Source: Semiconductor Engineering.

3DNAND Technology - Floating Gate vs. Charge Trap Flash

Floating Gate - Micron and Intel, currently uses the floating gate architecture

2015 Micron Presentation explaining the advantages with their 3D NAND floating gate technology shared with Intel.

Here you can read more about the Intel/Micron floating gate technology in an article by Dick James at Chipworks. I am not sure if ALD is used for the oxide and nitride layers but it is a possibility for sure due to high aspect ratio sttructures..


Charge Trap - Samsung, SK Hynix and the SanDisk/Toshiba are all steaming up the layers using charge trap NAND.

Samsung Promo video: Samsung's 3D V-NAND flash memory is fabricated using an innovative vertical design. Its vertical architecture stacks 32 cell layers on top of one another, rather than trying to decrease the cells' length and width to fit today's ever-shrinking form factors. [youtube.com]

A Look Ahead at IEDM 2015, Solid State Technology, By Dick James, Senior Technology Analyst, Chipworks

Many available cross sections of available on the internet show high-k material (Al2O3) and a metal nitride (TiN) gate being used for the to connect to the tungsten control gate. I can only assess it as ALD being used in these extreme aspect ratios. 

According to a statement in the article made by Applied materials 3DNAND will make the step from 48 to 64 layers in 2016 and if it can be scaled further will be limited at some point by high aspect ration etch capability of 96 or 128 layers. However, I am a bit doubtful here that actually the technology will be limited by etch unit process engineers. As a comparison, many think that deep trench DRAM scaling was killed by high aspect ratio etch but it was not, it was rather the impossibility to scale the memory cell down from 8F2 , via 6F2 down ti a most compact 4F2 cell design. In any, case these are not extreme aspect ratios for ALD so either the etchers or the device physics will have to throw in the towel for 3DNAND momentarily. - to conclude there are two possible paths according to Mark LaPedus:

The first path:

"So going forward, NAND suppliers will simultaneously follow two parallel paths. The first path is to wait for the etch tools and other manufacturing techniques to arrive. And if they arrive on time, vendors could scale today’s 3D NAND device from 32- and 48-layers, to 64 layers, to 96 and then to 128."

The second path:

"The second path is to move towards string stacking technology. This involves stacking two or more individual devices on top each other. Each device is separated by an insulating layer. String stacking is already in the works. Recently, Micron presented a paper on a new 64-layer chip. Micron, according to multiple sources, stacked two 32-layer chips on top of each other. In theory, string stacking could involve several different combinations. For example, a vendor could stack three 32-layer chips, enabling a 96-layer device. In addition, a vendor could stack three 96-layer chips, resulting in a 288-layer product."

Micron and Intel Unveils 3D NAND

Micron and Intel Unveils 3D NAND : The World’s Highest-Capacity NAND Flash Memory

"The interdependent, growing demands of mobile computing and data centers continue to drive the need for high-capacity, high-performance NAND flash technology. With planar NAND nearing its practical scaling limits, delivering to those requirements has become more difficult with each generation. Enter our new 3D NAND technology, which uses an innovative process architecture to provide 3X the capacity of planar NAND technologies while providing better performance and reliability."

3 times the capacity of existing NAND products—enough to enable 3.5TB gum stick-sized SSDs or more than 10TB in standard 2.5-inch SSDs.

 

The City College of New York report on ultimate replacement for flash memory

As reported by The City College of New York:  The quest for the ultimate memory device for computing may have just taken an encouraging step forward. Researchers at The City College of New York led by chemist Stephen O’Brien have discovered new complex oxides that exhibit both magnetic and ferroelectric properties.

Combining both properties is very exciting scientifically for the coupling that can occur between them and for the devices that might ultimately be designed, in logic circuits or spintronics. Combining these two properties in a single material, however, has proved difficult until now.

Using an innovative inorganic synthesis technique, an interdisciplinary team led by Dr. O’Brien, associate professor of chemistry at The City College and a member of the CUNY Energy Institute at CCNY, prepared a mineral previously unknown in nature.

X‐ray and electron micrographs of new discovery together with model of the crystal structure (Picture from The City College of New York)

 

“It’s based on common elements: barium, titanium and manganese,” said Professor O’Brien, who’s also an established nanotechnology researcher.

Together with collaborators from Drexel University, Columbia, Brookhaven National Laboratory and China’s South University of Science and Technology, they solved the structure and observed both magnetic and ferroelectric behavior. What they uncovered was a new Hollandite crystal group designated “multiferroic.”

Their finding confirmed a prediction by scientists dating back nearly two decades of the ferroelectric nature of such inorganic substances.

On multiferroics and their possible application, Professor O’Brien said: “The Holy Grail in this field is the combination of both magnetic and ferroelectric elements at room temperature with a sufficient magnitude of interaction.”

This, he added, could lead to the “ultimate replacement for flash memory” or smaller memory devices with massive storage capacities.

This concurs with British physicist J.F. Scott, who is regarded as the "the father of integrated ferroelectrics." A researcher at Cambridge University, Dr. Scott believes that multiferroics might hold the future for the ultimate memory device.

The CCNY findings appear in the Nature online journal “Scientific Reports.”

About The City College of New York
Since 1847, The City College of New York has provided low-cost, high-quality education for New Yorkers in a wide variety of disciplines. More than 16,000 students pursue undergraduate and graduate degrees in: the College of Liberal Arts and Sciences; the Bernard and Anne Spitzer School of Architecture; the School of Education; the Grove School of Engineering; the Sophie Davis School of Biomedical Education, and the Colin Powell School for Civic and Global Leadership. U.S. News, Princeton Review and Forbes all rank City College among the best colleges and universities in the United States.

Toshiba Corporation starting 15nm 128-gigabit NAND flash at Fab 5 Yokkaichi

Toshiba Corporation announced that it has developed the world's first 15-nanometer (nm) process technology, which will apply to 2-bit-per-cell 128-gigabit (16 gigabytes) NAND flash memories. Mass production with the new technology will start at the end of April at Fab 5 Yokkaichi Operations, Toshiba's NAND flash fabrication facility (fab), replacing second generation 19 nm process technology, Toshiba's previous flagship process. The second stage of Fab 5 is currently under construction, and the new technology will also be deployed there.

Read more at Tweaktown.

 

 

"In-keeping with semiconductor industry fast-track construction techniques and schedules, Toshiba and manufacturing partner, SanDisk have officially opened their third 300mm wafer NAND flash fabrication facility at Toshiba's Yokkaichi Operations in Mie Prefecture, Japan, dubbed Fab 5." (Fabtech)

If you want to take a visit Google Street View offers excellent view from the Toshiba site in Yokkaichi. Just tune in here in this intersection take a right turn and enjoy the drive : Toshiba Fab 5.

 

Screendump from Google Street View just upfront of Toshiba Fab 5 in Yokkaichi.