Friday, May 1, 2015

InAs Nanowire Transistors with Multiple Independent Wrap-Gate Segments

The Nanometer Structure Consortium (nmC) at, Lund University Sweden and School of Physics, University of New South Wales, Australia demonstrate a method for making horizontal wrap-gate nanowire transistors with up to four independently controllable wrap-gated segments. The excellent scalability potential of horizontal wrap-gate nanowire transistors makes them highly favorable for the development of advanced nanowire devices and possible integration with vertical wrap-gate nanowire transistors in 3D nanowire network architectures.

InAs Nanowire Transistors with Multiple, Independent Wrap-Gate Segments
A. M. Burke, D. J. Carrad, J. G. Gluschke, K. Storm, S. Fahlvik Svensson, H. Linke, L. Samuelson, and A. P. Micolich
Nano Lett., Article ASAP, DOI: 10.1021/nl5043243


Abstract Image

AN InAs Nanowire Transistors with Multiple, Independent Wrap-Gate Segments (Graphical Abstracts Nano Lett., Article ASAP, DOI: 10.1021/nl5043243)

We report a method for making horizontal wrap-gate nanowire transistors with up to four independently controllable wrap-gated segments. While the step up to two independent wrap-gates requires a major change in fabrication methodology, a key advantage to this new approach, and the horizontal orientation more generally, is that achieving more than two wrap-gate segments then requires no extra fabrication steps. This is in contrast to the vertical orientation, where a significant subset of the fabrication steps needs to be repeated for each additional gate. We show that cross-talk between adjacent wrap-gate segments is negligible despite separations less than 200 nm. We also demonstrate the ability to make multiple wrap-gate transistors on a single nanowire using the exact same process. The excellent scalability potential of horizontal wrap-gate nanowire transistors makes them highly favorable for the development of advanced nanowire devices and possible integration with vertical wrap-gate nanowire transistors in 3D nanowire network architectures.