Imec presents successors to FinFET for 7nm and beyond at VLSI Technology Symposium 2015

Leuven (Belgium)– June 17, 2015 – At this week’s VLSI 2015 Symposium in Kyoto (Japan), imec reported new results on nanowire FETs and quantum-well FinFETs towards post-FinFET multi-gate device solutions. 

The Technology roadmap as presented recently by Imec at the EWMOVPE workshop in Lund, Sweden.

As the major portion of the industry adopts FinFETs as the workhorse transistor for 16nm and 14nm, researchers worldwide are looking into the limits of FinFETs and potential device solutions for the 7nm node and beyond. Two approaches, namely Gate-All-Around Nanowire (GAA NW) FETs, which offer significantly better short-channel electrostatics, and quantum-well FinFETs (with SiGe, Ge, or III-V channels), which achieve high carrier mobility, are promising options. 

For the first time, imec demonstrated the integration of these novel device architectures with state-of-the-art technology modules like Replacement-Metal-Gate High-k (RMG-HK) and Self (Spacer)-Aligned Double-Patterned (SADP) dense fin structures. By building upon today’s advanced FinFET technologies, the work shows how post-FinFET devices can emerge, highlighting both new opportunities as well as complexities to overcome. 

Imec and its technology research partners demonstrated SiGe-channel devices with RMG-HK integration. Besides SiGe FinFET, a unique GAA SiGe nanowire channel formation during the gate replacement process has been demonstrated. The novel CMOS-compatible process converts fin channels to nanowires by sacrificial Si removal during the transistor gate formation. The process may even enable future heterogeneous co-integration of fins and nanowires, as well as Si and SiGe channels. The work also demonstrates that such devices and their unique processing can lead to a drastic 2x or more improvement in reliability (NBTI) with respect to Si FinFETs. 

Moreover, imec demonstrated Si GAA-NW FETs based on SOI with RMG-HK. The work compares junction-based and junction-less approaches and the role of gate work function for multi-Vt implementations. New insights into the improved reliability (PBTI) with junction-less nanowire devices have been gained.

Extending the heterogeneous channel integration beyond Si and SiGe, imec demonstrated for the first time strained Ge QW FinFETs by a novel Si-fin replacement fin technique integrated with SADP process. Our results show that combining a disruptive approach like fin replacement with advanced modules like SADF-fin, RMG-HK, direct-contacts can enable superior QW FinFETs. The devices set the record for published strained Ge pMOS devices, outperforming by at least 40% in drive current at matched off-currents.

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GLOBALFOUNDRIES, INTEL, Micron, Panasonic, Samsung, SK hynix, Sony and TSMC.

The success story of the European Semiconductor R&D Model!

I am pretty fed up with all these depressing statements and news that you can´t do leading edge semiconductor research in Europe and especially not in Germany or Sweden. Europe is failing and so on bla, bla, bla. That is why I was very happy to read about trouble elsewhere and I came to the conclusion that Europe is maybe the place to be in after all so that´s why I at the end tilted this blog - The success story of the European Semiconductor R&D Model! 

So here is what triggered me to write this:

"Rising costs and a consolidating industry are forcing companies to rethink where to place their dollars; Europe and Asia step up investments. " Says Mark Lapedus in a recent article in Semiconductor Engineering. 

He goes on stating how research and development is a sometimes forgotten but critical element in the semiconductor industry and paints a picture of how the R&D landscape is affected by all this and come with some interesting facts:

1) Asian and European R&D organizations are expanding their efforts while the United States is taking a step back. 

2) Sematech, a major R&D chip consortium in the U.S., is falling by the wayside, at least as a standalone organization.

According to Lapedus Sematech’s issues began showing up in March, when Intel confirmed it had exited from the R&D consortium followed by Samsung and TSMC. Leaving GlobalFoundries as one of the few remaining members in the organization.

As far as I know all these leading companies are Core members of Imec and have no plans of pulling out there. On the contrary they are steaming ahead scaling as fast as ever. 10 nm FinFET in the Pipeline, 7 and 5 nm programs and beyond are up and running at Imec.

Construction work at Imec, Leuven, June 2013.

I recently went to a MOVPE (same as MOCVD) Workshop in Lund Sweden (see picture below), and listenend to an interesting invited talk from Imec and there is a sold plan for III/V CMOS silicon 300 mm wafers. How solid is it you may ask - Imec is shuffling 300 mm integrated fort end test wafers through an Applied Materials MOCVD Centura advanced cluster tool since a while. According to Imec III/V channel material has been fabed on 300 mm. In addition, an interesting comment after the talk from Aixtron was "Intel and others are running III/V pre production".

The Imec Technology roadmap for CMOS scaling beyond 5 nm. Shown at the European Workshop on MOVPE 2015, in Lund, Sweden, in an invited talk, Bernardette Kunert, IMEC, Leuven, Belgium "Challenges for III/V in CMOS application".

Imec logic device roadmap - Device technology features. (Imec/ITF Korea 2015). Here you can see that at 5 nm there is an option for III/V channel material and possibly vertical Nanowire integration. Next time we will get updated from Imec will be at SEMICON West where An Steegen will give a presentation (http://www.semiconwest.org/node/13826)

Then lets´have a look on CEA/ Leti - also a European R&D organization. CEA/Leti together with ST Micro are steaming down a slightly different path than Imec focusing instead on SOI and FD-SOI technology and 3D stacked CMOS. Here a success has already been seen Globalfoundries Fab1 is putting up and running 20 nm FD-SOI technology. Samsung has signed a deal with ST Micro for the same - yet another european success story in Advanced CMOS scaling.

So to come to the point - when do you hear about scaled advance Logic device data on 300 mm coming out of CNSE or Sematech in New York the last years? How much has been invested there compared to the itty bitty 300 mm R&D Fabs in Europe? I may have missed certain findings but I am sure there is not much out there from Albany. OK they have a different task maybe, more focus on production and so on but at the end of the day much of the cool stuff still comes out of European R&D Pilot fabs.

Why is it so? Here are my thoughts and I would be interested in yours so please do not hesitate to use the comment field or drop me a private e-mail (jonas.sundqvist@baldengineering.com)

1) The management in Europe are Researchers and Innovators themselves - look at Imec, all the top level management, including the CEO Luc Van den Hove, are University Professors. They are not just holding the title here, they are leading research and students. I once took part in a series of workshops between Fraunhofer, TU Dresden and Imec top level managment and when it came to schedule the next meeting we had to adjust time in accordance to upcoming student exams in  Germany and Belgium - Would this happen in The US at that level?

Regarding the top management, I assume you have a similar situation at CEA/Leti and not to mention Fraunhofer - you can´t be taken serious in Fraunhofer unless your title starts with Herr Prof. Dr. Dr. In america they are all called Bill or George! Anything but Sue!

2) The track record. Imec and CEA/Leti has a long track record at their current locations and has not been forced to move - look at Sematech they had to move from warm Texas to Up State New York. People must have died the first weeks of winter out of frost bite. You just can´t move top notch researcher - not even in the US. 

3) Cross national Collaboration - in Europe all Universities are forced to collaborate with each other to become funded by the EU and in many cases also by the national funding organizations and it does´t matter if you fiddle around with coupons or shuffle 300 mm wafers - the same rules and incentives for everybody. In The US I have a sense that only the 4/6 inch wafer based National Labs and University Cleanrooms have to do this and that they are then financed partly by DARPA and Dr. Polla at IARPA - so the cool stuff is done on small wafers and then the industry steps in and scale it up. Please do correct me if I have the wrong picture here.

So a great success in European Semiconductor R&D that ends when it is time for production - then the Value Chain is sort of half broken - who cares we get to do the cool stuff and the Americans and Asians to shuffle the wafers in Mega Fabs and each wafer will travel at high speed and make multiple passes through an ASML super advanced Lithography tool.

ASML Lithography tool Installed at Imec 300 mm line in Leuven, Belgium (www.imec.be)

Asenov claims Nanowire transistors (NWT) favourite to succeed FinFET at 5 nm

Nanowire transistors are the most likely successor to finfets and will scale to 5nm, says Professor Asen Asenov, Professor of Electrical Engineering at Glasgow University and CEO of Gold Standard Simulations (GSS) which specialises in the predictive simulation of nano-CMOS devices including statistical variability and reliability.

”While 16/14nm FinFETs are about to enter volume production at the major foundries, the next generation transistors suitable for 7nm CMOS and below are already on the drawing board,” says Asenov, “one of the best candidates “Gate all around” transistors, better known as nanowire transistors (NWT), have superior scaling properties compared to FinFETs and can be scaled to channel lengths of approximately 5nm. ”

See more at: http://www.electronicsweekly.com/news/manufacturing/nanowire-transistors-will-replace-finfets-says-asenov-2015-05/?sthash.7S2u0ZL7.mjjo#sthash.7S2u0ZL7.TIRVaDXp.dpuf

Mobile charge distribution in a NWT with different cross-sections suitable for 7nm CMOS technology. Due to quantum mechanical confinement effects ‘strange’ patterns determine the Source' Drain' Gate' Spacer' Channel' positions of the current flow in the nanowire cross-section (Picure from GSS).

Samsungs road from HKMG to 14 nm FinFET

Here is an excellent article describing Samsungs road from 32 nm planar high-k first HKMG technology to 14 nm FinFET published in EE Times. The whole article is based in reverse engineering from TECHINSIGHT and recent publications and patents for Samsung and Globalfoundries. According to the article Samsung has lagged behind Intel in release of process nodes. However, remarkably now shrunk the lag for its 14nm to about 6 months. This article verifies the introduction of a HfO2 ALD gate dielectric at 32 nm IBM common platform technology and the ALD cap TiN.

Samsung 32nm NMOS transistor (left) and PMOS transistor (right) from EE Times / TECHINSIGHTS.

Samsung 20nm NMOS transistor (left) and PMOS transistor (right) from EE Times / TECHINSIGHTS. The PMOS showing the use of ALD TiN Work function metal gate and an ALD TaN etch stop, an ALD TiN cap and ALD HfO2 gate oxide. 

Samsung Exynos 7420 FinFET transistors from EE Times / TECHINSIGHTS. Patterning has been down with the Samsung SAPD (Self Aligned Double Patterning) technology which most probably involves a PEALD low temperature SiO2 on resist and as can be seen an ALD High-k metal gates each wrapping around the silicon fins. In addition it is quite possible that the channel doping have been realized by solid state difusion doping by deposition P and B doped silicon oxide by ALD or PEALD and diffusing the dopants into the channel by an RTP step like described here - however this is just speculation from my side.

The 14 nm FinFET is the actual technology that you will get if you buy a Samsung Galaxy S6 today, which uses the Samsung Exynos 7420 SoC - must be one of the most fully loaded ALD enabled products on the market today. Except for the processor, there must be plenty of ALD also for sure in the 3G SDRAM and the 32 GB NAND Flash. You can read more about the teardown here by Chipworks.

Chinese and US researchers dope & un-dope graphene FETs by ALD

Despite the tremendous world wide focus on the wonder material graphene, its pristine form can't be used in field-effect transistors (FETs) to replace current channel materials (Si, SiGe, III/V) between the source and drain suffer from the absence of a bandgap.

Here reseraches are seeking  to chemically modify or dope grapheneto open up a  band gap in the material. However, the carbon atoms in graphene are arranged in a two-dimensional sp² hybridization surface, which makes it almost impossible to induce any chemical modification or doping without alteration of its idealized properties.

Finally, in order to form a super fast CMOS logic based on ultra fast graphene FETs (GFET) you need to be able to dope the GFETs in to NMOS and PMOS transistores and it has been proven very difficult to produce a stable n-type graphene transistors than its p-type counterpart.

A team of Chinese and US researchers [1, 2, 3, 4] have developed a simple method to produce n-type doping of graphene by using an ALD chamber. That is not all - the mechanism is reversible, meaning they can bring back graphene to p-type by a thermal anneal step. The main mechanism of n-type doping is driven by a surface charge transfer at graphene/redox interfaces during the ALD processing of Al2O3. Fantastic - Check out the details in the publication below!


Reversible n-Type Doping of Graphene by H2O-Based Atomic-Layer Deposition and Its Doping Mechanism
Li Zheng, Xinhong Cheng, Zhongjian Wang, Chao Xia, Duo Cao, Lingyan Shen, Qian Wang, Yuehui Yu, and Dashen Shen
J. Phys. Chem. C, 2015, 119 (11), pp 5995–6000
DOI: 10.1021/jp511562t

The pre-H2O treatment and Al2O3 film growth under a two-temperature-regime mode in an oxygen-deficient atomic layer deposition (ALD) chamber can induce n-type doping of graphene, with the enhancement of electron mobility and no defect introduction to graphene. The main mechanism of n-type doping is surface charge transfer at graphene/redox interfaces during the ALD procedure. More interestingly, this n-type doping of graphene is reversible and can be recovered by thermal annealing, similar to hydrogenated graphene (graphane). This technique utilizing pre-H2O treatment and an encapsulated layer of Al2O3 achieved in an oxygen-deficient ALD chamber provides a simple and novel route to fabricate n-type doping of graphene. (From grapfical abstract J. Phys. Chem. C, 2015, 119 (11), pp 5995–6000)

[1] State Key Laboratory of Functional Materials for Informatics
[2] Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China
[3] University of Chinese Academy of Sciences, Beijing 100049, China
[4] University of Alabama in Huntsville, Huntsville, Alabama 35899, United States
 

VIDEO - How does a transitor work?

Here is a great video for education or just for fun on how a transitor works by Veritasium

Screendump from the video involving Swiss cheese...

 

Here the video link to Youtube:

At 7nm Silicon giving way to Ge, III-IV, CNT and Graphene

In 1950s, when industry has moved from vacuum-tube diodes and triodes to solid-state diodes and transistors, electronics device researchers have selected Germanium as their semiconductor material. Early solid state diodes and bipolar junction transistors were made using Germanium material. But quickly Germanium replaced with silicon. In today's complementary metal–oxide–semiconductor (CMOS) digital integrated circuits, silicon is used near 100%. Now with the geometries of MOSFET shrinking further down the 14/10 nm, the performance of silicon as MOSFET channel material is questionable, with limitations in frequency of switching, and even the switch itself is erroneously operating. Well the future can be called post-silicon era, where the industry is moving from microelectronics to nanoelectronics/photonics.

IBM said in one of its release "Their (latest Si chips) increasingly small dimensions, now reaching the nanoscale, will prohibit any gains in performance due to the nature of Silicon and the laws of physics. Within a few more generations, classical scaling and shrinkage will no longer yield the sizable benefits of lower power, lower cost and higher speed processors that the industry has become accustomed to."

In the immediate future, the transition into <7nm is basically moving into non-Silicon CMOS switching, EUV lithography and increased on-chip photonics, a combination of control of electrons and photon flow in single integrated device. The 3D growth of structures will be more prominent.

Full article: At 7nm Silicon giving way to Ge, III-IV, CNT and Graphene : http://www.eeherald.com/section/news/onws20150111001a.html

WODIM 2014, the 18th Workshop on Dielectrics in Microelectronics, 9-11 June 2014 in Kinsale Cork Ireland.

Coming up next week - The 18th Workshop on Dielectrics in Microelectronics, which takes place from 9-11 June 2014 in Kinsale Co Cork Ireland. This event is hosted by Tyndall National Institute, UCC, Cork, and celebrates the 10th anniversary of the last time the workshop was held in Ireland.

 

 

The main objective of the workshop is to bring together specialists who work in the field of dielectrics and all aspects of their application in the field of micro and nanoelectronics. The forum is intended to provide an overview of the state of the art in this significant field, and to promote a relatively informal atmosphere for the discussion of the latest research results, where contributions from students are particularly encouraged. The workshop deals with a range of issues in the field of advanced and new dielectrics, such as: growth and deposition, modelling and simulation, physical and electrical properties, reliability and dielectric applications.

 

 

 Kinsale, Co Cork, Ireland, in one of the most beautiful coastal towns in Ireland.

 

One of the more interesting talks will be on Tuesday ;-)

09.40 “Fluorine Interface Treatments within the Gate Stack for Defect Passivation in 28nm HKMG Technology”

M. Drescher1, E. Erben2, M. Trentzsch2, C. Grass2, M. Hempel2, A. Naumann1, J. Sundqvist1, J. Schubert3, J. Szillinski3, A. Schäfer3, S. Mantl3

1 Fraunhofer IPMS-CNT, Königsbrückerstraße 180, 01099 Dresden, Germany, 2 Globalfoundries,
Wilschdorfer Landstraße 101, 01109 Dresden, Germany, 3 Forschungszentrum Jülich, Wilhelm-Johnen-Straße, 52428 Jülich, Germany

 

Integration of thulium silicate for enhanced scalability of HKMG CMOS technology

A very interesting fresher than fresh PhD Thesis from Royal Institute of Technology (KTH), Sweden on the Integration of thulium silicate for enhanced scalability of high-k/metal gate CMOS technology. The ALD processing in this work has been preformed in a  Beneq TFS 200 ALD system - a crossflow-type 200mm hot-wall reactor. The public defense will take place on 27 May 2014 at 10.00 a.m. in Sal D, Forum, Kungliga Tekniska Högskolan, Isafjordsgatan 39, Kista. - Best of luck!

 

Left, the process flow and right a TEM cross-section of the TmSiO/HfO2/TiN gate stack implemented in gate-last MOSFETs. (From the thesis below)

Integration of thulium silicate for enhanced scalability of high-k/metal gate CMOS technology
EUGENIO DENTONI LITTA
Doctoral Thesis in Information and Communication Technology, Stockholm, Sweden 2014

Abstract: High-k/metal gate stacks have been introduced in CMOS technology during the last decade in order to sustain continued device scaling and ever improving circuit performance. Starting from the 45nm technology node, the stringent requirements in terms of equivalent oxide thickness and gate current density have rendered the replacement of the conventional SiON/poly-Si stack unavoidable. Although Hf-based technology has become the de facto industry standard for high-k/metal gate MOSFETs, problematic long-term scalability has motivated the research of novel materials and solutions to fulfill the target performances expected of gate stacks in future technology nodes. In this work, integration of a high-k interfacial layer has been identified as the most promising approach to improve gate dielectric scalability, since this technology presents the advantage of potential compatibility with both current Hf-based and plausible future higher-k materials. Thulium silicate has been selected as candidate material for integration as interfacial layer, thanks to its unique properties which enabled the development of a straightforward integration process achieving well-controlled and repeatable growth in the sub-nm thickness regime, a contribution of (0.25 ± 0.15)nm to the total EOT, and high quality of the interface with Si. Compatibility with industry-standard CMOS integration flows has been kept as a top priority in the development of the new technology. To this aim, a novel ALD process has been developed and characterized, and a manufacturable process flow for integration of thulium silicate in a generic gate stack has been designed. The thulium silicate interfacial layer technology has been verified to be compatible with standard integration flows, and fabrication of high-k/metal gate MOSFETs with excellent electrical characteristics has been demonstrated. The possibility to achieve high performance devices by integration of thulium silicate in current Hf-based technology has been specifically demonstrated, and the TmSiO/HfO2 dielectric stack has been shown to be compatible with the industrial requirements of operation in the sub-nm EOT range (down to 0.6nm), reliable device operation over a 10 year expected lifetime, and compatibility with common threshold voltage control techniques. The thulium silicate interfacial layer technology has been especially demonstrated to be superior to conventional chemical oxidation in terms of channel mobility at sub-nm EOT, since the TmSiO/HfO2 dielectric stack achieved 20% higher electron and hole mobility compared to state-of-the-art SiOx/HfO2 devices at the same EOT. Such performance enhancement can provide a strong advantage in the EOT-mobility trade-off which is commonly observed in scaled gate stacks, and has been linked by temperature and stress analyses to the higher physical thickness of the high-k interfacial layer, which results in attenuated remote phonon scattering compared to a SiOx interfacial layer achieving the same EOT.