Atomic Layer Etching as a Scaling Enabler: From Isotropic Chemistry to Selective, Directional, and Geometry-Driven Patterning

Continued scaling in semiconductor manufacturing increasingly relies on atomic-scale control of etching for complex 3D material stacks, making patterning precision a growing industrial bottleneck. Atomic layer etching (ALE) has emerged as a key enabler, with plasma-driven anisotropy and surface-chemistry control allowing improved selectivity and profile fidelity for advanced logic and memory integration. Current approaches emphasize decoupling surface modification from material removal to enable low-temperature, highly controlled processes.

From an industry perspective, the focus is shifting toward systematic ALE process development frameworks that combine thermodynamic screening, tailored half-cycle chemistries, and experimental verification of etch rates and selectivity. These strategies are increasingly relevant as device architectures push beyond conventional materials and dimensions. At the same time, ALE is gaining attention for its potential to reduce process complexity, energy use, and chemical consumption, positioning it as both a scaling and sustainability enabler for future semiconductor manufacturing.

In a recent paper by Smith et al (reference below), Thermal ALE is described as a purely chemical, vapor- or gas-phase process in which both the surface modification and removal steps are self-limiting and thermally activated. Volatile products are typically formed through ligand-exchange reactions that generate metalorganics. Because no ions are involved, this mode of ALE is intrinsically isotropic, leading to uniform material removal in all directions. This makes thermal ALE attractive for conformal trimming, lateral recessing, and highly selective etches, but fundamentally limits its ability to produce vertical, profile-controlled features.

(a) Periodic table of the elements showing which metals, metal oxides, and metal nitrides have had ALE processes developed for them. In developing a new ALE process, determining the nature of the volatile etch product is critical, with some metals proving more favorable to etching via the formation of volatile metalorganics and others via volatile metal halides. Data compiled from the ALE Database [reference]. (b) An outline of the pathways by which reported ALE processes can proceed. Metals, metal oxides, and metal nitrides can be halogenated, with the modified layer removed by subsequent Ar⁺ sputtering or ligand exchange. Metals can be oxidized or nitrided, and the metal oxide or nitride subsequently etched. (c) Gibbs free energy minimization and volatility diagram analysis can be used to theoretically screen possible etch processes. (d) Various surfaces of Ni modified with (1) surface O, (2) mixed surface and subsurface O, and (3) subsurface O. The Gibbs free energy of reaction showed the importance of having an oxidized sublayer to achieve favorable thermodynamic etching. Adapted from ref [reference]. (e) Analysis of Gibbs free energy of reaction: nitridation of nickel could form metastable Ni3N, which can be etched through favorable reactions with formic acid, forming dimers of nickel formates. by Smith et al (reference below)

In contrast, plasma ALE introduces ions as an active control parameter, most commonly during the removal step. A plasma first forms a chemically modified surface layer, such as a halogenated or oxidized film, which is then selectively removed by directional ion bombardment within a narrow ALE energy window. The momentum of the ions provides anisotropy, enabling vertical etching with atomic-scale precision while suppressing continuous sputtering. This directionality comes at the cost of tighter process windows and increased sensitivity to ion-induced damage.

A hybrid plasma–thermal ALE approach is presented as a way to decouple anisotropy from volatilization chemistry. In this scheme, plasma exposure is used to directionally modify the surface or precisely control the thickness of the modified layer, while removal proceeds via isotropic, thermally driven ligand-exchange reactions. This allows anisotropy to be engineered through selective surface modification rather than sputtering alone. Overall, the key conclusion is that isotropic versus directional behavior in ALE is determined by how and where ions are used, not simply by whether the process is labeled thermal or plasma.

Comment on Geometry

From an industrial standpoint, atomic layer etching is emerging as a core patterning technology as device scaling shifts toward complex 3D architectures and heterogeneous material stacks where conventional plasma etching reaches its limits. Smith et al. highlight that future adoption will be driven by selective ALE, enabled by surface-chemistry engineering, controlled anisotropy, and precise balance between etching and deposition rather than brute-force sputtering. In this landscape, AlixLabs’ use of geometrical selectivity extends the ALE paradigm by exploiting feature pitch and local geometry as an additional selectivity axis, enabling pattern multiplication and critical dimension scaling without added lithography complexity. The convergence of chemical, directional, and geometrical selectivity positions ALE not as a niche technique, but as a scalable, cost- and sustainability-aligned solution for next-generation semiconductor manufacturing.

The relevance of these advances is underscored by their recent and upcoming exposure at major industry forums. Results demonstrating sub-10 nm, high-aspect-ratio patterning with APS™ were presented at the 248th Electrochemical Society (ECS) Meeting in October 2025, marking an important milestone in validating the technology on bulk silicon using mature lithography. This momentum continues at SPIE Advanced Lithography + Patterning 2026, where AlixLabs will present new APS™ results spanning nanoimprint lithography and simplified self-aligned quadruple patterning, including joint work with UMC. Together, these events signal APS™ and geometrically selective ALE moving from concept and lab validation toward broader industrial evaluation and integration.

AlixLabs announced that Dr. Dmitry Suyatin, CIPO and Co-Founder, presented new APS™ (Atomic Layer Etching Pitch Splitting) results at the 248th ECS Meeting in Chicago (October 12–16, 2025), demonstrating high-aspect-ratio, narrow-fin patterning on bulk silicon with critical dimensions below 10 nm using standard 193-nm immersion lithography. The results reinforce APS™ as a viable path to advanced logic patterning without next-generation scanners, enabling reduced process complexity and cost. Supported by recent patent milestones and progress toward a beta tool planned for operation in fall 2026, APS™ is positioned to move from lab-scale validation toward production-grade refinement, aligning with AlixLabs’ goal of making advanced semiconductor manufacturing more accessible and sustainable.

AlixLabs announced its participation at SPIE Advanced Lithography + Patterning in San Jose, where two abstracts by Reza Jafari Jam et al and Robin Athlé et al have been accepted for oral presentation, including one in collaboration with United Microelectronics Corporation (UMC). The presentations will showcase recent progress in APS™ (Atomic Layer Etching Pitch Splitting), demonstrating sub-13 nm half-pitch patterning on silicon and a simplified alternative to self-aligned quadruple patterning that delivers a 4× density increase using a streamlined three-step process. Together, the talks highlight APS™ as a precise, cost-effective, and more sustainable approach to advanced nano-patterning that reduces complexity compared with conventional multi-patterning schemes.

Reference:

AlixLabs – News

Adapted from Smith, T. G. and Chang, J. P., Atomic Layer Etching in Patterning Materials: Anisotropy, Selectivity, Specificity and Sustainability, Plasma Chemistry and Plasma Processing, 46:9 (2026), © The Author(s) 2026. Published by Springer Nature and licensed under CC BY 4.0.

Smith, T. G., Chang, J. P., Atomic Layer Etching in Patterning Materials: Anisotropy, Selectivity, Specificity and Sustainability, Plasma Chemistry and Plasma Processing, 2026, 46:9.

Atomic Layer Etching in Patterning Materials: Anisotropy, Selectivity, Specificity and Sustainability | Plasma Chemistry and Plasma Processing

Intel Foundry Advances Future Logic Scaling with Manufacturable 2D Transistors and High NA EUV Integration

Intel Foundry has demonstrated concrete momentum in de-risking 2D field-effect transistors as a future scaling path beyond silicon, through long-term collaboration with Imec. Results presented at IEDM show a world-first, 300 mm fab-compatible integration of key 2DFET modules, including source/drain contacts and gate stacks, using transition-metal dichalcogenide channels (WS₂ and MoS₂ for n-type, WSe₂ for p-type devices). The core innovation is a selective oxide etch applied to high-quality Intel-grown 2D layers capped with AlOx/HfO₂/SiO₂, enabling damascene-style top contacts while preserving the integrity of atomically thin channels. 

Fab-compatible 2D FET process integration on 300 mm wafers, demonstrating selectively recessed oxide caps that enable damascene-style top contacts on WS₂, MoS₂, and WSe₂ channels, along with replacement-oxide gate stacks and interlayer-selective removal that scales gate CET from 2.5 nm to 1.5 nm. The work establishes manufacturable contact and gate modules as fundamental building blocks for future 2D transistor integration (IEDM Paper 10.1, Q. Smets et al.).

By validating these processes in production-class integration flows, Intel Foundry is addressing two of the most critical barriers to 2D transistor adoption—contact resistance and gate integration—while enabling realistic benchmarking, modeling, and design pathfinding. This work showcases Intel Foundry’s strategy of emphasizing manufacturability early in research, positioning 2D transistors as a credible, scalable option for future logic nodes and stacked transistor architectures.

Fab-compatible 2D FET process integration demonstrated on 300 mm wafers. An imec-led research team reports new manufacturable process modules enabling scalable integration of 2D field-effect transistors in a 300 mm pilot line. Exploiting the strong chemical selectivity and anisotropic van der Waals structure of transition-metal dichalcogenides, the work demonstrates for the first time a selectively recessed oxide cap that enables damascene-style top contacts on monolayer WS₂, MoS₂, and multilayer WSe₂ channels, resulting in improved contact resistance. A replacement-oxide gate stack with scaled equivalent oxide thickness is also shown. In addition, a novel interlayer-selective removal process based on liquid intercalation reduces the top-gate capacitance-equivalent thickness from 2.5 nm to 1.5 nm. Together, these modules form fundamental building blocks for future 2D integration technologies. Top row: epitaxial TiN growth enabled by a 2D template (left, center) and chemical confirmation of a Ru top contact on a multilayer WSe₂ channel (right). Bottom row: schematic comparison of the baseline top-gate stack comprising interlayer, cap, and top-up oxides; full replacement-oxide process; and selective lateral interlayer removal from contact trenches. Based on Paper 10.1, “Selective Etch Process for Fab-Compatible Top Contacts, Replacement Oxide and Interlayer Removal in 2D FETs,” Q. Smets et al., presented at IEDM.

In parallel with its 2D transistor research, Intel Foundry has made significant progress in High Numerical Aperture EUV lithography as a cornerstone enabler for future device scaling. In close collaboration with ASML, Intel Foundry has completed acceptance testing of the TWINSCAN EXE:5200B, the most advanced High NA EUV scanner currently available. This system builds on the first-generation EXE:5000 platform while extending productivity to 175 wafers per hour and achieving overlay performance of 0.7 nm, metrics that are directly relevant to high-volume manufacturing rather than purely experimental use. Intel’s early access to High NA EUV, beginning with the first commercial installation in its Oregon R&D fab in 2023, positions the company as a lead development partner shaping how High NA lithography is qualified, integrated, and eventually deployed in production logic nodes.

From a technology perspective, the EXE:5200B introduces several enabling innovations that are critical for advanced transistor architectures, including gate-all-around and future stacked devices. A higher-power EUV source supports practical exposure doses and improved resist process windows, helping control line edge and line width roughness at extremely small critical dimensions. A redesigned wafer stocker architecture improves lot logistics and thermal stability, which is especially important for multipass and multiexposure flows anticipated with High NA patterning. Finally, tighter alignment control reflects advances in stage mechanics, sensing, and environmental isolation, all of which become essential as overlay tolerances approach the sub-nanometer regime. For Intel Foundry customers, these capabilities translate into more flexible design rules, reduced reliance on complex multi-patterning schemes, fewer masks and process steps, and faster yield learning. Together, Intel’s High NA EUV progress and its 2D transistor integration work reflect a coherent strategy: pairing next-generation lithography with manufacturable device innovations to ensure that future scaling paths are both technically viable and production-ready.

Sources:

How Collaboration in High NA EUV and Transistor R&D Are Shaping Future Waves of Device Innovation

IEEE IEDM 2025 | 10-1 | Selective Etch Process for Fab-compatible Top Contacts, Replacement Oxide and Interlayer Removal in 2D FETs

Nanexa and Moderna partner on ALD-based PharmaShell drug delivery platform in licensing deal with USD 3 million upfront payment

Nanexa and Moderna have entered into a license and option agreement covering the development of up to five undisclosed drug compounds using Nanexa’s PharmaShell® drug delivery platform. The agreement includes an upfront payment of USD 3 million to Nanexa, with the potential for up to USD 500 million in development and commercial milestone payments, as well as tiered single-digit royalties on future product sales. Moderna receives an immediate license for the first selected compound and holds options to license up to four additional compounds following preclinical evaluation.

“We are excited to partner with Moderna, a pioneer and leader in the field of mRNA medicines, to explore the potential of our PharmaShell® platform and to support the development of improved products for Moderna,” said David Westberg, CEO of Nanexa. “This agreement underscores the versatility of PharmaShell and its potential to address key challenges in the delivery of advanced biologics.”

The collaboration focuses on evaluating PharmaShell®’s ability to improve release profiles and stability for Moderna’s compounds. PharmaShell® is based on atomic layer deposition (ALD) technology, enabling precise encapsulation of active pharmaceutical ingredients with controlled, long-acting release characteristics. The agreement highlights PharmaShell®’s applicability to advanced biologics and supports Nanexa’s strategy of combining internal development with partnerships and licensing to global pharmaceutical companies.

Background on ALD and PharmaShell

Atomic Layer Deposition (ALD) is a thin-film deposition technique originally developed for the semiconductor industry, where it is used to create extremely uniform, conformal, and precisely controlled coatings at the atomic scale. ALD is based on sequential, self-limiting surface reactions, which allow film thickness and composition to be controlled with angstrom-level precision. Because the process produces highly uniform coatings even on complex, high–surface-area structures, ALD has increasingly been adopted in life sciences and pharmaceutical applications where consistency, stability, and reproducibility are critical.

PharmaShell® is Nanexa’s proprietary drug delivery technology that applies ALD to pharmaceuticals by encapsulating active pharmaceutical ingredients with an ultrathin, inorganic coating. This coating acts as a controlled diffusion barrier, enabling precisely tuned and long-acting release profiles while also improving product stability and protection of sensitive molecules. By adjusting coating thickness and material properties at the atomic level, PharmaShell® can be tailored to specific drugs and therapeutic needs, making it particularly well suited for advanced biologics and long-acting injectable formulations.

PharmaShell® is administered as a suspended injectable formulation containing API particles coated with an ultrathin ALD-based shell. After injection, the coating gradually dissolves in vivo, enabling controlled and sustained release of the active pharmaceutical ingredient into systemic circulation. The coating materials break down into ions that are naturally eliminated via urine and feces, allowing long-acting drug delivery using thin-gauge needles and low injection volumes.

PharmaShell® is created by applying ultrathin inorganic oxide coatings to API particles using atomic layer deposition (ALD). ALD is a gentle, gas-phase process operating under dry conditions near room temperature, making it suitable for sensitive molecules such as peptides and monoclonal antibodies. The nanometer-scale coating provides precise control of drug release while maintaining a very high drug load, with no need for post-process purification.

About Nanexa

Nanexa AB (publ) is a Swedish drug delivery company specializing in long-acting injectable formulations. Its proprietary PharmaShell® technology uses atomic layer deposition to precisely encapsulate drug substances, enabling tailored release profiles, improved stability, and potentially reduced dosing frequency.

About Moderna

Moderna, Inc. (Nasdaq: MRNA) is a biotechnology company known for pioneering mRNA-based medicines and vaccines. The company focuses on developing therapeutics and vaccines across infectious diseases, oncology, rare diseases, and immune-mediated conditions using its mRNA platform.

Sources:

Nanexa AB - Nanexa and Moderna enter into license and option agreement for the development of PharmaShell®-based products

PODD-Oct-2025.pdf

Capacitive memory built on a TSMC CMOS chip (reported in Nature)

Researchers led by Junmo Lee from Georgia Institute of Technology in collaboration with Taiwan Semiconductor Manufacturing Company (TSMC) have demonstrated a new type of capacitive memory integrated directly on a CMOS chip. The work uses atomic layer deposition (ALD) and a dual-gated device architecture, pointing toward higher-density, low-power memory that can be integrated into advanced logic processes

Junmo Lee and colleagues now report a dual-gated non-volatile capacitive memory fabricated on the top metal layer of a foundry CMOS chip. The fabrication process begins with the removal of the chip’s passivation layer, followed by the deposition and patterning of the bottom electrode and interconnects. A layer of hafnium zirconium oxide (HZO) is then deposited using a tungsten sacrificial layer, and a film of tungsten-doped indium oxide (In2O3) grown via atomic layer deposition. The process concludes with the formation of a palladium top electrode and back-end pads, followed by a hafnium oxide (HfO2) top dielectric and then a palladium top gate.

The device exhibits a capacitive on/off ratio of 63.1, endurance exceeding 109 cycles at a read voltage of 1 V and retention of above 104 s at 25 °C. The operational principle of the integrated two-transistor–one-capacitor (2T–1C) device was validated by demonstrating the current amplification behaviour of the capacitance-modulated 40-nm silicon transistor within the integrated structure. Based on the measured data, the researchers proposed and simulated a cell-level digital compute-in-memory circuit model.

The study was also presented at IEDM2025: Technical Highlight – Monolithic 3D Capacitive Memory for Compute-in-Memory: 

This joint work by Georgia Tech & TSMC, nominated for Best Student Paper in Emerging Device Technology, describes the first monolithic 3D (M3D) integration of dual-gated non-volatile capacitive memory (nvCAP) with an ALD W-doped In₂O₃ channel on a TSMC foundry 40nm CMOS chip. The novel dual-gate design resolves the long-standing challenges of weak erase and poor retention in oxide-channel ferroelectrics, achieving a record non-destructive on/off ratio of ~64.4 at 0V on a foundry CMOS chip. In addition, the paper introduces a new capacitive digital compute-in-memory (Cap-DCIM) paradigm, showing >140x efficiency improvements versus analog CIMs and >100x lower static power than SRAM-based CIMs, pointing to a scalable and energy-efficient path for future memory-compute integration. The operational principle of M3D Cap-DCIM is experimentally validated by demonstrating BEOL capacitance-modulated FEOL transistor current amplification through the monolithically integrated DG nvCAPs on a foundry CMOS chip.

Paper 28.3, “Monolithic 3D Integration of Dual-Gated ALD Oxide-Channel Non-Volatile Capacitive Memory on 40nm Si CMOS for Digital Compute-in-Memory,” J. Lee et al, Georgia Tech

Source: 

Capacitive memory built on a CMOS chip | Nature Electronics

IEEE IEDM 2025 | 28-3 | Monolithic 3D Integration of Dual-Gated ALD Oxide-Channel Non-Volatile Capacitive Memory on 40nm Si CMOS for Digital Compute-in-Memory