ASM Charts the Future of ALD: Scaling Innovation, Integration, and Intelligence Toward 2030

ASM used its 2025 Investor Day to set a bold 2030 ambition of more than €5.7 billion revenue, operating margins above 30%, and free cash flow above €1 billion. The company has consolidated a leading position in ALD with over 55% market share in their segments they where they chose to compete and is scaling its Epi business from 12% in 2020 to 25% in 2024. ALD remains the central growth driver, with the market for single-wafer ALD expected to outpace overall wafer fab equipment and reach $5.1–6.1 billion by 2030, while Si Epi is forecast at $2.5–3.2 billion with a 9–13% CAGR. 

The single-wafer ALD market is projected to grow strongly from about 3.0 billion dollars in 2024 to between 5.1 and 6.1 billion dollars by 2030, representing a 9–13 percent compound annual growth rate, outpacing the overall wafer fab equipment market, which is expected to grow at 6 percent annually from 110 billion dollars in 2024 to 155 billion dollars in 2030. This growth is driven by the increasing number of ALD layers required in leading-edge logic and foundry processes as well as in advanced DRAM, both in the cell and peripheral CMOS areas. By 2030, ASM aims to maintain a market share above 55 percent, sustaining its lead in logic and foundry while also expanding its position in memory.

Node and memory inflections significantly expand ASM’s served markets, adding $400 million in their served available market from 3nm FinFET to 2nm GAA, and a further $450–500 million from 2nm to 1.4nm, while DRAM transitions contribute another $400–450 million. FEOL ALD layers grow fastest, with roughly 60% of ALD demand at 1.4nm coming from the transistor front end. In advanced packaging, a total available market of $11.5 billion by 2030 supports ASM’s plan to double its served available market to more than 30% of that market. 

Services are projected to grow at more than 12% CAGR through 2030, with half of revenues moving to outcome-based models and new “dry clean” refurbish technology delivering ~10× selectivity, ~5× part life, over 95% CO₂e reduction, and more than 2× cost-of-ownership benefits. 

ASM also introduced its XP8E common platform integrating clean, treat, inhibit, and ALD steps for 2nm ASD flows, and highlighted AI/ML deployment in high-volume manufacturing for anomaly detection, predictive maintenance, and improved first-time-right performance.

ASM’s XP8E common platform is positioned as a key enabler for the 2nm and beyond era, where Area-Selective Deposition and advanced integration schemes require multiple tightly coupled process steps. By bringing clean, treat, inhibit, and ALD into a single cluster, XP8E reduces wafer handling, shortens cycle times, and improves process control. This integration is critical for scaling as the number of ALD steps grows with each node, and it directly addresses challenges in pattern fidelity, defectivity, and variability that can otherwise undermine yield at 2nm. The platform is designed to be modular and flexible, so customers can configure it for different ASD and high-k/metal gate flows, while also benefiting from a common hardware base that simplifies fab operations, service, and parts management.

Alongside new hardware, ASM is embedding AI and machine learning capabilities into high-volume manufacturing. These tools enable real-time anomaly detection to flag subtle deviations in process behavior before they impact yield, and provide “top contributor” insights that help engineers rapidly identify root causes. Predictive maintenance, including ASM’s PM-Bot automation, improves precision and ensures higher first-time-right rates, cutting downtime and labor intensity. Over time, this creates a closed-loop system where data from thousands of wafers continuously refines process windows, stabilizes tool performance, and enhances cost-of-ownership. In combination, XP8E’s process integration and AI-driven control systems aim to deliver the repeatability, selectivity, and productivity gains required for the 2nm transition and future GAA nodes.

ASMs ALD History - from 1974 to 2024, 50+ years of ALD

The timeline highlights key milestones in the history of ALD and ASM’s leadership in the field. It begins in 1974 with Dr. Tuomo Suntola’s invention of ALD, followed by the founding of Microchemistry in Helsinki in 1987. ASM entered the scene in 1998 with the release of its first 200 mm Pulsar tool and strengthened its position by acquiring Microchemistry from Neste in 1999 and securing Sherman PEALD patents in 2000. Growth continued with the acquisition of Genitech in 2004. In 2008, ASM’s Pulsar tool was recognized as Product of the Year, cementing its reputation. More recently, ASM expanded its product portfolio with the introduction of the dual-chamber Synergis ALD system in 2018, the XP8 quad chamber module in 2019, and the Prominis ALD and XP8E platform in 2024. Strategic acquisitions, such as Reno Sub-Systems in 2022, further enhanced ASM’s technology base, illustrating a steady path of innovation and consolidation in ALD leadership over five decades.

The timeline illustrates ASM’s journey in atomic layer deposition from its origins to modern platforms. ALD was invented by Dr. Tuomo Suntola in 1974, followed by the founding of Microchemistry in 1987. ASM entered the field with the release of its first 200 mm Pulsar tool in 1998, strengthened its position by acquiring Microchemistry from Neste in 1999 (Finland), and expanded its patent base with Sherman PEALD patents in 2000. Key milestones include the acquisition of Genitech (Korea) in 2004, industry recognition for Pulsar in 2008, the introduction of Synergis in 2018 and XP8 in 2019, and the acquisition of Reno Sub-Systems in 2022. Most recently, ASM launched the Prominis ALD and XP8E platform in 2024, underscoring more than 50 years of continuous innovation and leadership in ALD.

The Finnish angle in ASM’s ALD story is both historic and ongoing. Atomic Layer Deposition was invented in Finland in 1974 by Dr. Tuomo Suntola, originally called Atomic Layer Epitaxy. The technology was developed at Microchemistry Ltd., a Finnish company founded in Helsinki in 1987 under Neste. When ASM acquired Microchemistry in 1999, they started gaining the pioneering ALD patents, know-how, and expertise that underpin its leadership today. Finland continues to play an active role through the University of Helsinki and ASM’s Chemical Innovation Group in Helsinki, where precursor chemistry and process research are carried out in close collaboration with Finnish scientists. In this way, Finland provided both the origin of ALD for ASM and remains an important innovation hub supporting ASM’s growth and leadership.

The ASM Pulsar “HIG source” for solids (or the solid precursor delivery subsystem) is a core enabler for ASM’s ability to use low-vapor-pressure solid precursors in ALD. The original innovation from ASM Microchemistry has been further developed over decades and is now still a key technology on the new platform for Molybdenum ALD seen below. It involves a heated sublimation mechanism (sometimes mounted close to or integrated with the reactor), controlled inert gas valves, purge isolation, and precise flux control to feed vapor from a solid into the ALD chamber. The architecture seeks to avoid cold spots or condensation and maintain consistent, controllable precursor delivery pulses.

Genitech was a South Korean company specializing in plasma enhanced ALD and thin film deposition. ASM acquired the company in 2004 to expand its capabilities in plasma based processes and complement its existing thermal ALD portfolio. The acquisition gave ASM a stronger position in PEALD for applications such as high k dielectrics and metal gate stacks used in advanced logic and memory. Genitech’s technology was integrated into ASM’s Pulsar and subsequent platforms, helping establish ASM’s leadership in both thermal and plasma ALD.

ASM acquired Reno Sub-Systems in 2022. Reno is a US-based company specializing in RF power delivery systems and matching networks for plasma tools. Their solid-state RF technology is valued for faster response times, higher precision, and better process stability compared to legacy RF solutions. By integrating Reno’s subsystems into its platforms, ASM strengthened its capability in plasma-based ALD and PEALD, where fine RF control is critical for uniformity, repeatability, and advanced film properties.

Future Outlook

ASM ties its deposition processing capability to its tool portfolio—Pulsar, EmerALD, Synergis, Prominis, XP8E, and others—which are engineered with small-volume reactors, advanced plasma control, and integrated multi-step clustering (clean, treat, inhibit, deposit).

Looking ahead, ASM is uniquely positioned to remain the clear leader in atomic layer deposition as the semiconductor industry advances to 2nm and beyond. The company’s deep history in ALD, dating back to Dr. Tuomo Suntola’s invention in 1974, has evolved into a robust technology portfolio that now commands more than 55 percent market share where ASM chooses to compete. 

With single-wafer ALD forecast to nearly double in size by 2030 and outpace overall wafer fab equipment growth, ASM is set to capture outsized value from both logic and memory inflections. Its proven expertise in solid source precursor delivery, trailing back to the the Pulsar HIG sublimation system and F120 Microchemistry research reactors, now expands to new material capabilities such as molybdenum ALD for advanced node metallization. At the same time, ASM is broadening its impact through the XP8E common platform, which integrates multiple critical steps into one cluster with embedded AI and machine learning into high-volume manufacturing for real-time control. ASM’s combination of process innovation, equipment integration, and data-driven intelligence places the company at the center of semiconductor scaling, ensuring its leadership in enabling Moore’s Law through the next decade.

Sources:

ASM InvestorDay 2025

JSR, Lam Research, and SK hynix Push the Boundaries of ASML´s EUV Semiconductor Manufacturing

JSR Corporation, including its subsidiary Inpria Corporation, and Lam Research have entered into a cross-licensing and collaboration agreement to accelerate the development of next-generation semiconductor manufacturing technologies. The partnership combines JSR’s expertise in photoresists and advanced materials—anchored by Inpria’s metal-oxide resists (MORs) for extreme ultraviolet (EUV) lithography—with Lam’s leadership in wafer fabrication equipment and process technology. By sharing intellectual property and integrating complementary capabilities, the companies aim to address scaling and patterning challenges as chipmakers pursue smaller, denser, and more energy-efficient devices for advanced logic and memory applications.

Inpria’s MORs, based on spin-on tin-oxide materials, provide high EUV photon absorption, excellent etch resistance, and reduced line edge roughness compared with conventional organic resists. These materials are fully compatible with existing lithography systems, making them attractive for high-volume production. To meet growing demand, JSR is expanding its global footprint with new R&D facilities in Japan and a production plant in Korea set to begin operations in 2026. Lam Research complements this with its Aether® dry resist technology, which replaces wet spin-coating and development with fully dry, vapor-phase processes. This innovation improves uniformity, reduces stochastic defects, and strengthens EUV absorption, enabling higher resolution and sensitivity. Aether has demonstrated direct-print 28 nm pitch patterning for logic and is already being adopted by leading memory manufacturers, offering both performance advantages and sustainability gains through reduced chemical and energy use.

These advances align with a broader industry shift toward tighter integration of materials and equipment solutions, exemplified by SK hynix’s installation of the world’s first commercial High-NA EUV lithography tool, ASML’s TWINSCAN EXE:5200B, at its M16 fab in Icheon, South Korea. Featuring a numerical aperture of 0.55—compared with 0.33 in current Low-NA EUV systems—the High-NA platform boosts resolution by 40%, enabling transistors about 1.7× smaller and wafer transistor densities nearly 2.9× higher. For SK hynix, this milestone supports the development of next-generation DRAM, reduces process complexity, lowers costs, and strengthens competitiveness in AI memory and advanced compute markets.

As one of the “big three” memory makers alongside Samsung and Micron, SK hynix has established itself as the leader in high-volume DRAM manufacturing. It was the first to mass-produce DDR5 and high-bandwidth memory (HBM3), both essential for AI and high-performance computing. Its early adoption of EUV lithography for DRAM production—and now the industry-first deployment of ASML’s High-NA EUV system—underscores its position at the forefront of DRAM scaling and density. Together, the innovations from JSR, Inpria, Lam Research, and SK hynix illustrate how collaboration across the semiconductor ecosystem is driving the breakthroughs required to sustain Moore’s Law in the era of AI and advanced computing.

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Do you want me to keep the headline-style opening as above, or make it read more like a press release introduction with a formal lead sentence?

Sources:

JSR Corporation/Inpria Corporation and Lam Research Enter Cross Licensing and Collaboration Agreement to Advance Semiconductor Manufacturing

Dry Resist Patterning Progress and Readiness Towards High NA EUV Lithography

INPRIA | A world leader world leader in metal oxide photoresist design, development and manufacturing

Inpria Co-Developing Metal Oxide Resist with SK hynix to Reduce Complexity of Patterning for Next-Generation DRAM | 2022 | News | JSR Corporation

SK hynix Introduces Industry’s First Commercial High NA EUV

Breaking the Copper Bottleneck: Lam Research’s Mo-ALD ALTUS Halo Enables Next-Generation Hybrid Metallization

Lam Research now offers molybdenum (Mo) atomic layer deposition (ALD) with its ALTUS Halo platform, introduced in 2025 as the first high-volume ALD tool designed for Mo metallization. The system enables conformal and selective, bottom-up deposition of low-resistivity, void-free Mo films, targeting advanced logic, memory, and 3D NAND applications where conventional copper and tungsten interconnects face scaling and reliability limits. This positions Lam’s Mo-ALD as a key enabler for next-generation BEOL hybrid metallization schemes.

Current density of various metal/via schemes. Red and green areas indicate higher current density.  

Hybrid metallization using Mo shows strong potential to overcome the scaling limitations of conventional copper dual damascene (Cu DD) processes in advanced semiconductor BEOL interconnects. As device dimensions shrink, Cu faces challenges such as increased resistivity, barrier thickness limitations, and stress-induced voids (SIVs), all of which degrade performance. Mo hybrid metallization, which uses bottom-up barrierless metal deposition before a conventional Cu process, significantly reduces resistance—by about 55% compared to Cu DD—and further by 15% with selective barrier deposition (SBD). This lower resistance translates into higher current densities and improved reliability. Stress distribution studies also reveal that Mo hybrid vias exhibit lower void formation risks than Cu due to smaller stress gradients at the via/barrier interfaces.

Comparison of via and line resistance for conventional Cu dual damascene and Mo hybrid metallization schemes. Mo vias reduce total resistance by ~35% without selective barrier deposition (SBD), with an additional ~20% reduction when fully replacing Cu. Applying SBD further lowers resistance, achieving up to ~55% reduction compared to the Cu baseline.

Optimization studies, performed with SEMulator3D® simulations, identified key parameters like via critical dimensions, height, and material stress properties that impact resistance, capacitance, and hydrostatic stress. Findings show that increasing Mo via height lowers resistance but raises stress, suggesting an optimal fill height around 25 nm for balancing performance and reliability. Intrinsic stress of Mo and process temperature tuning were also shown to mitigate stress-induced reliability issues, with 400°C identified as a favorable condition. Ultimately, hybrid metallization with Mo offers a scalable path forward, combining electrical and mechanical benefits, while virtual DOE and process modeling enable predictive optimization without extensive wafer-based experiments.

Sources:

Breaking the Copper Bottleneck With Molybdenum Hybrid Metallization

Lam Research Ushers in New Era of Semiconductor Metallization with ALTUS® Halo for Molybdenum Atomic Layer Deposition - Feb 19, 2025

ALD News Week 38

Solid-state batteries get a boost with new protective coating

Link: https://www.anl.gov/article/solidstate-batteries-get-a-boost-with-new-protective-coating

“A thin, glass-like layer could help protect solid-state batteries from degradation, researchers say. They use a process called atomic layer deposition (ALD) to apply a protective layer.” (ANL)

Microwave enhanced atomic layer deposition (MW-ALD): Incorporating a microwave antenna into an ALD reactor
Link: https://pubs.aip.org/avs/jva/article/43/5/052403/3361679/Microwave-enhanced-atomic-layer-deposition-MW-ALD

“Atomic layer deposition (ALD) is a technique widely used for thin film deposition with excellent uniformity and conformality. In this work, we present a modification of a conventional ALD system by integrating a microwave antenna to explore how microwave energy can enhance film growth and reduce cycle times, particularly for materials that are otherwise difficult to deposit.” (AIP Publishing)

Impacts of different thickness Al2O3 and SiO2 atomic layer deposition sidewall passivation layers on GaN-based devices
Link: https://pubs.aip.org/avs/jvb/article/43/5/052209/3361926/Impacts-of-different-thickness-Al2O3-and-SiO2-atomic-layer-deposition-sidewall
 
“The sidewall passivation layer has a critical effect on the performance and reliability of GaN-based devices. In this study, we investigate how varying the thickness of atomic layer deposition (ALD) Al₂O₃ and SiO₂ sidewall passivation layers influences device leakage, breakdown voltage, and surface recombination. The results show that thicker layers can better suppress leakage but may lead to trade-offs in other device parameters.” (AIP Publishing)

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Forge Nano to Unveil Commercial Single Module Semiconductor Wafer Fab ALD Tool at SEMICON Taiwan
Link: https://www.globenewswire.com/news-release/2025/09/04/3144564/0/en/Forge-Nano-to-Unveil-Commercial-Single-Module-Semiconductor-Wafer-Fab-ALD-Tool-at-SEMICON-Taiwan.html

DENVER, Sept. 04, 2025 (GLOBE NEWSWIRE) -- Forge Nano, Inc., a technology company pioneering domestic battery and semiconductor innovations, today announced it is unveiling a new commercial single module semiconductor wafer fab atomic layer deposition (ALD) tool – TEPHRA^{One}. The fully automated 200 mm single module platform is outfitted with features from Forge Nano’s flagship multi-process module TEPHRA in a streamlined configuration for oxide, nitride, metal and nanolaminate coatings. (GlobeNewswire)

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New Tool Announcement: Thermal/Plasma ALD System Now Available for User Access
Link: https://nanofab.ucsd.edu/new-tool-announcement_thermal-plasma-ald-system/

We are happy to announce that the new Arradiance GEMStar Thermal & Plasma ALD (Atomic Layer Deposition) System is now available for user access. This advanced system supports both thermal and plasma enhanced ALD processes and is designed to allow users to explore a wide range of thin film materials and process conditions. (nanofab.ucsd.edu)

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Press Release “ALD for Industry 2025” - Dresden
Link: https://efds.org/en/45604/

Dresden, March 12, 2025 – The 8th International Conference “ALD FOR INDUSTRY” has once again bridged the gap between basic research, industrialization and commercialization of atomic layer deposition (ALD). This event, which has been held annually in Dresden since 2017, once again welcomed over 100 participants from 14 countries and numerous exhibitors this year despite the strike at German airports. (efds.org)

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News & Announcements: Continuous, high-speed atomic layer deposition for thin-film coatings
Link: https://www.anl.gov/amd/news-announcements

“Self-exhausting” precursor pulses enable fast, precise coating applications for … (ANL)

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Global Semiconductor Sales Surge 20.6% in July, Driven by Americas and Asia Pacific

Global semiconductor sales surged in July 2025, reaching $62.1 billion — a 20.6% increase from the same month last year and 3.6% higher than June. The robust expansion was fueled by strong demand in the Americas and Asia Pacific, underscoring the industry’s momentum despite regional fluctuations. With the Americas up nearly 30% and Asia Pacific/All Other climbing over 35% year-on-year, July marked one of the strongest months of growth in recent years, highlighting continued strength in advanced computing, AI, and data-driven technologies.

• The Americas and Asia Pacific regions are the strongest contributors to both monthly and yearly growth.
• China is still growing year-to-year but slipped month-to-month, suggesting softer short-term demand.
• Japan is contracting in both comparisons, signaling structural weakness.
• Europe remains modest but positive year-to-year.

Global Overview

• Total sales: $62.07B
• Year-to-year growth: +20.6% (vs. $51.48B in July 2024)
• Month-to-month growth: +3.6% (vs. $59.91B in June 2025)
• Three-month-moving average growth: +8.9%

Regional Breakdown (Year-to-Year, July 2025 vs. July 2024)

• Asia Pacific/All Other: +35.6% (biggest growth driver)
• Americas: +29.3%
• China: +10.4%
• Europe: +5.7%
• Japan: -6.3% (only region in decline)

Month-to-Month (July vs. June 2025)

• Americas: +8.6%
• Asia Pacific/All Other: +4.9%
• Europe: 0.0%
• Japan: -0.2%
• China: -1.3%

Source:

Global Semiconductor Sales Increase 20.6% Year-to-Year in July - Semiconductor Industry Association

EU Expands Dual-Use Export Controls to Cover Atomic Layer Deposition, Etch, Epitaxy, Lithography, EUV Components and Quantum Technologies

On 8 September 2025, the European Commission adopted a Delegated Regulation updating the EU’s dual-use export control list (Annex I of Regulation (EU) 2021/821). The update aligns EU rules with commitments made in 2024 under the Wassenaar Arrangement, MTCR, Australia Group, and the Nuclear Suppliers Group, ensuring a uniform application of newly agreed controls across all Member States. The move reflects the EU’s broader strategy outlined in the 2024 White Paper on Export Controls, strengthening oversight of sensitive technologies while maintaining competitiveness and a level playing field for European industry.

The updated list introduces new controls on a range of emerging technologies. These include quantum technologies such as cryogenic components and amplifiers, advanced semiconductor manufacturing and testing equipment — notably Atomic Layer Deposition tools, epitaxial deposition systems, and EUV lithography materials — as well as high-performance computing circuits, additive manufacturing systems, peptide synthesisers, and specialized high-temperature coatings. The Delegated Regulation will enter into force following the standard two-month scrutiny period by the European Parliament and Council, reinforcing the EU’s role in safeguarding security and international stability through effective export controls.

Specifically, this update of the EU control list provides for the addition of new dual-use items, including: 

• Controls related to quantum technology (e.g. quantum computers, electronic components designed to work at cryogenic temperatures, parametric signal amplifiers, cryogenic cooling systems, cryogenic wafer probers);
• Semiconductor manufacturing and testing equipment and materials (e.g. Atomic Layer Deposition equipment, equipment and materials for epitaxial deposition, lithography equipment, Extreme Ultra-Violet pellicles, masks and reticles, Scanning Electron Microscope equipment, etching equipment);
• Advanced computing integrated circuits and electronic assemblies such as Field Programmable Logic Devices and Systems;
• Coatings for high temperature applications;
• Additive manufacturing machines and related materials (e.g. inoculants for powders);
• Peptide synthesisers, and;
• Modification of certain control parameters and update of certain technical definitions and descriptions.

By extending controls to core process equipment essential for leading-edge semiconductor production, the EU aims to close regulatory gaps and ensure uniform oversight across all Member States. For the semiconductor industry, this means that exports of critical manufacturing tools and materials outside the Union will now require authorisation, tightening compliance requirements but also ensuring fair competition and transparency within the internal market. The regulation highlights the EU’s growing focus on safeguarding supply chains for advanced chip technologies while balancing competitiveness with security concerns

For more information
Delegated Regulation
Comprehensive Change Note Summary – Update 2025: An overview of changes to the EU Dual-Use Control List across the 10 categories of Annex I

TSMC’s 2 nm Fabs Lock Out China OEMs, Securing ALD and Process Tool Demand for US, European, and Japanese Tier-1 Suppliers

TSMC’s decision to exclude Chinese equipment vendors from its 2 nm fabs in Taiwan and the US reshapes the competitive landscape in favor of Japanese, American, and European suppliers. With the 2 nm node set to become the largest in history by wafer volume and revenue potential, this policy shift effectively concentrates demand among a handful of Tier 1 players —ASMI, TEL, Applied Materials, and Lam Research—who already dominate in deposition, etch, and cleaning tools essential for nanosheet GAA and backside power delivery. No need to mention ASML.

Announced in January: TSMC is advancing with its 2 nm (N2) technology, establishing a pilot line at its Hsinchu Baoshan Fab 20 with an initial monthly output of around 3,000–3,500 wafers. By combining production from Hsinchu and Kaohsiung, the company expects to exceed 50,000 wafers per month by the end of 2025 and reach about 125,000 wafers per month by the end of 2026. Output at Hsinchu should rise to 20,000–25,000 wafers per month by late 2025 and 60,000–65,000 by early 2027, while Kaohsiung is projected to produce 25,000–30,000 wafers monthly by late 2025 and also expand to 60,000–65,000 by early 2027. Chairman C.C. Wei has highlighted that demand for 2 nm exceeds that of 3 nm, driven by its 24–35% lower power consumption, 15% performance boost at the same power, and 15% higher transistor density. Apple will be the first adopter, followed by MediaTek, Qualcomm, Intel, NVIDIA, AMD and Broadcom.

TSMC will start 2 nm mass production in Taiwan in the second half of 2025, initially with Fab 22 in Kaohsiung as the anchor site for yield learning. The first ramp is set at 40,000 wafers per month, expanding to 100,000 wafers per month in 2026 and reaching 200,000 wafers per month by 2027, making N2 the largest and most profitable node in TSMC’s history.

In the US, Arizona Fab 21 is being developed in phases. Phase 1 is already producing 4 nm chips, Phase 2 will start 3 nm by late 2025 or early 2026, and Phase 3 is planned for 2 nm and A16-class chips toward the end of the decade. This ensures that while Taiwan remains the cost-optimized base for N2 production, Arizona provides premium, subsidy-supported capacity for US customers, diversifying geographic and geopolitical risk.

Overall, Taiwan will carry the bulk of N2 output and cost efficiency, while Arizona secures local supply for strategic US clients like Apple, Nvidia, AMD, and Intel. By 2027, with 200,000 wafers per month globally, N2 alone could generate nearly $50 billion annually, cementing TSMC’s central role in powering AI and HPC expansion.

The move aligns directly with Washington’s Chip EQUIP Act, which ties subsidies to avoiding “foreign entities of concern.” By pre-emptively removing Chinese tools, TSMC safeguards its access to US incentives while giving its global customers—Apple, Nvidia, AMD, and Intel—assurance that supply chains are insulated from geopolitical risk. This codifies the leading suppliers as the “trusted” baseline for advanced-node capacity worldwide, effectively reinforcing their moat at the most profitable process node ever.

For ASMI, TEL, AMAT, and Lam, the outlook is very positive. With Chinese competitors pushed out, these companies can win more business and have stronger pricing power. At the same time, 2 nm wafer prices are climbing toward $30,000, far above older smartphone-focused nodes. TSMC is reviewing its suppliers for profit margins and China ties, but these four are essential for 2 nm production, so they are more likely to gain from rising demand and higher-value tools than lose ground. Put simply, the 2 nm era is set to drive lasting growth and profits for them as AI adoption accelerates through 2027.

Chinese semiconductor equipment OEMs that are cut out from TSMC’s 2 nm fabs under the new restrictions and supplier realignment:

• AMEC (Advanced Micro-Fabrication Equipment Inc.) – leading Chinese etch tool supplier, with relevance in dielectric etch and epitaxy
• Naura Technology Group – broad portfolio in etch, deposition, and cleaning tools
• Mattson Technology (China-owned, via E-Town Dragon Semiconductor) – focuses on dry strip, rapid thermal processing (RTP), and etch
• SMEE (Shanghai Micro Electronics Equipment) – China’s only domestic lithography tool maker (far behind in capability, but relevant in domestic fabs)
• Kingsemi – maker of ALD/CVD equipment, mainly for memory and advanced logic
• Piotech – deposition (CVD, PECVD, ALD) equipment vendor
• ACM Research (China) – cleaning and electrochemical deposition tools (though headquartered in the US, its operations are China-based and increasingly seen as China OEM)

At TSMC’s 2 nm fabs, the exclusion of Chinese equipment vendors channels ALD equipment demand entirely to US, European, and Japanese suppliers. ASM International (Europe) remains the clear leader in single-wafer ALD for high-k metal gate stacks and nanosheet spacers, with Applied Materials and Lam Research (US) competing in selective and plasma ALD for gate-all-around and backside power steps, while Tokyo Electron and Kokusai Electric (Japan) cover both single-wafer and batch ALD, particularly for spacer and liner deposition. By contrast, Chinese ALD players such as Naura, Kingsemi, and Piotech, while active in domestic logic and memory at 28–14 nm and some 7 nm non-EUV capacity, will not gain any capability at N2 and are explicitly excluded under TSMC’s supplier policy and US subsidy rules, leaving the largest and most profitable ALD opportunity in history to be divided among the established US, European, and Japanese Tier-1 suppliers.

Sources:

TSMC reportedly cuts Chinese chipmaking tools from 2nm fabs as suppliers face scrutiny due to emerging new US restrictions | Tom's Hardware

https://open.substack.com/pub/drrobertcastellano/p/tsmcs-2-nm-era-technology-leadership?r=l0uj0&utm_campaign=post&utm_medium=web&showWelcomeOnShare=false

TSMC Is Getting Ready to Launch Its First 2nm Production Line | TechPowerUp