Saturday, March 22, 2014

Samsung: A modified double patterning using ALD allows for continued scaling of DRAM for 10nm class technology

Samsung reports that they are  now mass producing industry’s most advanced 4Gb DDR3, using 20 nanometer process technology:

"Samsung has pushed the envelope of DRAM scaling, while utilizing currently available immersion ArF lithography, in its roll-out of the industry’s most advanced 20-nanometer (nm) 4-gigabit (Gb) DDR3 DRAM."

"With DRAM memory, where each cell consists of a capacitor and a transistor linked to one another, scaling is more difficult than with NAND Flash memory in which a cell only needs a transistor. To continue scaling for more advanced DRAM, Samsung refined its design and manufacturing technologies and came up with a modified double patterning and atomic layer deposition."

"Samsung’s modified double patterning technology marks a new milestone, by enabling 20nm DDR3 production using current photolithography equipment and establishing the core technology for the next generation of 10nm-class DRAM production. Samsung also successfully created ultrathin dielectric layers of cell capacitors with an unprecedented uniformity, which has resulted in higher cell performance."

Here is a folow up blog post from the Samsung Blog: So…About Samsung Mass Producing the Most Advanced 20nm DDR3 DRAM explaining why the dielectric layers (high-k) in the DRAM capacitor memory cell need to be a ‘ultrathin dielectric layer’ for the 20nm DDR3 DRAM compared to the 25 nm cell.

"Why are the 20nm DDR3 DRAM’s dielectric layers ultrathin rather than ultra-thick? Because the thicker the dielectric layers are, the fewer electrical charges are stored in the cell’s transistors; there is simply less room for them. Then how is it that Samsung 20nm DDR3 DRAM’s ultrathin layers are effective?

The material used in the 20nm DDR3 DRAM is measured in Angstrom (Å), a unit of length equal to 10−10 m, basically the size of an atom. The ultrathin dielectric layers of Samsung are composed of atomic materials, aka atomic layer deposition. This is why the amount of electric charges stored in the capacitor of the 20nm DDR DRAM doesn’t change much, in a significantly scale downed cell. Overall, the quality of the each cell of Samsung’s 20nm DDR DRAM is superior to the preceding 25nm DDR3 DRAM. Consequently, 20nm DDR3 DRAM’s superior cells enable high-speed operation, which is the most important characteristic of a DRAM, and low power consumption. Making the dielectric layers of the 20nm capacitor much denser and thinner than the 25nm capacitor was one of the keys to the successful development and now mass producing Samsung’s new 20nm 4G DDR3."

From a Chipworks report abstract that can be bought here, we can see a cross section of the stack capacitor array Samsung is using at 26 nm (see below). For 20 nm I have not been able to find any free available information yet.

The Samsung K4B4G0846C-BCK0 is a 4Gb DDR3 SDRAM manufactured at 26 nm, based on the half minimum pitch ("20nm generation"). The technology features capacitor-over-bitline DRAM cell arrays.

Wikipedia on Multiple Patterning: Multiple patterning is a class of technologies for manufacturing integrated circuits (ICs), developed for photplithography to enhance the feature density. The simplest case of multiple patterning is double patterning, where a conventional lithography process is enhanced to produce double the expected number of features. The resolution of a photoresist pattern begins to blur at around 45 nm half-pitch. For the semi conductor industry, therefore, double patterning was introduced for the 32 nm half-pitch node and below, mainly using state-of-the-art 193 nm immersion lithography tools.
A basic example of a double patterning techniques using Spacer mask: first pattern; deposition by e.g. SiO2 ALD or PEALD; spacer formation by etching; first pattern removal; etching with spacer mask;  final pattern [Source Wikipedia]

There are many types of double patterning and when used in combination it iscalled  multiple patterning. Those are:
  • Dual-tone photoresist
  • Dual-Tone Development
  • Self-aligned spacer
  • Double/Multiple exposure
  • Double Expose, Double Etch (mesas)
  • Double Expose, Double Etch (trenches)
  • Directed self-assembly (DSA)
Please see Wikipedia on more information on each type.


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