The 2026 Area Selective Deposition Workshop (ASD 2026)

The ASD Workshop was initiated in 2016 to provide a scientific communication channel to learn and exchange about selective deposition techniques. It has since offered a forum for open discussions between researchers from academia and industry. The meeting will include one day of Tutorials followed by the Workshop at ETEC Building (University at Albany). The last day of the workshop will highlight the state of the art of SC devices and processes at NY state with invited presentation from our main industrial partners at the NY CREATES’ Albany NanoTech Complex.

The 2026 Area Selective Deposition Workshop (ASD 2026) will take place March 29-April 1, 2026, at the University at Albany in New York, but it will be in two different locations:

March 29-31, 2026: ETEC Building

April 1, 2026: NY CREATES’ Albany NanoTech Complex

Abstract submission: Abstracts

Samsung Researchers Achieve Near-Perfect Grain Orientation in Atomic Layer Deposited Ruthenium for Next-Generation Interconnects

Researchers at the Samsung Advanced Institute of Technology (SAIT) have unveiled a breakthrough in interconnect materials at IEDM 2025 with their paper “Grain-Orientation-Engineering of Atomic Layer Deposited Ruthenium Interconnect Technology.” As semiconductor scaling pushes below 10 nm, conventional copper wiring faces mounting resistance and reliability challenges. The SAIT team demonstrated that ruthenium (Ru), deposited via atomic layer deposition (ALD), can serve as a superior alternative by precisely controlling its crystallographic orientation. Through tailored ALD cycles, they achieved more than 99 percent texture quality in Ru films deposited on amorphous underlayers—an unprecedented level of structural order that dramatically reduces electron scattering at grain boundaries.

The study introduces a “supercycle-based area-selective deposition” approach that enables bottom-up via filling, producing c-axis-oriented single-crystal Ru vias. This method not only delivers void-free filling in narrow, high-aspect-ratio structures but also supports excellent conformality, making it highly compatible with advanced three-dimensional BEOL (back-end-of-line) architectures. By demonstrating atomic-scale control over film orientation and growth direction, the researchers show how ALD Ru can overcome the resistivity limitations of conventional PVD methods and outperform Cu in nanoscale interconnect applications.

Beyond resistivity improvements, the findings have broader implications for the semiconductor industry’s transition toward Ru-based interconnect schemes. A highly oriented ALD Ru process could simplify integration by minimizing the need for thick diffusion barriers and improving electromigration resistance. The work reinforces ALD’s growing importance not just for conformal coatings but as an enabler of crystallographic precision at the atomic level. Samsung’s demonstration positions ruthenium as a front-runner for sub-10 nm and 3D interconnect nodes—bridging the gap between conventional BEOL metals and the emerging era of atomic-scale device engineering.

Sources: 

IEEE IEDM 2025 | 33-6 | Grain-Orientation-Engineering of Atomic Layer Deposited Ruthenium Interconnect Technology

SAIT | Samsung Semiconductor Global

IEDM2025 Tutorial - Atomic layer deposited atomically thin In₂O₃ transistors for BEOL logic and memory applications

The IEDM 2025 T3 tutorial session titled “Atomic-layer-deposited atomically thin In₂O₃ transistors for BEOL logic and memory applications” will focus on recent progress in oxide semiconductor thin-film transistor (TFT) technologies designed for back-end-of-line (BEOL) 3D integration. The work is closely associated with Professor Peide (Peter) Ye’s group at Purdue University, which has been leading research on atomic-layer-deposited (ALD) indium oxide (In₂O₃) as a channel material for low-temperature, monolithically integrated logic and memory devices. The presentation will likely consolidate several years of development in ALD In₂O₃ transistors and ferroelectric field-effect transistors (Fe-FETs), demonstrating how these devices can be integrated above silicon CMOS layers in BEOL-compatible processes.

The image shows diagrams and data related to an indium oxide transistor with an 8 nm channel length. This research from Purdue University focuses on developing smaller and better-performing transistors using new material New material advances lead to smaller and better-performing transistors - Elmore Family School of Electrical and Computer Engineering - Purdue University

The main motivation behind this research is to develop semiconductors that can operate effectively within the stringent temperature constraints of BEOL processing, typically below 400°C. ALD In₂O₃ stands out because it can be deposited at 200–250°C, ensuring compatibility with existing copper and low-k interconnect layers. The ALD process provides atomically precise thickness control and excellent film uniformity, enabling channel layers as thin as 0.5–0.7 nm with smooth surfaces and strong electrostatic control. In₂O₃ also possesses a favorable charge neutrality level deep in the conduction band, which leads to high electron density and low contact resistance even in ultrathin configurations. Together, these characteristics make ALD In₂O₃ an attractive candidate for BEOL transistors, offering both scalability and manufacturability advantages over 2D materials or III–V semiconductors.

In terms of device performance, ALD In₂O₃ transistors have achieved channel lengths as short as 8 nm with channel thicknesses under 1 nm, demonstrating on-currents of about 3 A/mm at 0.5 V and transconductance values near 1.5 S/mm. On/off current ratios exceeding 10⁷ have been reported, alongside good subthreshold slopes and uniformity across wafers. Planar BEOL-compatible TFT versions of these devices exhibit electron mobilities above 100 cm²/Vs and current densities exceeding 2 mA/µm at low operating voltages. Some experimental devices have also demonstrated radio-frequency performance with cutoff frequencies around 36 GHz in sub-1 V operation, highlighting their potential for low-power, high-performance logic circuits integrated on top of CMOS wafers.

The memory aspect of this research involves combining ALD In₂O₃ channels with ferroelectric HfZrO₂ (HZO) gate dielectrics to realize In₂O₃-based Fe-FETs. These devices achieve channel lengths as small as 7 nm and exhibit memory windows around 2.2 V, with retention projected beyond 10 years and endurance exceeding 10⁸ switching cycles. Importantly, these Fe-FETs are also fabricated entirely within BEOL-compatible temperature budgets. This enables their use as embedded non-volatile memories in monolithic 3D integration schemes or as building blocks for in-memory computing architectures. The combination of logic FETs and Fe-FETs based on the same material platform offers a streamlined approach to constructing stacked computing tiers with both logic and memory functionality.

Applied Materials Deepens Partnership with Besi and Launches Kinex™ – the Industry’s First Fully Integrated Die-to-Wafer Hybrid Bonding System for Next-Gen AI and Memory Chips

Applied Materials announced it has acquired a 9% stake in BE Semiconductor Industries (Besi) to strengthen their ongoing collaboration on hybrid bonding technology for advanced semiconductor packaging. Building on a partnership that began in 2020, the two companies recently extended their agreement to co-develop the industry’s first fully integrated die-based hybrid bonding system—combining Applied’s front-end processing expertise with Besi’s precision die placement and assembly capabilities. Hybrid bonding, which connects chips through direct copper-to-copper interfaces, is key to improving performance, power efficiency, and cost in next-generation logic and memory chips powering AI applications. Applied emphasized the investment as a strategic, long-term commitment, made through market transactions without seeking board representation or additional share purchases.

Applied Materials and BE Semiconductor Industries (Besi) have introduced Kinex, the industry’s first integrated die-to-wafer hybrid bonding system, engineered to deliver higher performance and lower power consumption for advanced logic and memory chips. The Kinex system unites all hybrid bonding steps — surface preparation, bonding, and metrology — within a single tool, offering tighter interconnect pitches, consistent bonding quality, and improved cycle times.

The Kinex™ Bonding system is the industry’s first integrated die-to-wafer hybrid bonder. It enables production of higher performance, lower power advanced logic and memory chips by integrating all the critical hybrid bonding process steps into one system.

Kinex is Applied Materials’ fully integrated hybrid bonding system, purpose-built for HVM environments. Co-developed with BE Semiconductor Industries N.V. (Besi), the industry leader in hybrid bonding, Kinex combines best-in-class bonding accuracy, advanced queue-time control, and exceptional system cleanliness. Its modular architecture supports many chiplets per module and integrates wet clean, plasma activation, and in-situ metrology for real-time overlay control. Kinex’s smart sequencer and AIx-powered software suite enable predictive maintenance, die-level traceability, and multi-binning capabilities. 

Kinex is optimized for a wide range of applications including 3D integrated circuits, HBM, co-packaged optics (CPO), and sensor integration. Its flexible configuration supports both single-layer and multi-layer bonding flows, with validated performance on silicon, III-V materials, and glass substrates. As the industry moves toward higher die counts and tighter interconnect pitches, Kinex’s roadmap includes enhanced bonding force capabilities, in-situ annealing, and expanded metrology integration. With its scalable design and deep ecosystem partnerships, Kinex is positioned to lead the next wave of innovation in die-to-wafer hybrid bonding, enabling the future of AI, HPC, and beyond.

Sources:

Applied becomes major shareholder of Besi - Bits&Chips

Applied Materials Announces a Strategic Investment in BE Semiconductor Industries | Applied Materials

Kinex