Saturday, April 19, 2014

Video : Understanding the new FinFET semiconductor transistor technology

The FinFET process is a way to stack additional transistors onto the silicon, thereby making faster and more power-efficient chip. For an explainer on the manufacturing process, watch the video below. The term FinFET was coined by University of California, Berkeley researchers (Profs. Chenming Hu, Tsu-Jae King-Liu and Jeffrey Bokor) to describe a nonplanar, double-gate transistor built on an SOI substrate. The distinguishing characteristic of the FinFET is that the conducting channel is wrapped by a thin silicon "fin", which forms the body of the device. The Wrap-around gate structure provides a better electrical control over the channel and thus helps in reducing the leakage current and overcoming other short channel effects. In current usage the term FinFET has a less precise definition. Among microprocessor manufacturers, AMD, IBM, and Freescale describe their double-gate development efforts as FinFET development whereas Intel avoids using the term to describe their closely related tri-gate architecture. In the technical literature, FinFET is used somewhat generically to describe any fin-based, multigate transistor architecture regardless of number of gates. In 2012, Intel started using FinFETs for its future commercial devices. In September 2012, Globalfoundries announced plans to offer a 14-nanometer process technology featuring FinFET three-dimensional transistors in 2014. The next month, the rival company TSMC, announced start early or "risk" production of 16 nm FinFETS in November 2013.[adopted from Wikipedia]
Recently Samsung and Globalfoundries announced an agreement between the two companies would see Samsung develop a 14nm process node and license it to Globalfoundries.


Screendump showing the ALD high-k dielectric and TiN metal gate wrapping the fin conformally.

This Globalfoundries factory near Albany, New York, will adopt a production process developed by Samsung. Kelvin Low, senior director of marketing for Samsung's North American foundry operations, said its 14-nanometer process is already being used to produce some customer chips in small quantities. It predicts volume production by the end of 2014 using the process, which will be introduced at two factories in South Korea as well as Austin. [Source WSJ]

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