Friday, April 27, 2018

Intel shifts high volume 10 nm shipments to 2019 due to yield issues from multi-patterning

As reported by Reuters [LINK], Intel bet the earnings expectations for the first quarter driven by the biggest-ever quarterly jump in its data centre business and small-but-steady growth in its personal computer business.However, Intel also announced that they are pushing out volume production of their 10 nm Logic process to 2019, which was most recently announced for the 2nd half of 2018. during the 1Q 2018 earnings conference calls more details were given:

[Seeking Alpha, LINK] "We continue to make progress on our 10-nanometer process. We are shipping in low volume and yields are improving, but the rate of improvement is slower than we anticipated. As a result, volume production is moving from the second half of 2018 into 2019. We understand the yield issues and have defined improvements for them, but they will take time to implement and qualify. We have leadership products on the roadmap that continue to take advantage of 14-nanometer, with Whiskey Lake for clients and Cascade Lake for the data center coming later this year.

Moore's Law is essential to our strategy and our product leadership. It continues to create significant value for Intel and our customers. While it's taking longer and costing more to deliver and yield advanced process technologies, we are able to optimize our process and products within the node to deliver meaningful performance improvements.

For example, 14-nanometer process optimizations and architectural improvements have resulted in performance gains of more than 70% since the first 14-nanometer products were launched. We combine these advances in manufacturing technology and architecture to produce truly leadership products. And it's that product leadership that ultimately matters most to our customers and end users."

Brian M. Krzanich - Intel Corp.

Earnings call slides [Seeking Alpha, LINK]

In the Q&A Mr. Krzanich elaborated on the reason behind the 10 nm push out and he explained how it is mainly due to yield issues coming from multiple patterning (SADP and SAQP):

- Intel have 10 nm product and process leadership and are shipping 10 nm products today. 
- Those are the densest, highest performing products out there.
- Intel is slowing the ramp down to fix yield issues related to patterning.
- In multi-multi-patterning (SAQP) there are six layers of patterning to produce a feature. 
- Intel understand the yield issues, which are tied to 10 nm being the last technology tied to not using EUV and the amount of multi-patterning and the effects of that on defects.


Intel’s 10 nm Platform Process was presented in detail at the IEDM 2017 (Dec 2017) “A 10nm High Performance and Low-Power CMOS Technology Featuring 3rd Generation FinFET Transistors, Self-Aligned Quad Patterning, Contact over Active Gate and Cobalt Local Interconnects” and you may study the details in this excellent article by Dick James [Solid State Technology, LINK]

Media coverage:
 
The Register