EU Signs €145bn Declaration to Develop Next Gen Processors and 2nm Technology

Hey listen up ALD, Santa is coming - A lot of EU funds coming in bringing Europe back in the leading edge Semiconductor game. Thank you Matthieu Weber for sharing these wonderful news in these bad times.

In a major push to give Europe pride of place in the global semiconductor design and fabrication ecosystem, 17 EU member states this week signed a joint declaration to commit to work together in developing next generation, trusted low-power embedded processors and advanced process technologies down to 2 nm. It will allocate up to €145 bn funding for this European initiative over the next 2-3 years.

Full article in EE Times Europe: LINK

While I am at it, check the planned invest for Europe in the latest Semi equipment forecast. Yes I have double checked, Europe is rolling back into the game as we speak. Following 300 mm fabs are gearing up:

• Globalfoundries Fab1 in Dresden Germany
• STMicro Corlles in Grenoble France
• Infineon Dresden, Germany
• Infineon Villach, Austria
• Bosch Sensortech Dresden, Germany
• Intel Leixlip,

The following results reflect market size in billions of U.S. dollars. New equipment includes wafer fab, test, and A&P. Total equipment does NOT include wafer manufacturing equipment. Totals may not add due to rounding. Source: SEMI December 2020, Equipment Market Data Subscription

Low Resistivity Titanium Nitride Thin Films ALD realized by RASIRC Brute® Hydrazine vaporization technology

TiN ALD is one of the most important ALD processes in high volume manufacturing in the semiconductor industry for more than 15 years. Most Tier 1 ALD equipment manufacturers (e.g. ASM International, Tokyo Electron , Applied Materials, Lam Research, Kokusai, Jusung Engineering, Wonik IPS, Picosun) has TiN ALD and PEALD in their process portfolio for 300 mm wafer productions targeting the Logic, 3DNAND and DRAM fab customers (e.g. Intel, Samsung, TSMC, SK Hynix, Micron, Globalfoundries, Toshiba, TI) because the metallic film has proven to be highly flexible metal film due to:

• Relatively cheap precursor, mainly TiCl4 and TDMAT, as compared to the much more expensive precursors with lower vapor pressure for tantalum metal nitrides (PDMAT) and metals like Co (CCTBA) and Ru (RuCp´s). 
• High vapor pressure and reactivity allowing fast conformal processing bay both CVD, pulsed CVD and ALD for TiCl4/NH3 based processes 
• Possibility to tune low resistivity films however at relatively high temperatures (TiCl4/NH3) not allowing for BEOL thermal budget requirements (<390 °C) 
• Excellent barrier properties hindering metal diffusion (TDMAT and TiCl4) 
• Metal gate work function tuning by doping and partial controlled oxidation 
• Oxygen gettering driving excess oxygen from the gate oxide channel interface into the metal gate reducing the CMOS device EOT. 
• Mini Batch and Large Batch processing capability (e.g. TEL Indy, ASM A412, Kokusai ALDina, Picosun Sprinter)

Due to low resistivity, titanium nitride (TiN) thin films are in production as the diffusion barrier for Cu, Co and W as well as the gate metal barrier in CMOS. However, as mentioned, for high aspect ratio features, thermal ALD deposition  is needed because of high conformality. Therefore, it is very important to develop thermal ALD TiN processes further to improve the capacitor electrode, barrier and CMOS metal gate properties to perfection.

Cheng-Hsuan Kuo and co-workers at UCSanDiego in the Kummel research group, has recently concluded a study on TiN ALD utilizing the RASIRC BruteÒ Hydrazine (N2H2) vaporizer technology, which is presented this week at IEEE SISC December 16-18 (LINK).

In the work, titanium tetrachloride (TiCl₄) and anhydrous hydrazine (Rasirc, Brute Hydrazine^Ò) were employed as the precursors with ultra-high purity nitrogen purge gas.

• The TiN ALD chamber was connected to an in-vacuo Auger Electron Spectrometer (RBD Instruments), which was used to determine the atomic composition of ALD. (Fig. 1)
• The sample was biased at -100V DC and Ar plasma (50W) was used to remove the surface oxides and impurities. (Fig. 2)
• To determine resistivity, four-point probe (Ossila) measurements were performed on TiN thin films on degreased SiO₂ substrates. (Fig. 3)
• Scanning electron microscopy (SEM), ellipsometry, and X-ray reflectivity (XRR) were used to measure TiN film thicknesses. (Fig. 4)

Fig.1 Auger Electron Spectroscopy of TiN at different sputtering time.(oxygen and carbon contents are listed)

Fig. 2 Oxygen concentration and resistivity vs pulse length at 300 °C 

Fig. 3. Oxygen concentration and resistivity vs pulse length at 350 °C 

Fig.4 X-Ray Reflectivity (XRR) of the 350 oC TiN film with optimal pulse lengths 

To conclude, these experiments indicate that minimizing oxygen concentration is key in producing TiN thin films with desirable electrical properties.

The optimal resistivity of the TiN deposited at 350^oC was 160 micro-ohm-cm which is the lowest reported resistivity of any TiN film deposited by thermal ALD.  As stated above the importance of 3D process capability can be met by having TiN thin films synthesized by using thermal ALD and post-plasma treatment reducing oxygen concentration and impurities potentially in very high aspect ratio structures such as contact holes, FinFET, Gate all around FETs, vias, DRAM capacitors structures as well as 3DNAND metal gates and contacts.

References

[1] C. H. Ahn. et al. Metals and Materials International, 7 (2001)

[2] Steven Wolf et al. Applied Surface Science 462 (2018)

Acknowledgements

This work was supported in part by the SRC

LINKS

UCSanDiego 

Kummel research group

EEE SISC December 16-18 (LINK).

Beneq completes new clean room facility

The new ISO 7 cleanroom will be dedicated to manufacturing ALD equipment for semiconductor and other markets with similar cleanroom requirements. The new Espoo, Finland facility includes a 350 m2 ISO 7 cleanroom and a 150 m2 ISO 5 semiconductor ALD application laboratory. 

Beneq, a supplier of atomic layer deposition (ALD) equipment for semiconductor and other industrial markets, has completed construction of a brand-new cleanroom and application laboratory at its corporate headquarters in Espoo, Finland. 

Built with the latest cleanroom design and construction technology, the new facility adds approximately 350 square meters of ISO 7 cleanroom floor space at Beneq's headquarters. It will be used for product and process development, equipment assembly, prototyping, and testing services. 
 

"Since the launch of the Beneq TransformTM last year we have seen great demand for our ALD equipment products from semiconductor customers,” stated Dr. Tommi Vainio, Vice President of ALD at Beneq. “Together with the semiconductor application laboratory the new cleanroom will be the engine for Beneq’s rapid growth in More-than-Moore markets, including power semiconductors, RF, image sensors, MEMS, compound semiconductors, LED & Micro-LED, OLED, and more.” 

The new cleanroom is part of Beneq’s ISO 9001 certified processes. It also houses a modern 150 square-meter semiconductor application laboratory, solely designed for developing and prototyping ALD solutions for More-than-Moore applications. Beneq has also expanded its existing cleanroom facility to ensure the highest availability and new safety features. 

The new cleanroom officially entered into production in December 2020. Prior to this facility the company had 1900 square meters of existing cleanroom capacity, which it will continue to operate for other customer markets.

Imec introduces 2D materials in the logic device scaling roadmap

[IEDM 2020 Virtual, Imec Belgium LINK] At the 2020 IEDM conference, imec proposes that 2D semiconductors like tungsten disulfide (WS2) can further extend the logic transistor scaling roadmap. The team laid the groundwork for integrating 2D semiconductors in a 300mm CMOS fab, and worked towards improved device performance. These findings are presented in four IEDM papers, one of which was selected as IEDM highlight.

More details can be found in 4 papers presented at the 2020 IEDM conference:

[1] ‘Introducing 2D-FETs in device scaling roadmap using DTCO’, Z. Ahmed et al.
[2] ‘Wafer-scale integration of double gated WS2-transistors in 300mm Si CMOS fab’, I. Asselberghs et al.
[3] ‘Dual gate synthetic WS2 MOSFETs with 120µS/µm Gm 2.7µF/cm2 capacitance and ambipolar channel’, D. Lin et al.
[4] ‘Sources of variability in scaled MoS2 FETs’, Q. Smets et al. (IEDM highlight paper)

TEM image of a 2D device fabricated with 300mm processes. (Source: Imec)

KLA Introduces Two New Systems that Take On Semiconductor Manufacturing's Toughest Problems

MILPITAS, Calif., Dec. 10, 2020 /PRNewswire/ -- Today KLA Corporation (NASDAQ: KLAC) announced two new products: the PWG5™ wafer geometry system and the Surfscan® SP7XP wafer defect inspection system. The new systems are designed to address exceedingly difficult issues in the manufacture of leading-edge memory and logic integrated circuits.

KLA’s new PWG5™ patterned wafer geometry metrology system and Surfscan® SP7XP unpatterned wafer defect inspection system support development and production of advanced logic, DRAM and 3D NAND devices.

Stacked ever higher, like molecular skyscrapers, the most capable flash memory is built in an architecture called 3D NAND. Today's 96-layer top-of-the line memory chips, already on the market in the most advanced mobile devices, will soon be superseded by 3D NAND structures with 128 or more layers in the ongoing quest for increased space-efficiency and cost-effectiveness. To manufacture these complex structures requires depositing hundreds of thin films of multiple materials, and then creating memory cells by etching and filling holes several microns deep and one-hundredth of a micron across. As these film stacks grow higher, they induce stress on the wafer, ultimately distorting the surface planarity of the wafer. These warped wafers impact the uniformity of downstream processes and patterning integrity, ultimately affecting final device performance and yield. The PWG5 metrology system can measure minute distortions of wafer geometry with unprecedented resolution to identify and correct patterned wafer distortion at the source. Moreover, these critical wafer geometry measurements can now be accomplished for large warp ranges at inline speeds.

"The complex multilayer construction of 3D NAND has moved wafer geometry measurements to the forefront," said Jijen Vazhaeparambil, general manager of the Surfscan and ADE division at KLA. "Our new patterned wafer geometry system, the PWG5, has the sensitivity to measure any deviations from planarity on the front side and back side of the wafer simultaneously. Its first-of-a-kind inline speed and exceptional resolution support not only 3D NAND, but also advanced DRAM and logic applications. Coupled with KLA's 5D Analyzer® data analytics system, the PWG5 helps our customers drive decisions, such as wafer re-work, process tool re-calibration, or alerting the lithography system so that best possible patterning corrections can be applied. The PWG5 system plays a critical role in process control, helping grow advanced memory and logic yield, performance and fab profitability."

On the leading-edge logic side of the semiconductor industry, high volume manufacturing of 5nm node devices is rising while the 3nm node is under development.* EUV lithography has become nearly universal for the most critical layers within these nodes, and device manufacturing is further complicated by novel geometries like finFET or gate all around (GAA) transistor architectures. Patterning such small, complex features in a repeatable way, billions of times across a wafer, requires exquisite defectivity control, including use of unpatterned wafer inspectors for careful qualification of starting substrates and materials, and frequent monitoring of processes and tools. The new Surfscan SP7XP unpatterned wafer defect inspection system features advancements to sensitivity and throughput, and introduces machine learning-based defect classification that together enable capture and identification of an even wider range of defect types on an even wider range of blanket films and substrate types than the benchmark Surfscan SP7.

Vazhaeparambil added, "The Surfscan design team focused not only on technical advances to support sensitivity and defect classification, but also on improving the cost of ownership." As a result, the Surfscan SP7XP represents a single-tool solution for unpatterned wafer inspection applications from R&D to high volume manufacturing of leading-edge design node substrates and devices. It is in use at silicon wafer manufacturers, semiconductor equipment manufacturers developing defect-free processes, and semiconductor fabs for ensuring incoming wafer, process and tool quality.

To maintain their high performance and productivity, Surfscan SP7XP and PWG5 systems are backed by KLA's global comprehensive service network. For more information about the technology advances that enable the PWG5 and Surfscan SP7XP systems' new capabilities, and to read about applications of the systems beyond those described here, visit the KLA Advance newsroom.

*The node nomenclature used by the semiconductor industry correlates to the smallest dimension of the transistor. For comparison 3nm is about half the diameter of the DNA double-helix.

Surfscan and 5D Analyzer are registered trademarks of KLA Corporation.

ALD Webinar - The Ultimate Anti-Corrosion Coating Solution presented by Beneq

Join this webinar featuring ALD (atomic layer deposition) pioneer Beneq to learn about the unique benefits of ALD for critical chamber components with complex geometry, and how the technology offers the ultimate anti-corrosion coating solution for semiconductor equipment parts.

Wednesday, January 27, 2021, 9:00 AM – 10:00 AM CET

Save Your Seat

If you can't attend the live session, register for access to a recording for later viewing.

Semiconductor manufacturing involves corrosive gases in multiple processes. As we transition to each new technology node, e.g. from 10nm to 7nm and to 5nm, there are even more stringent fab requirements against metal and particle contamination. This poses challenges for existing coating methods such as anodization or plasma spray, which may not provide complete protection especially on critical chamber components with complex geometry. 

Topics to be discussed:

• Common issues of metal or particle contamination for critical chamber components
• Common coating methods to protect against corrosion, and how they compare
• What properties to look for – e.g. high purity and uniformity – when evaluating the optimal protective coating solution
• Unique benefits of ALD coatings with Al2O3 and Y2O3
• How to work with your OEM partner to design, test and implement an ALD coating solution for your equipment

Agenda and Speaker Information

Sponsored by

[PALD] SUMMIT Video Library is now available on demand - Enjoy!

The 2nd [PALD] Summit by Forge Nano is now happening. This is following the first very successful event earlier in 200 and Forge Nano is planning yet a 3rd event i summer 2021. More information will come in the near future.

Anyhow, the [PALD] SUMMIT Video Library is now available on demand - Enjoy!

------ [PALD] SUMMIT on Demand LINK ------

Presentation by BALD Engineering during the first [PALD] Summit

Horizontal high temperature rotating graphite drum furnace for ALD and LPCVD on particles and powders BALD Engineering AB: Jonas Sundqvist

MSS Corp Low temp ALD the solution for analyzing extreme ultraviolet photoresist

MSS launches new materials analysis items: "ALD sample preparation" for 5nm ~ 2nm EUV PR & Low-k materials

MSS launches new materials analysis items: "ALD sample preparation" for 5nm ~ 2nm EUV photoresist & Low-k materials process structure and composition analysis! All the loyal customers can still keep ALD sample preparation technical services with the same the price. On the other hand, the customers will be applicable to the quotation of new analysis service items.

[MSS Corp article] Atomic layer deposition (ALD) has attracted considerable attention in integrated circuit (IC) equipment industry in recent years. This is largely due to its superior properties, excellent coating conformity, and controllable coating thickness in single atomic layer, especially when compare to other coating systems.

Today, ALD has turned into a core technology in IC fabrication processes and its significance has become even more pronounced as a result of its advanced fabrication processes, including such modern solutions as 3D FinFET or even future gate-all-around (GAA), along with all other variants where precisely well-controlled coating thickness and thin film conformity in sub-nanometer level are in high demanded.

Apart from the above applications in IC fabrication, ALD can also be used for material analysis. A good example in this regard would be the transmission electron microscope (TEM), where by ALD is used to prepare a protection layer on top of areas of interest (AOI) before TEM lamella preparation. Here, it is well known that TEM lamellas are mainly prepared by focused ion beam (FIB). In order to protect AOI from ion bombardment during FIB milling, an external protection layer on top of AOI is indispensable. The material within this protection layer is generally carbon-based glues or metals, and the layer thickness varies from tens of nanometers up to about 500 nm. This protection layer can be coated on surface of AOIs by spin coaters or deposition systems in a vacuum chamber.

Now, depending on coating mechanisms, sample temperature and ion bombardment effects are two main factors that should be considered in order to prevent structures of AOI being altered or damaged during coating processes. For older technology nodes (bigger than 28 nm node), such coating can be easily achieved with wider preparation windows. This is because both the material and structure of AOI are relatively robust and stable. Generally speaking, coating with normal preparation conditions leads to no obvious structural changes or damages of the AOI when observing TEM results.

In terms of advanced technology nodes (below 16 nm node), continuous shrinkage of critical dimension (CD) along with the fact that many new materials are now involved in the fabrication processes are important factors to consider. For instance, extreme ultraviolet (EUV) photoresist (PR) has become one of the most crucial materials used in fabrication processes of 7 nm (and below) node FinFET and future GAA. However, it has been widely reported that EUV PR is extraordinarily fragile and highly sensitive to temperature and ion (both polarities). Damaged or deformed AOIs are expected to be found by traditional coating for older technology nodes, and pristine structures no longer exist for further analysis.

Coating conformity can also be problematic for structures with smaller CDs, such as vias or trenches, when using traditional methods. Extrinsic pinholes or bubbles are expected to be formed before vias or trenches being fully filled with the coating material. These unwanted artifacts could lead to possible difficulties in terms of preventing curtain effect during FIB milling and afterwards when it comes to TEM data interpretation.

To solve all of the above listed challenges, MSS proposes an innovative approach – utilizing a low-temperature vacuum ALD approach to prepare the protection layer on surface of AOIs. Because of its growth mechanism, ALD has an excellent coating conformity, so it is perfectly fitted for coating materials into vias, trenches, or other structures with smaller CDs.

When it comes to preventing damages from FIB milling and following TEM observation (high-energy electron damages), a thicker protection layer is preferred – at least 50 nm in thickness. This is because the thick protection layer is like a powerful armor and has a strong resistance to FIB milling and high-energy electron bombardment. Depending on surface properties of AOIs and analytic purposes, different protection materials can be prepared. Most importantly, despite varieties of protection materials, the sample temperature must always be kept at a low temperature throughout preparation – only a bit higher than room temperature, but certainly well below the one utilized in traditional coating systems. It is crucial, especially for EUV PR because all these steps have to ensure EUV PR stays intact throughout the whole analysis flow and precise results can be delivered.

Figure 1. a-d TEM images of PR structures. Two different types of PR structures were utilized a, b and c, d. The protection layers in a and c were prepared by the traditional coating and those in b and d were prepared by MSS ALD coating. In a and c, obviously, the PR structures were damaged or altered by comparing with those in b and c, see the areas marked by green arrows.

Figures 1a and 1c exhibit TEM images taken from two different PR samples. Their protection layers were all prepared by the traditional coating method. Poor coating conformity can be observed, especially in Fig. 1c. For comparison, an MSS low-temperature vacuum ALD has been utilized on another two samples with the same structures and materials as Figs. 1a and 1c. The TEM images are shown in Figs. 1b and 1d, respectively. From these TEM images, it is easy to see the PR structures prepared by the traditional coating have been damaged or modified, especially the areas marked by green arrows, with certain degree by comparing with the ones prepared by MSS ALD.

The question here now becomes how best to prove the low-temperature vacuum ALD coating has no effects on modifying PR structures as shown in Figs.1 a and 1c. To answer this question, we utilized one of our niche analyses, non-coating high-resolution SEM, to observe the pristine sample before ALD coating and the result is shown in Fig. 2a. The same sample was then coated with MSS ALD followed by FIB milling and TEM observation, and the result is shown in Fig. 2b. The fact that the PR structure shown in Fig. 2a is consistent with the one shown in Fig. 2b observed by TEM strongly suggests the PR structure does not need to be altered or damaged with our ALD preparation.

Figure 2. a High-resolution non-coating SEM image of the PR structure. b TEM image of the PR structure, the same structure as a and the protection layer was prepared by MSS ALD coating. By comparing with these two images, the PR structures stay the same after the ALD coating.

In conclusion, we have successfully demonstrated that MSS’s low-temperature vacuum ALD can be utilized for preparing a protection layer on EUV PR in order to prevent damages from FIB milling and TEM observation. Such sample protection can be applied to other fragile samples as well, and the concept can be extended to other purposes not only in material analysis but failure analysis or even surface analysis.

MSS’s theory on utilizing a low-temperature vacuum ALD for sample protection has been patented in 2020. We believe more and more samples will need such technology in the near future.