Plasma-Based Deposition Refines ALD for Next-Gen DRAM: 30% Higher k, 40× Lower Leakage

Researchers from POSTECH and UNIST in Korea have unveiled a new atomic-layer process using plasma-based deposition (PDP) to significantly improve DRAM capacitors. This innovation addresses a critical challenge in semiconductor manufacturing: enhancing the performance of high-k dielectric materials without introducing defects that cause electrical leakage. The PDP process refines the deposition of aluminum-doped titanium dioxide (ATO), enabling better charge storage and stability for next-generation devices.

The PDP technique introduces a controlled plasma treatment step after standard atomic layer deposition (ALD). By exposing the capacitor film to an argon/oxygen plasma, the process reorders the crystal lattice and fills oxygen vacancies—defects that typically cause instability and increased leakage currents in conventional ALD methods. This precise atomic-scale refinement is key to achieving superior performance.

The results of this breakthrough are highly promising, with the treated DRAM capacitors showing a roughly 30% higher dielectric constant and a nearly 40-fold reduction in leakage current compared to conventional methods. This enhances DRAM retention time, improves energy efficiency, and boosts overall device reliability. Beyond DRAM, this technology has potential applications for other next-gen electronic devices and energy storage systems.

Sources:

https://www.miragenews.com/new-process-boosts-semiconductor-performance-1557957/

Researchers Develop Innovative Process to Enhance Semiconductor Device PerformanceUNIST News Center | UNIST News Center

AlixLabs presents HAR narrow-fin patterning at ECS 248

AlixLabs is pleased to announce that Dr. Dmitry Suyatin, CIPO and Co-Founder, has presented the company’s latest advances in APS™ (Atomic Layer Etching Pitch Splitting) at the 248th Electrochemical Society (ECS) Meeting held in Chicago, October 12–16, 2025.

During the session, Dr. Suyatin highlighted new experimental results demonstrating high-aspect-ratio (HAR), narrow-fin patterning on bulk silicon achieved using conventional immersion lithography at a 193-nanometer wavelength. These results further confirm the viability of APS™ as an innovative method for extending fine-pitch patterning capabilities using existing lithography infrastructure.

By enabling advanced logic patterning without the need for next-generation scanners, APS™ offers a significant opportunity to reduce process complexity and cost, paving the way for broader access to advanced semiconductor manufacturing technologies.

“These new APS™ results – demonstrating high-aspect-ratio narrow-fin (CD < 10 nm) patterning on bulk silicon – go hand in hand with our recent patent successes,” said Dmitry Suyatin, CIPO and Co-Founder of AlixLabs. “Together, they validate APS™ as both a technically sound and strategically protected innovation in semiconductor manufacturing. As we prepare to install our beta tool that will become operational in fall 2026, we’re excited to take APS™ from lab-scale to production-grade refinement. Each step brings us closer to making advanced logic manufacturing simpler, more accessible, and more cost-efficient for the global industry.”

The advances presented at ECS reflect AlixLabs’ long-term mission to lower the threshold to advanced logic production, supporting a more sustainable, affordable, and globally accessible semiconductor ecosystem.

This research has been led by Dr. Dmitry Suyatin and Dr. Intu Sharma, whose work continues to push the boundaries of patterning innovation.

Source: AlixLabs presents HAR narrow-fin patterning at ECS 248 – AlixLabs