Saturday, May 28, 2016

Imec Tech Forum 2016 on the future of scaling, EUV and transistor architecture

Here is a very interesting article "Event scans silicon road map, IoT as driver" by Rick Merritt in EETimes from Imec Tech Forum that took place this week in Brussels. ALD, EUV and Gate All Around Nanowire transistors is still all on the table.

As previous years Imec also this year rewarded "The imec lifetime of innovation award 2016" and this year it was given to Dr. Gordon Moore himself. Below is an interview with Gordon Moore in Hawaii made by Luc Van den Hove - President & CEO of imec.


Interview with Dr. Gordon Moore who was granted the imec lifetime of innovation award 2016. Interview by Luc Van den Hove - President & CEO of imec. [www.youtube.com]

Ivo Raaijmakers, chief technologist of equipment maker ASM International on scaling


“The industry will find a way to continue scaling, not a classic Denard scaling, but there are many innovations in the pipeline…so maybe the growth rate will decrease a bit and the cadence of new nodes will decrease…but we don’t see this as a downward spiral, just a shift from nodes maybe every three years instead of two,”

An Steegen, the senior vice president of process technology at Imec on EUV and the 5 and 3 nm nodes

“We make daily progress [on EUV]…the most complex layers at the back end where it is very difficult for immersion will be the first insertion point and the sooner the better,” said An Steegen, the senior vice president of process technology at Imec.

Rick Merritt in EETimes reports that: Steegen believes horizontal nanowires, a sort of gate-all-around deisgn, will be the next big transisitor. They could be stacked laterally to deliver 30-50% gains in lower power and higher performance, she said. Imec is still evaluating first-generation designs that it will need to prove out in second-gen hardware.

“We aways need new features to manage power density, we had dynamic frequency and voltage scaling a few years ago, FinFETs now and I believe nanowires in the future,” Steegen said.

Further out vertical nanowires could be a next step. However “going vertical is very disruptive” and these transistors cannot be stacked without area penalties, potentially forcing a move to new high-mobility III-V materials to hit performance targets, she said.

Imec is exploring lateral and vertical nanowires as successors to the FinFET. (Image: Imec) 

Full article in EETimes here.