Sunday, May 15, 2016

UPDATE: Imec showcase low cost Self-aligned quadruple patterning (SAQP) for sub 10nm nodes

Imec has developed a low cost Self-aligned quadruple patterning (SAQP) that meet the basic requirements for 7 and 5 nm CMOS FinFET patterning. The technology is based on 193 immersion (193i) lithography and repeated plasma ALD and etching steps as alternative to expensive high resolution EUV lihography. You can read all details SPIE Newsroom (abstract below).

UPDATE: According to information received spacers are Plasma Enhanced ALD SiO2 and the a-Si mandrel and SiN all from ASM. The etching has been performed using Lam Research chambers.

Self-aligned quadruple patterning to meet requirements for fins with high density

Efraín Altamirano-Sánchez, Zheng Tao, Anil Gunay-Demirkol, Gian Lorusso, Toby Hopf, Jean-Luc Everaert, William Clark, Vassilios Constantoudis, Daniel Sobieski, Fung Suong Ou and David Hellin

14 May 2016, SPIE Newsroom. DOI: 10.1117/2.1201604.006378 
Transmission electron microscopy (TEM) images of the stages of SAQP show, from left to right: patterning of the first core onto a mandrel; deposition of SiO2 by ALD; etching of the first spacers; etching of the mandrel to produce the second core; further deposition of SiO2by ALD; and etching of the second spacers and silicon nitride pad (14 May 2016, SPIE Newsroom. DOI: 10.1117/2.1201604.006378 ).

Repeated plasma deposition and etching steps enable the patterning of fins with the potential to meet requirements of N7 and N5 technologies for profile, depth, uniformity, and pitch walk. Over recent decades, continuous reductions in the scale of field-effect transistors in accordance with Moore's law, which states that the number of transistors in an integrated circuit doubles every two years, have enabled continuous increases in device performance and transistor density. Currently, state-of-the-art devices are based on structural elements with dimensions of 7nm or even 5nm (N7/N5). The highest-resolution patterns required for N7/N5 devices are silicon fins with a pitch of 18–28nm and metal layers with a pitch of 24–32nm. These dimensions far exceed the resolution attainable with 193 immersion (193i) lithography. Extreme UV lithography might be an alternative process for the formation of lines and spaces, but is expensive and not entirely ready for use in production.