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Applied Materials has announced new materials engineering breakthroughs aimed at improving energy efficiency in computing by enabling copper wiring to scale down to the 2nm node and beyond. Central to this innovation is the industry’s first high-volume use of ruthenium in a binary metal liner with cobalt (RuCo), which allows for thinner liners, improved copper fill, and up to 25% lower electrical resistance. This innovation, part of the new Endura™ Copper Barrier Seed IMS™ system, combines six process technologies in one high-vacuum system and is already being adopted by major logic chipmakers. These advances address the increasing challenges of interconnect resistance and mechanical weakness as chip feature sizes shrink.
Applied Materials’ new Endura™ Copper Barrier Seed IMS™ with Volta™ Ruthenium CVD combines six different technologies in one high-vacuum system, including an industry-first combination of materials that enables chipmakers to scale copper wiring to the 2nm node and beyond.
Complementing this, Applied also introduced an enhanced version of its long-standing Black Diamond™ low-k dielectric material, designed to reduce capacitance and reinforce chip strength — critical for advanced 3D stacking in logic and memory chips. These solutions help overcome scaling limitations associated with Moore’s Law and are critical for sustaining AI-driven computing advancements. As demand for high-performance, energy-efficient chips grows, Applied’s innovations are expanding its served market for interconnect technologies, which is projected to reach $7 billion per 100K wafer starts per month with the addition of backside power delivery.
The new Producer™ Enhanced Black Diamond™ dielectric is a revolutionary product, enabling next-generation chips of the AI era. Enhanced Black Diamond™ addresses two key issues in leading-edge chips. As wires become closer together, parasitic capacitance increases. The phenomenon slows signals down, worsening performance and energy consumption. Additionally, damaging plasma manufacturing processes can cause the thinner insulating dielectric material between wires to fracture or collapse, potentially leading to chip failure (Embedded from Youtube : https://youtu.be/uJju9KNA-yE?si=ae-Eqc0Qaf5J8e0W).
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This is actually a pretty big step forward for chip technology, especially with how quickly AI workloads are growing. Moving toward 2nm with innovations like a ruthenium-cobalt liner and advanced dielectrics shows how much effort is going into improving performance while keeping power use in check. The 3D stacking angle is just as interesting, since it can really change how efficiently data moves within chips. It’s one of those developments that most people won’t notice directly, but it’ll quietly power everything from smarter apps to faster systems. Funny enough, while reading about all this cutting-edge tech, I caught myself thinking about how people are also trying to optimize their own time in different ways, like searching for services where they can Pay someone to take my online nursing exam just to keep up with everything else going on.
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