Saturday, June 12, 2021

Applied Materials to present New Innovations Needed to Continue Scaling Advanced Logic (June 16)

Applied Materials (Santa Clara, USA): The semiconductor industry is at a crossroads. Demand for chips has never been greater as we enter the early stages of a new wave of growth fueled by the Internet of Things, Big Data and AI. At the same time, it’s become apparent that conventional Moore’s Law 2D scaling techniques are no longer able to deliver the consistent improvements in power, performance, area-cost and time to market (PPACt) that chipmakers have long relied on. This is particularly the case for logic chips, which serve as the main processing engine in nearly every electronic product and where power efficiency and performance are critical.

To shed light on this issue, Applied Materials is hosting an online Logic Master Class on Wednesday, June 16. I will be joined by other experts from Applied and the industry to discuss the logic scaling roadmap, including challenges and solutions for delivering continued improvements in PPACt. We will be exploring several different areas, including transistor and interconnect scaling, patterning and design technology co-optimization (DTCO). The common denominator underlying all of these areas is the need to supplement classic 2D scaling with a combination of approaches that includes new chip architectures, new 3D structures, novel materials, new ways to shrink features and new ways to connect chips with advanced packaging.

Source: Applied Materials Blog (LINK)


Primary modules of a FinFET are channel and shallow trench isolation (1), high-k metal gate (2) and transistor source/drain resistance (3). (Credit: Applied Materials)

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