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Atomic Level Processing technology like ALD and ALE are crucial for current and coming nodes in both logic and memory. So for you atomic level people it may be interesting to keep a close track of the current challenges and solutions in scaling and patterning. Here are three interesting articles by Coventor covering this topics (from the Coventor August 2017 news letter).
What drives SADP BEOL variability (LINK)?
Figure from Coventor August 2017 newsletter
Until EUV lithography becomes a reality, multiple patterning technologies such as triple litho-etch (LELELE), self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP) are being used to meet the stringent patterning demands of advanced back-end-of-line (BEOL) technologies. In this blog, we modeled SADP process variability to try to understand the effect of this variability on BEOL and RC performance.
How small variations in photoresist shape significantly impact multi-patterning yield (LINK)
Figure from Coventor August 2017 newsletter
Things were easy for integrators when the pattern they had on the mask ended up being the pattern they wanted on the chip. Multi-patterning schemes such as Self-Aligned Double Patterning (SADP) and Self-Aligned Quadruple Patterning (SAQP) have changed that dramatically. In this blog, we look at how small variations in photoresist shape can significantly impact multi-patterning yield.
Problems and Solutions at 7nm (LINK)
As we approach 7nm and lower technology nodes, lithography, patterning, material and interconnect challenges abound. David Fried, Chief Technology Officer of Coventor, addresses these challenges in a video interview with Ed Sperling of Semiconductor Engineering. David also reviews the problems that we are facing at both 7nm and 5nm and proposes some potential solutions.
Movie from Coventor August 2017 newsletter as released on Youtube from an interview with Ed Sperling of Semiconductor Engineering.
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