Imec introduces 2D materials in the logic device scaling roadmap

[IEDM 2020 Virtual, Imec Belgium LINK] At the 2020 IEDM conference, imec proposes that 2D semiconductors like tungsten disulfide (WS2) can further extend the logic transistor scaling roadmap. The team laid the groundwork for integrating 2D semiconductors in a 300mm CMOS fab, and worked towards improved device performance. These findings are presented in four IEDM papers, one of which was selected as IEDM highlight.

More details can be found in 4 papers presented at the 2020 IEDM conference:

[1] ‘Introducing 2D-FETs in device scaling roadmap using DTCO’, Z. Ahmed et al.
[2] ‘Wafer-scale integration of double gated WS2-transistors in 300mm Si CMOS fab’, I. Asselberghs et al.
[3] ‘Dual gate synthetic WS2 MOSFETs with 120µS/µm Gm 2.7µF/cm2 capacitance and ambipolar channel’, D. Lin et al.
[4] ‘Sources of variability in scaled MoS2 FETs’, Q. Smets et al. (IEDM highlight paper)

TEM image of a 2D device fabricated with 300mm processes. (Source: Imec)