Saturday, November 23, 2019

Imec updates semiconductor miniaturization roadmap to 1nm-ITF Japan 2019

Imec held an annual research result presentation event “imec Technology Forum Japan 2019 (ITF Japan 2019)” in Tokyo on October 11.




This is what we are to expect coming next for Logic scaling: Nanosheet transistors (Gate All Around transistors), Buried Power Rails, Ruthenium incorporation, Forksheet transistor architecture, CFET (complementary FET by 3D stacking of nanosheet PFET and NFET), deployment of 2D materials, spintronics, and quantum computing as the way to continued chip scaling for keeping a modified Moore's Law alive.
Source: LINK

----------
By Abhishekkumar Thakur

No comments:

Post a Comment