VLSI 2019 Workshop - The Impact of Atomic Layer Processing and Selective Area Patterning on Device Fabrication and Performance

On June 9th, the 2019 Symposia on VLSI Technology and Circuits will feature a free workshop on The Impact of Atomic Layer Processing and Selective Area Patterning on Device Fabrication and Performance. This workshop is endorsed by the AVS and features presentations from some prominent members of the AVS community. If you happen to be attending the VLSI Symposia, or have colleagues who are planning to attend, please let them know about this opportunity hear about the impact of ALD/ALE on device properties and to further develop the link between the ALD/ALE process community and the semiconductor device and circuits community. 

 

Any additional questions you may have, please feel free to reach out to Eric Joseph, the workshop organizer, to the workshop committee (which consists of the 2019 ALD Conference / ALE Workshop Chairs) or to the VLSI or AVS staff. 

 

More information: LINK