Thursday, February 19, 2015

Processing of graphene on 300mm HKMG Si device wafers in a CMOS Fab at CNSE

Processing of graphene on 300mm Si wafers in a state-of-the-art CMOS fabrication facility is now possible thanks to research at College of Na- noscale Science and Engineering, SUNY Polytechnic Institute, Albany NY.

It has been demonstrated that working MOSFETs with graphene channels can be fabricated in a conventional 300mm CMOS fabrication line using state-of-the-art process tools. The building blocks shown  can be used to fabricate other novel device architectures that can take advantage of the unique properties of graphene or other interesting single-layer (i.e., 2D) materials. Further optimization of graphene transfer and contact schemes intended to reduce overall resistance are ongoing and will the focus of future research.

Graphene 4-C

Higher magnification view of 100nm contact. Dotted line shows expected location of graphene (Image Solid State Technology)

A gate-quality 4nm HfO2 dielectric was deposited using an ALD process. Graphene was then transferred onto this HfO2 surface. This approach eliminates the need for a gate-quality dielectric deposition over the graphene.