Energy Storage on Chip Integrated Supercapacitors

[From Fraunhofer IPMS-CNT Web www.cnt.fraunhofer.de]

 

The progressive miniaturization of electronic devices such as of smartphones or sensors for medical, industrial and automotive applications requires smaller substrates. This drives amongst others the integration and scaling of space consuming external passive components for buffering and decoupling purposes on chip (SoC) or package (SiP) level. Simultaneously, extremely high capacitances are needed. The main parameters to increase the capacitance are on the one side the choice of an isolator material with high dielectric constant. Several high-k materials like HfO2, ZrO2 or Ta2O5 based systems are under investigation at the Fraunhofer IPMS-CNT.

 

Intensive material tuning is necessary to meet the electrical requirements for capacitor applications with respect to capacitance density and linearity, leakage current and reliability. While doing this, the capacitor area has to be as large as possible andthat can be achieved by 3D integration of high aspect ratio (AR) structures.

 

a) SEM cross section of a trench array with AR 13:1 filled with MIM stack and b) top down micrograph of Si trench array after silicon etch.

 

c) TEM micrograph of a MIM stack

The Fraunhofer IPMS-CNT has developed Si-integrated high-density capacitors based on 300 mm wafer technology aiming to buffer capacitor applications. A simplified patterning scheme using e-beam lithography and high technology dry etch processes provides structures with large aspect ratio in a high package density (Figure 1a and 1b). The used capacitor stack is based on a metalinsulator-metal (MIM) structure built from Al-doped ZrO2 as dielectric and TiN electrodes. All materials are deposited by atomic layer deposition to reach highly conformal step coverage in the large aspect ratio structures (Figure 1c). The electrical characteristics show very low leakage current densities normalized for a capacitor of 1 μF. Thereby, the capacitance is stable over the voltage region with a deviation smaller than 3 %.
The temperature stability is below 5 %. These values are significantly lower compared to common ceramic capacitors. The good electrical results are complemented by a reliability over 10 years. The maximum capacitance reached for the AR of 6:1 (Gen2) lies around 100 nF/mm2 for the material system which is adapted to an operation voltage of 3 V. This is a significant increase compared to planar capacitors (Gen1).. By increasing the AR to 13:1 (Gen3) a capacitance enhancement to 220 nF/mm2 could be achieved.
The Fraunhofer IPMS-CNT forces also an up-scaling of the 3D capacitors (Gen4-5) either by an improved etch-process or by using materials with higher dielectric constant. The outlook predicts integrated capacitors of 1 μF.

Further Information can be find in this excellent pape by Wenke Weinreich et al
High-density capacitors for SiP and SoC applications based on three-dimensional integrated metal-isolator-metal structures, Weinreich, W., Rudolph, M. ; Koch, J. ;Paul, J. ; Seidel, K. ; Riedel, S. ; Sundqvist, J. ; Steidel, K. ; Gutsch, M. ;Beyer, V. ;Hohle, C. Bus. Unit Fraunhofer Center Nanoeletronic Technol., Fraunhofer Inst. of Photonic Microsyst., Dresden, Germany, 2013 IEEE International Conference onIntegrated Circuit Design