FinFET evolution for the 7nm and 5nm CMOS technology nodes
From AARON THEAN, Director of the Logic Device Program at imec, Leuven, Belgium.http://electroiq.com/blog/2014/01/finfet-evolution-for-the-7nm-and-5nm-cmos-technology-nodes/
"The learning curve to master these materials (for FinFETs) is steep. For example, introducing Ge into a fin is not a trivial process when it agglomerates easily with higher process temperatures. On the device side, leakages due to narrow band gap, gate-stack passivation, and defectivitiy are on-going hurdles. Moreover, any technique employed to integrate Ge in the pFET must be CMOS compatible, which means that it must allow a co-integration with materials for nFETS, like Si, III-V materials. For all these challenging options, it is our goal to identify, for our technology partners, the promising options, innovate on the solutions, and work-out the design/system impact"
From AARON THEAN, Director of the Logic Device Program at imec, Leuven, Belgium.http://electroiq.com/blog/2014/01/finfet-evolution-for-the-7nm-and-5nm-cmos-technology-nodes/
"The learning curve to master these materials (for FinFETs) is steep. For example, introducing Ge into a fin is not a trivial process when it agglomerates easily with higher process temperatures. On the device side, leakages due to narrow band gap, gate-stack passivation, and defectivitiy are on-going hurdles. Moreover, any technique employed to integrate Ge in the pFET must be CMOS compatible, which means that it must allow a co-integration with materials for nFETS, like Si, III-V materials. For all these challenging options, it is our goal to identify, for our technology partners, the promising options, innovate on the solutions, and work-out the design/system impact"
Cross-sectional TEM images Left: SiGe on Si Fins, Middle: strained Ge/SiGe on Si, Right: InGaAs/InP on Si Fins.
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