Stanford presents Area Selective ALD to Develop Higher Performing, More Energy Efficient Electronics

Press release: Stanford University researchers sponsored by Semiconductor Research Corporation (SRC), the world’s leading university-research consortium for semiconductor technologies, have developed a new area selective atomic layer deposition (ALD) process that promises to accelerate the manufacturing of higher performing, more energy efficient semiconductors. 

The Stanford researchers employ the intrinsically selective adsorption of octadecylphosphonic acid self-assembled monolayers on Cu over SiO2 surfaces to selectively create a resist layer only on Cu. ALD is then performed on the patterns to deposit a dielectric film. A mild etchant is subsequently used to selectively remove any residual dielectric film deposited on the Cu surface while leaving the dielectric film on SiO2 unaffected. The selectivity achieved after this treatment, measured by compositional analysis, is found to be 10 times greater than for conventional area selective ALD. "Reprinted (adapted) with permission from (ACS Nano, 2015, 9 (9), pp 8710–8717, DOI: 10.1021/acsnano.5b03125). Copyright (2015) American Chemical Society."
 

Press release Continued :

 

It is well known that next-generation electronic, optoelectronic and sensing devices that contain nanoscale dimensions face increasingly difficult materials and fabrication challenges as the downward scaling of these devices continues. Conventional semiconductor manufacturing processes are time-consuming and expensive, in part due to the need for lithographic patterning. The Stanford research leverages simple ALD and etching processes that eliminate this lithography step and improve selective deposition of dielectric materials by more than 10 times in film thickness compared to similar advanced processes.

Due to difficulties of current top-down fabrication processes that contain multiple deposition, lithography and etching steps, along with problems with misalignment in lithography, using an alternative approach in which the desired materials are directly and selectively deposited would significantly facilitate the process, according to the Stanford team. 

 

 

Stacey Bent, Department of Chemical Engineering Chair and Jagdeep and Roshni Singh Professor in School of Engineering, Stanford University.(Picture from Stanford University)

 

“Our technology is a promising candidate for overcoming the challenges of top-down processing and misalignment because it greatly improves the ability to perform selective deposition of materials. This research introduces a novel processing method to meet the increasingly difficult materials challenges associated with new devices,” said Dr. Stacey Bent, Department of Chemical Engineering Chair and Jagdeep and Roshni Singh Professor in School of Engineering, Stanford University.

Link to Stacy Bent´s Research Group : http://bentgroup.stanford.edu/
 

Current approaches utilize lithography for nanoscale patterning. Using lithography and etching for fabrication of 2D or 3D structures often results in misaligned features and causes a risk of shorting or high resistant areas. However, selective deposition using ALD can reduce these risks and reduce the process time and steps.

Bent explained that selective deposition allows layers of material to be added onto a substrate only where desired without the need for additional lithography steps. However, the high level of selectivity needed for a manufacture-worthy process has not yet been achieved in area selective deposition studies. In addition, most methods for area selective deposition require long processing times.

The Stanford research has been focused on selective deposition of dielectric materials on metal/dielectric patterns. These type of structures can be found in interconnects and back-end-of-line (BEOL) processing. With ALD being used in other stages of the device fabrication process as well, the results from the Stanford experiments can potentially be applied to a variety of nanoscale electronic, optoelectronic and sensing devices.

The research developments occurred during the second year of research on the topic, and the Stanford team is continuing to explore new methods for area selective ALD to improve both selectivity and manufacturability.

“The Stanford team’s research has shown for the first time that, by following selective deposition of a dielectric material using pre-treatment by an inhibitory material, they can significantly reduce the process time (from 48 hours to less than 1 hour) and also improve the limits of selective deposition of dielectrics by more than 10 times,” said Kwok Ng, Senior Science Director of Nanomanufacturing Materials and Processes at SRC.

Area-Selective ALD : Conformal Coating, Subnanometer Thickness Control, and Smart Positioning

Area-Selective Atomic Layer Deposition: Conformal Coating, Subnanometer Thickness Control, and Smart Positioning

Ming Fang†§ and Johnny C. Ho*†‡§
† Department of Physics and Materials Science, City University of Hong Kong, 83 Tat Chee Avenue, Kowloon, Hong Kong
‡ State Key Laboratory of Millimeter Waves, City University of Hong Kong, 83 Tat Chee Avenue, Kowloon, Hong Kong
§ Shenzhen Research Institute, City University of Hong Kong, Shenzhen, 518057, P. R. China
ACS Nano, Article ASAP
DOI: 10.1021/acsnano.5b05249

 

 

Transistors have already been made three-dimensional (3D), with device channels (i.e., fins in trigate field-effect transistor (FinFET) technology) that are taller, thinner, and closer together in order to enhance device performance and lower active power consumption. As device scaling continues, these transistors will require more advanced, fabrication-enabling technologies for the conformal deposition of high-κ dielectric layers on their 3D channels with accurate position alignment and thickness control down to the subnanometer scale. Among many competing techniques, area-selective atomic layer deposition (AS-ALD) is a promising method that is well suited to the requirements without the use of complicated, complementary metal-oxide semiconductor (CMOS)-incompatible processes. However, further progress is limited by poor area selectivity for thicker films formed via a higher number of ALD cycles as well as the prolonged processing time. In this issue of ACS Nano, Professor Stacy Bent and her research group demonstrate a straightforward self-correcting ALD approach, combining selective deposition with a postprocess mild chemical etching, which enables selective deposition of dielectric films with thicknesses and processing times at least 10 times larger and 48 times shorter, respectively, than those obtained by conventional AS-ALD processes. These advances present an important technological breakthrough that may drive the AS-ALD technique a step closer toward industrial applications in electronics, catalysis, and photonics, etc. where more efficient device fabrication processes are needed.