University of Helsinki presents Self-Aligned Thin-Film Patterning by Area-Selective Etching of Polymers

A promising path to cut cost, scale, and reduce the environmental impact of semiconductor manufacturing

One of the driving costs in the high volume production of semiconductor components for especially powerful processors and memory chips is the patterning process. Both the capital investment in photolithographic equipment and the design cost add to the escalating cost going down to smaller nodes (see figure below). If one can reduce the number of lithographic mask layers needed in the production for a chip design one automatically cut the overall cost. Another problem is that while scaling down designs to smaller critical dimensions and tighter pitches and scaling up in the 3rd dimension like for 3D-NAND and coming 3D-DRAM it becomes more difficult to match the next mask layer with the previous one. The industry has solved this issue successfully for many years by introducing self-aligned processes like self-aligned contacts to the source, drain, and gate of the transistors below. Also, selective deposition processes like selective Epi and Cobalt CVD caps on copper are in production.

From an environmental view, lithography and mask more mask layers also consume more energy and clean water. Recent reports from Taiwan have it that both are problems, where drought has led to water shortages and the overall energy demand from fabs are high (about 5% of Taiwan total demand in 2019). 

Here, the University of Helsinki presents a process sequence for the future that is self-aligned and selective making it possible to mitigate all those problems in a very clever way for future devices and metallization schemes - please find all the details in the article below that is open source for download.

Self-Aligned Thin-Film Patterning by Area-Selective Etching of Polymers

by Chao Zhang, Markku Leskelä and Mikko Ritala *

Coatings 2021, 11(9), 1124; https://doi.org/10.3390/coatings11091124

Patterning of thin films with lithography techniques for making semiconductor devices has been facing increasing difficulties with feature sizes shrinking to the sub-10 nm range, and alternatives have been actively sought from area-selective thin film deposition processes. Here, an entirely new method is introduced to self-aligned thin-film patterning: area-selective gas-phase etching of polymers. The etching reactions are selective to the materials underneath the polymers. Either O2 or H2 can be used as an etchant gas. After diffusing through the polymer film to the catalytic surfaces, the etchant gas molecules are dissociated into their respective atoms, which then readily react with the polymer, etching it away. On noncatalytic surfaces, the polymer film remains. For example, polyimide and poly(methyl methacrylate) (PMMA) were selectively oxidatively removed at 300 °C from Pt and Ru, while on SiO2 they stayed. CeO2 also showed a clear catalytic effect for the oxidative removal of PMMA. In H2, the most active surfaces catalysing the hydrogenolysis of PMMA were Cu and Ti. The area-selective etching of polyimide from Pt was followed by area-selective atomic layer deposition of iridium using the patterned polymer as a growth-inhibiting layer on SiO2, eventually resulting in dual side-by-side self-aligned formation of metal-on-metal and insulator (polymer)-on-insulator. This demonstrates that when innovatively combined with area-selective thin film deposition and, for example, lift-off patterning processes, self-aligned etching processes will open entirely new possibilities for the fabrication of the most advanced and challenging semiconductor devices.

Schematics showing self-aligned polymer etching and the subsequent film patterning through area-selective deposition and lift-off processes. (Zhang et al Coatings 2021, 11(9), 1124, figure 1)

This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited

Semiconductor design and manufacturing: Achieving leading-edge capabilities, McKinsey LINK