XPoint NVM Array Process Engineering & Teardown

By Ed Korczynski, Sr. Technical Editor: Now that TECHINSIGHTS has published a teardown of a 3D XPoint array, we have seen cross-section transmission electron micrographs (TEM) of the device. From first principles of process engineering, we can make educated guesses as to the process flows and challenges in creating this type of non-volatile memory (NVM) integrated circuit (IC). Evolution of device technology over more than fifteen years has resulted in cross-point arrays connecting precise stacks of chalcogenide materials. Intel with “Optane” and Micron with “QuantX” branded ICs can now claim success in commercializing what has always looked good in R&D but was notoriously difficult to make in high-volume manufacturing (HVM).

Figure 1 shows the TEM cross-section, parallel to the wordline direction, of a XPoint memory cell array taken from an Intel Optane product. There are two levels of cross-point cell-stacks, connected in the middle by bitlines (orthogonal to the wordlines). The upper- and lower-wordlines have been analyzed as tungsten (W) metal with tungsten-nitride (WN) barriers. The memory cell material is a variant on a germanium-antimony-teluride (GeSbTe or “GST”) chalcogenide glass, while the selector material is made with arsenic-silicon-germanium-selenide.

Fig. 1: Cross-section TEM of Intel XPoint NVM array in the wordline direction, showing two levels of memory cell stacks separated by bitline arrays. (Source: greyscale image by TechInsights, color commentary by Ed Korczynski)

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