Friday, January 7, 2022

TSMC Self-Aligned Via Process Development for Beyond the 3nm Node

Semiwiki Tom Dillinger reports on an interesting paper by TSMC at the recent IEDM 2021 conference in San Francisco using selective ALD with the help of SAMs or Dielectric on Dielectric (DOD) as it is called.




From the article sumary: Continued interconnect scaling below the 3nm node will necessitate unique process development research to maintain electrical and reliability specs in the presence of (up to 4nm) overlay error. The need for low-K interlevel dielectrics is a given – yet, the via etch in these materials is not especially tolerant of EPE.

TSMC has demonstrated a potential process flow for a “self-aligned via” with an additional DoD material. The etch rate differential of the DoD results in more robust via-to-adjacent metal reliability. This process flow utilizes two unique steps – the SAM of a blocking material on metal surfaces, and the selective ALD of a dielectric-on-dielectric.

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