Friday, July 23, 2021

PlasticARM - A natively flexible 32-bit Arm microprocessor using ALD

Woah - PlasticARM 32-bit microprocessor using ALD and other thin film deposition techniques on a flexible substrate.

A natively flexible 32-bit Arm microprocessor using ALD

John Biggs, James Myers, Jedrzej Kufel, Emre Ozer, Simon Craske, Antony Sou, Catherine Ramsdale,
Ken Williamson, Richard Price & Scott White
Nature volume 595, pages532–536 (2021)

Abstract: Nearly 50 years ago, Intel created the world’s first commercially produced microprocessor—the 4004, a modest 4-bit CPU (central processing unit) with 2,300 transistors fabricated using 10 μm process technology in silicon and capable only of simple arithmetic calculations. Since this ground-breaking achievement, there has been continuous technological development with increasing sophistication to the stage where state-of-the-art silicon 64-bit microprocessors now have 30 billion transistors (for example, the AWS Graviton2 microprocessor, fabricated using 7 nm process technology). The microprocessor is now so embedded within our culture that it has become a meta-invention—that is, it is a tool that allows other inventions to be realized, most recently enabling the big data analysis needed for a COVID-19 vaccine to be developed in record time. Here we report a 32-bit Arm (a reduced instruction set computing (RISC) architecture) microprocessor developed with metal-oxide thin-film transistor technology on a flexible substrate (which we call the PlasticARM). Separate from the mainstream semiconductor industry, flexible electronics operate within a domain that seamlessly integrates with everyday objects through a combination of ultrathin form factor, conformability, extreme low cost and potential for mass-scale production. PlasticARM pioneers the embedding of billions of low-cost, ultrathin microprocessors into everyday objects.

a, The SoC architecture, showing the internal structure, the processor and system peripherals. The processor contains a 32-bit Arm Cortex-M CPU and a Nested Vector Interrupt Controller (NVIC), and is connected to its memory through the interconnect fabric (AHB-LITE). Finally, the external bus interface provides a General-Purpose Input-Output (GPIO) interface to communicate off-chip with the test framework. b, Features of the CPU used in PlasticARM compared to those of the Arm Cortex-M0+ CPU. Both CPUs fully support Armv6-M architecture with 32-bit address and data capabilities and a total of 86 instructions from the entire 16-bit Thumb and a subset of 32-bit Thumb instruction set architecture. The CPU microarchitecture has a two-stage pipeline. The registers are in the CPU of the Cortex-M0+, but in the PlasticARM the registers are moved to the latch-based RAM in the SoC to save the CPU area of the Cortex-M. Finally, both CPUs are binary compatible with each other and to other CPUs in the same architecture family. c, The die layout of PlasticARM, denoting the key blocks in white boxes such as the Cortex-M processor, ROM and RAM. d, The die micrograph of PlasticARM, showing the dimensions of the die and core areas. From: A natively flexible 32-bit Arm microprocessor

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