Monday, August 31, 2015

Japanese researchers provide record low Dit in ALD Al2O3/La2O3/InGaAs gate stacks

InGaAs is one of the most promising III/V semiconductor materials for n-channel MOSFETs because of its extremely high electron mobility of ∼13 800 cm2/V s. However, there  is a major issue with InGaAs not having a high quality native oxide like Silicon resulting in a high interface state density at InGaAs MOS interfaces degrades the MOSFET performance because of Ga dangling bonds and/or As-As dimers created during the oxidation process at InGaAs surfaces. It has been reported that the passivation of trivalent oxides such as Gd2O3 or Al2O3 with InGaAs surfaces can eliminate such dangling bonds and dimers because of the abrupt and chemical-bond-well-arranged interface between the trivalent oxides and InGaAs.

TEM image of Au/AlO (3.5 nm)/LaO (0.4 nm)/InGaAs gate stacks. Citation: J. Appl. Phys. 118, 085309 (2015);

ALD HfO2 has already been introduced at 45 nm CMOS and is still the dominating high-k material in high performance CMOS including recent Si FinFET technologies. Therefore, many have chosen to combine HfO with the AlO/InGaAs structure by continuously ALD has been employed for CET scaling. Thin CET of ∼1.08 nm and low of ∼5 × 1012 cm−2 eV−1 have been realized in the HfO/AlO/InGaAs gate stacks.

Another high-k that has commonly been used and is used e.g. as a dopant in the IBM Alliance 28 nm planar CMOS technology is LaO, which is also trivalent oxide. It has been shown on InGaAs that La2O3 can further improve the MOS interface quality by the formation of Ga-O-La and In-O-La bonds. [ref]

In a very good study presented below by University of Tokyo, JST-CREST and Sumitomo Chemicals a high quality LaO films were deposited on InGaAs by ALD. It was found that the LaO/InGaAs interfaces provide recorded-low of ∼3 × 1011 cm−2 eV−1 as the InGaAs MOS interfaces, which is attributable probably to the intermixing reaction between LaO and InGaAs. It is concluded, as a result, that the AlO/LaO/InGaAs gate stacks can realize lower than in the conventional AlO/InGaAs MOS interfaces with maintaining small hysteresis and low gate leakage by optimizing the thickness of AlO and LaO.

For me now some questions remains - why not combine the best of the best in one stack, i.e., HfO2/La2O3/InGaAs? Perhaps with only a slight touch of blend with Al2O3. Another question that worries me when reading HKMG InGaAs papers is the very low thermal budget that has to be used.  The first high-k layer is deposited at 150 deg. C not destroy the super sensitive InGaAs interface. Most high-k materials needs to be deposited in the ranger 250 to 300 deg.C in order to perform at its best in addition PDAs or PMAs will bring out even more out of the material. Here and in other studies that I have seen a PMA of only 300 deg. C is used. Just imagine bringing this stack on to a silicon based channel material and it will not perform too much better than old poly/SiON with respect to CET / Leakage performance. I guess in the end it is all about the higher mobility given by a III/V channel. It just hurts every time seeing all these smart guys using a relatively low performing high-k.

Please find the OPEN ACCESS publication below!

Impact of La2O3 interfacial layers on InGaAs metal-oxide-semiconductor interface properties in Al2O3/La2O3/InGaAs gate stacks deposited by atomic-layer-deposition [OPEN ACCESS]

C.-Y. Chang, O. Ichikawa, T. Osada, M. Hata, H. Yamada, M. Takenaka and S. Takagi 
J. Appl. Phys. 118, 085309 (2015);

(a) of the AlO (3.5 nm)/LaO/InGaAs gate stacks as a parameter of the LaO ALD cycle numbers, and (b) the LaO ALD cycle number dependence of of AlO (3.5 nm)/LaO/InGaAs at the surface energy of 0.1 eV from midgap ( ). Citation: J. Appl. Phys. 118, 085309 (2015);

We examine the electrical properties of atomic layer deposition (ALD) LaO/InGaAs and AlO/LaO/InGaAs metal-oxide-semiconductor (MOS) capacitors. It is found that the thick ALD LaO/InGaAs interface provides low interface state density ( ) with the minimum value of ∼3 × 1011 cm−2 eV−1, which is attributable to the excellent LaO passivation effect for InGaAs surfaces. It is observed, on the other hand, that there are a large amount of slow traps and border traps in LaO. In order to simultaneously satisfy low and small hysteresis, the effectiveness of AlO/LaO/InGaAs gate stacks with ultrathin LaO interfacial layers is in addition evaluated. The reduction of the LaO thickness to 0.4 nm in AlO/LaO/InGaAs gate stacks leads to the decrease in hysteresis. On the other hand, of the AlO/LaO/InGaAs interfaces becomes higher than that of the LaO/InGaAs ones, attributable to the diffusion of AlO through LaO into InGaAs and resulting modification of the LaO/InGaAs interface structure. As a result of the effective passivation effect of LaO on InGaAs, however, the AlO/10 cycle (0.4 nm) LaO/InGaAs gate stacks can realize still lower with maintaining small hysteresis and low leakage current than the conventional AlO/InGaAs MOS interfaces.

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