AlixLabs to Demonstrate APS™ on 300-millimeter UMC wafers at the 2025 CMC Conference

Atomic Layer Etching Pitch Splitting (APS) proven on more industry-leading wafers, doubling fin density and proving flexibility without EUV.

Austin, TX, USA/Stockholm, Sweden – April 10th, 2025 – AlixLabs AB, a Swedish semiconductor startup specializing in Atomic Layer Etching (ALE), today demonstrates the latest in its line of groundbreaking development in advanced chip fabrication unveiling additional research into its novel semiconductor manufacturing process known as APS™ (Atomic Layer Etching Pitch Splitting) capable of doubling fin density while introducing the unprecedented flexibility to vary pitch and critical dimensions within the same wafer area.

Proven on 300-millimeter wafers provided by United Microelectronics Corporation (UMC), the APS™ technology successfully halved pitch compared to current industry benchmarks. This significant advancement was achieved entirely without relying on expensive and energy-intensive Extreme Ultraviolet (EUV) lithography.

Instead, APS™ leverages advanced etching techniques that substantially enhance sustainability, drastically reducing energy consumption without compromising throughput. Previous demonstrations of the APS™ process, validated through Intel’s Test Vehicle Program[1], confirmed its potential by achieving metal pitches as small as 25 nanometers.

“Today we are sharing more proof that the APS™ process can be a game changer for leading foundries. Thanks to UMC, we have been able to verify our process on production wafers that are shipped in quantities measured in millions of wafers annually,” said Dr. Robin Athle, Principal Researcher at AlixLabs. “Our mission is to create equipment that allows companies that don’t have access to EUV tools to scale down their production to 5 nanometer and beyond. By eliminating the dependency on EUV lithography, we are offering the industry a path towards more sustainable and economically feasible high-density chip production.”

Detailed results from AlixLabs’ UMC wafer tests and further insights into APS™ technology will be presented at the 2025 CMC Conference, scheduled for April 10th in Austin, Texas. Dr. Athle’s presentation “Atomic Layer Etching Pitch Splitting (APS™): a New Alternative to Multi Patterning” will be held at 4:00 PM at the Bergstrom Ballroom in Hilton Austin Airport Hotel.

AlixLabs Demonstrates 3 nanometers on Intel Silicon – Without EUV

The Swedish semiconductor company has fabricated leading-edge structures without using complex and costly lithography techniques.

The Swedish semiconductor company AlixLabs announces that it has used its technology to etch structures equivalent to commercial 3-nanometer circuits on Intel test silicon. Notably, this has been achieved without the use of extreme ultraviolet lithography (EUV) or advanced multi-patterning techniques such as SADP and SAQP (Self-Aligned Double Patterning and Self-Aligned Quad Patterning, respectively).

AlixLabs, a startup based in Lund, specializes in the development of Atomic Layer Etching (ALE), a type of plasma-based dry etching for cutting-edge structures, and ALE Pitch Splitting (APS), which enables transistor fins to be split using etching. The advantage of this approach is that it significantly reduces costs at the cutting edge, where wafer prices skyrocket with each new generation.

"We are pleased to demonstrate how APS can help the industry reduce its dependence on multi-patterning while lowering costs and environmental impact. Our technology enables the fabrication of sub-10-nanometer structures on silicon, and through Intel’s Test Vehicle Program, we have proven that sub-5-nanometer structures can be achieved using etching alone."

– Dmitry Suyatin, CTO and Co-Founder of AlixLabs

According to Dmitry Suyatin, AlixLabs’ CTO, this demonstration was made possible through Intel’s Test Vehicle Program, which provided test silicon for AlixLabs to process with its APS technology. While ALE has traditionally been limited to structures in the 10-nanometer class, AlixLabs' APS technique has significantly simplified the manufacturing of structures smaller than 5 nanometers.

Etching 3-nanometer-class structures without advanced EUV lithography, using only immersion lithography, is a significant breakthrough—provided the technology can be scaled and applied in practical manufacturing. AlixLabs has previously stated its goal of seeing its technology adopted by TSMC and Samsung for their 2-nanometer processes.

Since the industry moved past the 28-nanometer node, multi-patterning has become increasingly necessary to create smaller structures and transistors. This lithographic technique involves breaking down complex patterns into simpler ones and sequentially patterning them onto the silicon wafer for higher precision and detail. Lithography can perform this in two, three, or four steps (SADP, SAQP), though more steps are theoretically possible, they are considered too complex and costly for practical use at smaller nodes.

"APS technology demonstrates that complex multi-patterning techniques such as SADP and SAQP are not needed to manufacture circuits at 5 nanometers and below. This increases the potential to use immersion lithography for critical mask layers in 3-nanometer processes. These results were achieved with our early Alpha equipment, and Beta equipment will follow later in 2025. We thank Intel for enabling this demonstration and providing high-quality test silicon."

– Jonas Sundqvist, CEO and Co-Founder of AlixLabs

While lithographic multi-patterning is often necessary, it comes with several downsides. Each additional step requires more masks, which must be precisely aligned to form the final, complex pattern. Even a slight misalignment can lower yield and performance, but more importantly, it significantly extends production time. Avoiding multi-patterning whenever possible is therefore always preferable.

It is essential to distinguish between "nanometer-class" structures and actual physical nanometer measurements. What AlixLabs has achieved is a metal pitch (the distance between metal interconnects connecting transistor gates) of 25 nanometers through dry etching. This compares to TSMC’s most advanced 3-nanometer process, which achieves a metal pitch as low as 23 nanometers in certain high-density configurations.

AlixLabs highlights this test silicon as a major milestone towards commercialization and announces that more updates will follow later in 2025. Additional details will be presented by CTO Dmitry Suyatin at SPIE Advanced Lithography + Patterning in San Jose, California, on February 27, from 9:00–9:20 AM (local time).

Sources:

AlixLabs demonsterar 3 nanometer på Intel-kisel – utan EUV – Semi14

AlixLabs to Showcase Latest APS™ Findings at SPIE Advanced Lithography + Patterning – AlixLabs

Browse the 2025 program for SPIE Advanced Lithography + Patterning

Lam Research’s Dry Resist: A Breakthrough in EUV Lithography for Next-Generation Logic and Memory Manufacturing

Lam Research’s dry resist technology represents a major shift in EUV lithography and semiconductor patterning, addressing critical challenges such as stochastic defectivity, resolution limitations, and cost-efficiency. With recent qualifications for advanced DRAM and 2nm logic manufacturing, along with a growing ecosystem for high-volume production, dry resist is positioned to disrupt traditional chemically amplified resists (CARs) and enable future High-NA EUV adoption.

One of the most significant recent developments is Lam’s qualification of dry resist for 28nm pitch BEOL logic at 2nm and below in collaboration with imec. This qualification confirms that dry resist can eliminate multi-patterning steps, reducing complexity and improving EUV throughput. The process is designed to work with both low-NA and high-NA EUV scanners, ensuring its relevance for sub-2nm logic scaling. This represents a key milestone in extending direct EUV printing to future logic nodes, an approach that could significantly lower lithography costs while improving pattern fidelity.

In addition, a leading DRAM manufacturer has selected Lam’s Aether dry resist technology as its production tool of record for advanced DRAM nodes. This decision highlights dry resist’s low-defect, high-fidelity patterning capabilities, which are essential for scaling memory architectures. The technology enables lower exposure doses while reducing stochastic defects, which are a major concern in EUV-based DRAM production. Given that Samsung, SK Hynix, and Micron are all increasing their reliance on EUV for next-generation DRAM, Lam’s dry resist is well-positioned for widespread adoption in the memory sector.

To ensure a stable supply chain for dry resist materials, Lam Research has partnered with Entegris and Gelest, a Mitsubishi Chemical Group company. This collaboration ensures reliable dual-source precursor production, providing chipmakers with long-term process stability. The partnership also focuses on the development of next-generation high-NA EUV precursors, further strengthening dry resist’s role in future sub-2nm manufacturing.

SEM images of 28 nm pitch line/space patterns imaged with 0.33NA EUV in dry resist from Entegris precursor.

A critical enabler of dry resist technology is its atomic layer deposition (ALD) process, which replaces traditional spin-coating used in CARs. ALD-based vapor-phase deposition offers higher uniformity, eliminating polymer chain variations found in conventional resists. It also allows precise thickness control, which is essential for optimizing EUV photon absorption and etch selectivity. Unlike CARs, which rely on a complex mixture of polymers, dry resist materials are based on single-component metal-organic precursors such as organo-tin oxides. These materials provide higher EUV photon absorption, improving sensitivity and pattern resolution.

Another key advantage of dry resist is its anisotropic dry development process, which replaces wet solvent-based development. Traditional CAR-based EUV resists require organic solvents or aqueous bases, leading to stochastic defects, material loss, and waste. Dry resist, by contrast, is developed entirely in the gas phase, selectively removing unexposed regions and forming a negative-tone image. This eliminates line collapse and delamination issues, improving yield stability. Additionally, the elimination of wet chemistries significantly reduces chemical waste, making dry resist a more sustainable solution with five to ten times lower material consumption compared to traditional resists.

Lam’s dry resist technology is poised to disrupt traditional CAR-based EUV lithography, particularly as the industry moves toward High-NA EUV adoption. By reducing multi-patterning dependency, the technology enhances cost-effective EUV scaling, making it an attractive solution for both logic and memory manufacturers. This positions Lam as a key leader in next-generation EUV resist solutions, challenging conventional resist suppliers like JSR, TOK, and Inpria.

From a sustainability perspective, dry resist significantly lowers EUV exposure dose requirements, leading to higher scanner throughput and lower energy consumption. Its reduced defectivity translates to higher yield per wafer, further enhancing cost-efficiency. The collaboration with Entegris and Gelest ensures supply-chain stability, making dry resist a viable and scalable technology for sub-2nm nodes.

The patent US20220020584A1 mentions several Lam Research tools that play a role in the dry resist deposition, patterning, and development process for EUV lithography. The Altus system is referenced for deposition, likely for metal or dielectric films in the dry resist stack, while the Striker plasma-enhanced atomic layer deposition (PEALD) system may be used for precise resist or underlayer deposition. The Versys platform, known for plasma processing, is relevant to the dry development process, and the Syndion system, typically used for deep silicon etching, may have applications in pattern transfer. Additionally, the Reliant tool is designed for volume manufacturing, possibly adapted for integrating dry resist technology, and the Kiyo plasma etch system is likely involved in etching after the dry resist development stage. These tools collectively enable Lam’s dry resist process to achieve improved resolution, defect reduction, and cost efficiency in advanced EUV lithography.

The patent US20220020584A1, filed by Lam Research Corporation, describes an innovative dry development process for EUV photoresists, which eliminates the need for traditional wet chemical development methods. The patent details a dry resist system deposited via vapor-phase precursors, forming a highly uniform, single-component material that enhances EUV photon absorption and sensitivity. The dry development process selectively removes unexposed resist regions using plasma-based or plasma-free chemical methods, significantly reducing line collapse and defectivity while improving resolution at sub-2nm nodes. By integrating dry resist deposition, EUV exposure, and dry development into a single cluster tool, the patented technology enables scalable, high-volume EUV manufacturing with lower chemical consumption and improved process sustainability, positioning it as a key enabler for High-NA EUV lithography.

Lam Research’s dry resist technology represents a significant development in EUV lithography by addressing key challenges in stochastic defectivity, process cost, and sustainability. Its qualification for 2nm logic and advanced DRAM manufacturing confirms its readiness for high-volume production. By utilizing ALD for precise resist deposition and securing a stable precursor supply through partnerships with Entegris and Gelest, Lam has established a strong foundation for scaling the technology. 

Sources:

Lam Research Press Release on DRAM Adoption (Jan 2025): Lam Research

imec Qualification of Dry Resist for 2nm Logic (Jan 2025): imec

Entegris and Gelest Collaboration Announcement (July 2022): Entegris

Overview of Dry Resist ALD and Precursor Chemistry: SemiAnalysis

ASML High-NA EUV Roadmap and Implications for Dry Resist: ASML

Lam Reserach patent application US20220020584A1: US20220020584A1.pdf

Intel Unveils 6 nm Gate Length Silicon RibbonFET CMOS and Breakthroughs in Semiconductor Scaling at IEDM 2024

Intel Corporation / Intel Foundry has demonstrated and extensively characterized gate-all-around Silicon RibbonFET CMOS transistors with a 6 nm gate length (LG). The study showcases nanoribbon silicon thickness (Tsi) scaling down to 3 nm, enhancing short-channel effects without compromising performance. Effective workfunction engineering mitigates threshold voltage increases caused by quantum confinement at scaled Tsi, enabling reduced threshold voltage at highly scaled gate lengths. Injection velocity of 1.13x10^7 cm/s is maintained at LG=6nm without degradation down to Tsi=3 nm, highlighting advancements crucial for continued gate length scaling and the ongoing realization of Moore's Law.

Intel Foundry made groundbreaking announcements at the IEEE International Electron Devices Meeting (IEDM) 2024, showcasing advancements that propel semiconductor technology into the next decade and beyond. Highlights include innovations in transistor and interconnect scaling, advanced packaging, and emerging materials to support the industry’s roadmap toward achieving 1 trillion transistors on a chip by 2030. Intel demonstrated a 25% capacitance reduction using subtractive ruthenium for interconnections, achieved a 100x throughput improvement in advanced packaging through Selective Layer Transfer (SLT), and advanced gate-all-around (GAA) transistor scaling with Silicon RibbonFET CMOS at a 6 nm gate length. Additionally, Intel unveiled new work on gate oxide modules for scaled 2D FETs, addressing the next phase of GAA scaling.

Among the key technical breakthroughs, subtractive ruthenium stands out as a metallization alternative to copper for interconnects, offering significant capacitance reductions at tight pitches while being cost-effective and scalable for high-volume manufacturing. SLT further revolutionizes advanced packaging with ultra-fast, flexible chip-to-chip assembly, enabling smaller, higher-density chiplets for AI and other demanding applications. For transistor scaling, Intel’s demonstration of Silicon RibbonFET CMOS at 6 nm gate length delivers industry-leading short-channel effects and performance, paving the way for continued scaling under Moore’s Law. Additionally, Intel’s progress with 2D GAA NMOS and PMOS transistors and gate oxide development signals readiness for post-silicon semiconductor technologies.

Intel also highlighted progress in gallium nitride (GaN) technology, demonstrating the first 300 mm GaN-on-TRSOI substrates for high-performance power and RF electronics. These developments, alongside Intel’s continued focus on advanced memory integration, hybrid bonding, and modular system expansion, underscore its commitment to addressing challenges in AI, energy efficiency, and thermal management. With these innovations, Intel Foundry continues to lead the charge in semiconductor advancements, ensuring a robust path forward for the trillion-transistor era.

Source: Intel IEDM 2024 Innovations

New Method for Precision Doping in 2D Semiconductors Enables Next-Gen CMOS Integration

Researchers have achieved a breakthrough in doping two-dimensional (2D) semiconductors, paving the way for monolithic integration of p-type and n-type semiconductor channels on a single chip. This development holds promise for advancing complementary CMOS technology, allowing further transistor scaling and efficient interlayer connections.

The study focuses on 2H-MoTe2, a van der Waals material, and employs a precise substitutional doping technique. Unlike conventional methods such as ion implantation—which do not work well with 2D materials—this approach allows the targeted introduction of niobium (Nb) for p-type doping and rhenium (Re) for n-type doping, using a magnetron co-sputtering method followed by chemical vapor deposition (CVD). By precisely adjusting the concentration of these dopants, researchers produced wafer-scale films with consistent carrier properties, even enabling spatial control of the doped regions. This advance allows for the patterning of p-type and n-type channels on the same wafer in a single growth process, which is essential for CMOS device fabrication.

Using this novel technique, the team created a large-scale 2D CMOS inverter array that achieved impressive performance metrics. For instance, a typical inverter from this array demonstrated a voltage gain of 38.2 and low static power consumption, key parameters for efficient CMOS operation. The new doping method also exhibits high uniformity and reliability, essential for scaling up 2D materials in commercial semiconductor applications.

This innovation in 2D semiconductor doping introduces a promising pathway for integrating materials like 2H-MoTe2 into very-large-scale integration (VLSI) technology, further driving forward Moore's Law and the miniaturization of semiconductor devices.

Figure 1 from paper, Pan, Y., Jian, T., Gu, P. et al. Precise p-type and n-type doping of two-dimensional semiconductors for monolithic integrated circuits. Nat Commun 15, 9631 (2024). https://doi.org/10.1038/s41467-024-54050-2

Experimental

In the study, co-sputtering and CVD is used to create large-scale, precisely doped 2D 2H-MoTe2 films by transforming a molybdenum film doped with niobium or rhenium into 2H-MoTe2 through a process called tellurization. Here’s a breakdown of how this process works:

Preparation of the Mo Film: Initially, thin Mo films are deposited on a silicon/silicon dioxide (Si/SiO2) substrate using magnetron co-sputtering. During this step, controlled amounts of Nb (for p-type doping) or Re (for n-type doping) are co-sputtered with the Mo film, resulting in a doped Mo layer.

Tellurization Process in the CVD Reactor: The Mo film, now doped with Nb or Re, is placed in a CVD furnace along with solid tellurium (Te) lumps. Under a controlled flow of carrier gases (argon and hydrogen), the CVD chamber is heated to high temperatures (around 650°C). The Te vapor reacts with the Mo, leading to the formation of 1T'-MoTe2.

Phase Transformation to 2H-MoTe2: At the elevated temperatures within the CVD system, the 1T'-MoTe2 structure undergoes a phase transformation into the more stable 2H phase, producing the final doped 2H-MoTe2 film. This phase is crucial because 2H-MoTe2 has semiconducting properties suitable for integrated circuits.

Doping Incorporation: During the CVD tellurization, Nb and Re atoms from the initial Mo film become substitutionally incorporated into the MoTe2 lattice. This incorporation determines the semiconductor type (p-type or n-type) and carrier concentration of the resulting 2H-MoTe2 film.

Large-Scale Uniformity: By controlling the initial dopant concentration and maintaining consistent conditions in the CVD process, the researchers achieved uniform doping across large-scale wafers, crucial for creating reliable semiconductor devices.

Source: Precise p-type and n-type doping of two-dimensional semiconductors for monolithic integrated circuits | Nature Communications

Intel Sets Record with 2D TMD Transistors for Next-Gen Electronics

Intel researchers have achieved record-breaking performance in transistors using ultra-thin 2D transition metal dichalcogenides (TMDs) like MoS₂ and WSe₂ as channels. These monolayer materials are ideal for scaled devices but present challenges in integration due to their lack of atomic “dangling bonds.” By developing a specialized gate oxide atomic layer deposition (ALD) process and low-temperature gate cleaning, Intel built GAA NMOS and PMOS transistors with record subthreshold slopes and high drain currents. Specifically, they achieved a subthreshold slope of <75 mV/dec and Idmax >900 µA/µm in MoS₂ NMOS transistors, and a slope of 156 mV/dec with Idmax = 132 µA/µm in WSe₂ PMOS devices. These advancements highlight the promise of 2D TMDs for next-gen electronics and the need for further research to overcome integration challenges.

The images above are TEM characterizations of the record GAA NMOS device across the gate, showing a healthy, conformal GAA architecture with 43nm-wide monolayer MoS2 channel and conformal HfO2 with a thickness of ~4.0nm.

Record Performance with 2D Channels: Ultra-thin transition metal dichalcogenides (TMDs), such as MoS2 and WSe2, are called monolayer, or 2D, materials because they’re one just atomic layer thick. They are being extensively studied for use as the channel in extremely scaled devices because of their excellent electrical performance. However, interfacing them with other materials in a device structure is difficult because at the atomic level there are no available “dangling bonds” to use. Thus, 2D channels have been a challenge to optimize.

Intel researchers will describe how they used 1) a unique gate oxide atomic layer deposition (ALD) process and 2) a low-temperature gate cleaning process to build GAA devices that demonstrated breakthrough performance for MoS2- and WSe2-based GAA NMOS and PMOS transistors, respectively. This includes record subthreshold slope (<75mv/dec) and drain current (Idmax>900 µA/µm at <50nm gate length) in sub-1nm-thick monolayer MoS2 GAA NMOS transistors. Also, using ruthenium (Ru) source and drain (S/D) contacts, they achieved record subthreshold slope (156mV/dec) and drain current (Idmax = 132µA/µm) in a ~30nm gate-length WSe2 PMOS device. The researchers say these results both underscore the potential of 2D TMDs for use in next-generation electronics, and highlight the critical need for continued research to address the remaining scientific and technological challenges.

Sources:

https://www.ieee-iedm.org/press-kit

(Paper #24.3, “Gate Oxide Module Development for Scaled GAA 2D FETs Enabling SS<75mV/d and Record Idmax>900µA/µm at Lg<50nm,” W. Mortelmans et al, Intel)

AlixLabs Qualifies APS™ for Use In 300-millimeter Silicon Wafer Designs

Swedish semiconductor startup clears technical hurdle for leading-edge process use on 300 mm wafer design*.

Scanning electron microscopy (SEM) images of amorphous silicon lines before (top) and after the APSTM process: nominal 40 nm line width and 40 nm half-pitch converted to lines with width below 15 nm and a half-pitch of 20 nm. Bild: Alixlabs

Stockholm, Sweden – September 12th, 2024 – AlixLabs AB, a Swedish semiconductor startup specializing in Atomic Layer Etching (ALE), announces that it has qualified its APS™ (ALE Pitch Splitting) process on a 300-millimeter silicon wafer design, marking one of its final steps towards commercial adoption. APS™ provides atomic-scale precision and pattern fidelity with critical dimensions below 15 nanometers for both single crystalline and amorphous silicon.

AlixLabs APS™ is designed to reduce the cost of leading-edge manufacturing, sub-7-nanometer, where feature sizes of less than 20 nanometers are required. An estimated cost saving of up to 40 percent per mask layer can be achieved with APS™ rather than relying on EUV lithography, and complex self-aligned multi patterning schemes.

AlixLabs' patented and wordmarked APS™ IP – short for Atomic Layer Etch (ALE) Pitch Splitting, here demonstrated in a simple animation.

“Proving that APS™ works on lithography designs on 300-millimeter wafers, is what we’ve all worked on since we founded AlixLabs in 2019,” says CEO and co-founder Dr. Jonas Sundqvist. “Not only do we aim to provide chip manufacturers wafer processing equipment that can create 20-nanometer half-pitch lines and critical dimension below 15 nanometers on silicon, we aim to do that at a lower cost and a more sustainable way than other technologies”

“We are also able to provide record breaking 3-nanometer critical dimension features on gallium phosphide (GaP) wafers today showing that APS™ can scale far into the future beyond what is needed today,” adds CTO and co-founder Dmitry Suyatin.

APS™ is positioned as an alternative to self-aligned double and quadruple patterning (SADP and SAQP). It allows for splitting dense line structures that can act as a foundation for transfer-etch into various materials such as dielectrics, metals, metal nitrides, and high-k dielectrics. The structures created with APS™ can also be used as-is for critical device features such as the fins in FinFET-type transistors due to extremely low surface damage.

AlixLabs’ goal is to supply leading semiconductor manufacturers, in both logic and memory segments. By enabling them to simplify and speed up their chip production at least fourfold for each critical mask layer by replacing four plasma wafer processing chambers in the SADP process flow with one APS™ chamber and eightfold correspondingly in SAQP. Finally, AlixLabs contributes overall to more sustainable semiconductor manufacturing.

*EBL patterned 300 mm wafers were provided by Fraunhofer IPMS Center Nanoelectronic Technologies (CNT) and financed by Ascent+ European Union's Horizon 2020 research and innovation program under GA No 871130.

Sources:

www.alixlabs.com

ASML Unveils Hyper-NA EUV: Pioneering New Frontiers in Chip Innovation and Efficiency

ASML, the leader in lithography technology for semiconductor manufacturing, has launched its latest breakthrough: the Hyper-NA EUV tool and Intel being the first customer getting its first machine earlier this year. This leading-edge technology, which boosts the numerical aperture (NA) from 0.55 to 0.75, is poised to revolutionize chip design by enabling unprecedented levels of transistor density. Scheduled for introduction around 2030, Hyper-NA promises to extend the capabilities of chipmakers far beyond current limits, opening up new possibilities for intricate and powerful chip designs.

The presentation announcing ASML's Hyper-NA EUV technology was delivered by the company's former president, Martin van den Brink, at imec's ITF World event in Antwerp. 

Reduction in Double Patterning Complexity: Hyper-NA EUV technology simplifies the lithography process by reducing the need for double patterning, i.e., like Litho-Etch-Litho-Etch (LELE) etc., a method that involves aligning two masks perfectly to create intricate chip designs. By providing higher resolution and precision, Hyper-NA EUV minimizes the challenges and costs associated with double patterning, streamlining production and enhancing overall efficiency for chipmakers. However, there are a myriad of multi-patterning technologies deployed out there and SMIC, the main Chinese foundry, is reportedly using sextuple-patterning for its 5 nm technology.

Hyper-NA EUV technology is designed to significantly increase the productivity of semiconductor manufacturing, enabling the processing of 400 to 500 wafers per hour. This improvement will help chipmakers meet the growing demand for high-performance chips more efficiently, reducing production time and costs while maintaining high precision and quality.

The adoption of Hyper-NA EUV presents a myriad of opportunities for the semiconductor industry. As Intel has already installed the first High-NA systems, showcasing the potential of these advanced tools to enhance processor performance. As other industry leaders like TSMC, Samsung, Micron, and SK Hynix explore the adoption of High-NA and eventually Hyper-NA, the competitive landscape is set for a dynamic transformation. Innovations such as advanced polarizers to overcome light polarization issues and improvements in resist materials and etch selectivity will enable more precise and efficient chip manufacturing.

ASML’s Hyper-NA EUV technology is not just a short-term solution but part of a long-term roadmap that will sustain chip innovation for the next decade and beyond. Collaborative research and development efforts, including Imec’s simulations and Zeiss’s lens designs, highlight the cooperative spirit driving this technological advancement. As chip designers like Nvidia, Apple, and AMD leverage these tools at leading foundries such as TSMC, the future of chip design looks brighter than ever, promising enhanced productivity, technological leadership, and sustained growth. Hyper-NA EUV is set to redefine what is possible in the world of semiconductors, driving the industry towards new heights of efficiency and performance.

Sources: ASML Aims for Hyper-NA EUV, Shrinking Chip Limits - EE Times

Intel Receives ASML's First High-NA EUV Lithography Scanner, Pioneering Next-Gen Semiconductor Manufacturing

ASML has delivered its groundbreaking High-NA EUV lithography scanner, the Twinscan EXE:5000, to Intel Oregon. Marking a significant technological leap, this first-of-its-kind scanner boasts a 0.55 NA lens, enabling 8nm resolution for advanced semiconductor manufacturing. Designed for process technologies beyond 3nm, it promises to enhance chip production efficiency and reduce costs. Intel's early adoption of this state-of-the-art equipment, valued between $300-$400 million, positions them at the forefront of the industry, potentially setting new standards in High-NA manufacturing. This development represents a major milestone in semiconductor technology, signaling a new era of innovation and capability in chip production.

TSMC Set to Revolutionize Chip Technology with Trillion-Transistor Packages by 2030

In a groundbreaking announcement at IEDM, TSMC has unveiled ambitious plans to develop chip packages harboring over one trillion transistors and monolithic chips with more than 200 billion transistors by 2030. This visionary goal is set to be achieved through the development of advanced production nodes, including 2nm-class N2 and N2P, and even finer 1.4nm-class A14 and 1nm-class A10 processes. Despite the slowdown in process technology development and existing technical and financial challenges, TSMC remains optimistic about accomplishing these targets within the next five to six years. The company, renowned as the world's largest semiconductor foundry, is confident in overcoming industry hurdles to bring these complex, multi-chiplet systems and more intricate monolithic chips to the forefront of technology. This development signals a significant leap in chip architecture, promising transformative advancements in the tech industry.

Source:

https://www.kitguru.net/channel/generaltech/joao-silva/tsmc-expects-to-create-chip-packages-with-over-1-trillion-transistors-by-2030/

Intel Showcases Groundbreaking Transistor Innovations at IEDM 2023

At the 2023 IEEE International Electron Devices Meeting (IEDM), Intel introduced significant advancements in transistor technology that continue to drive Moore's Law forward. Intel's Components Research group demonstrated innovative 3D stacked CMOS transistors, enhanced with backside power and direct backside contacts. This breakthrough in transistor architecture allows for more efficient scaling and improved performance, marking a first in the industry.

3D Stacked CMOS Transistors

Intel displayed the ability to vertically stack complementary field effect transistors (CFET) with a scaled gate pitch down to 60 nanometers (nm). This technology, combined with backside power and direct backside contacts, underscores Intel's leadership in gate-all-around transistors and its capacity to innovate beyond RibbonFET.

Beyond Five Nodes in Four Years

Intel's PowerVia, set for manufacturing readiness in 2024, represents the first implementation of backside power delivery. At IEDM 2023, the company identified ways to extend and scale backside power delivery beyond PowerVia, utilizing backside contacts and other novel vertical interconnects for efficient device stacking.

Integration of Silicon and GaN Transistors

Intel successfully integrated silicon transistors with gallium nitride (GaN) transistors on the same 300 mm wafer. The "DrGaN" technology showcased at the event demonstrates Intel's advancements in high-performance integrated circuits for power delivery.

Advances in 2D Transistor Space

Intel presented high-mobility transition metal dichalcogenide (TMD) 2D channel materials, showcasing prototypes of high-mobility TMD transistors for both NMOS and PMOS. Additionally, Intel revealed the world’s first gate-all-around (GAA) 2D TMD PMOS transistor and the first 2D PMOS transistor fabricated on a 300 mm wafer.

These developments by Intel represent a significant stride in semiconductor research, promising to enhance the efficiency and capabilities of future computing technologies.

IBM and Samsung Revolutionize Semiconductor Industry with Groundbreaking VTFET Transistor Technology

In a breakthrough development, IBM and Samsung have introduced a new transistor architecture named Vertical-Transport Nanosheet Field-Effect Transistors (VTFETs), potentially outperforming traditional FinFETs. This exciting innovation was discussed in the AAC Exclusive article, "A Chat With IBM Researchers Who Built the New 'VTFET' Transistor," featuring insights from IBM researchers Brent Anderson and Hemanth Jagannathan.

Comparison of a VTFET (left) vs. a lateral FET (right) transistor with current flowing through them. FinFETs have a limited gate pitch, scaled down to ~48nm, while VTFETs offer more scaling potential with a longer gate length due to their vertical design.

VTFETs offer significant improvements in performance and area scaling, potentially reducing energy usage in devices by up to 85% compared to FinFETs. These transistors operate with a vertical orientation, allowing for longer gates and thicker spacers and source-drains, which reduce resistance and capacitance. This design enables smaller transistor size while enhancing performance.

Anderson and Jagannathan's roles at IBM have been pivotal in the development of VTFETs. Anderson, who joined IBM in 1991, has been instrumental in driving the technology design for various logic nodes, including VTFET. Jagannathan, with IBM for 15 years, has managed process technology groups and played a crucial role in hardware research for VTFET.

Their work signifies a significant step forward in semiconductor technology, promising higher density, performance, and energy efficiency. This innovation represents a potential future for Moore's law scaling, alongside other advancements like monolithic 3D and chip stacking technologies. The real-world implementation of VTFETs is eagerly anticipated, with the technology expected to mature in the coming years.

Source: AAC Exclusive: A Chat With IBM Researchers Who Built the New “VTFET” Transistor - News (allaboutcircuits.com)

TSMC To Report Breakthrough in NMOS Nanosheets Using Ultra-Thin MoS2 Channels at IEDM 2023

A TSMC-led research team, in collaboration with National Yang Ming Chiao Tung University and National Applied Research Laboratories, has unveiled promising results for using ultra-thin transition metal dichalcogenides (TMDs), specifically MoS2, as the channel material in NMOS nanosheets. Their innovative approach deviates from the conventional method of thinning Si channels. The team's devices exhibited impressive performance metrics: a positive threshold voltage (VTH) of ~1.0 V, a high on-current of ~370 µA/µm at VDS = 1 V, a large on/off ratio of 1E8, and a low contact resistance ranging between 0.37-0.58 kΩ-µm. These outcomes were primarily attributed to the introduction of a novel C-shaped wrap-around contact, which enhances contact area, and an optimized gate stack. While the devices demonstrated satisfactory mechanical stability, a challenge remains in addressing defect creation within the MoS2 channels. This groundbreaking study, titled "Monolayer-MoS2 Stacked Nanosheet Channel with C-type Metal Contact" by Y-Y Chung et al., is a pivotal step forward in nanosheet scaling using TMDs.

ALD is a the technique for the precise and uniform synthesis of MoS₂, especially for semiconductor applications on large-scale wafers. The choice of precursors plays a crucial role in achieving optimal deposition characteristics. Mo (CO) 6 and H2S have been identified as the primary precursors for depositing molybdenum and sulfur components, respectively. These precursors have demonstrated the capacity for self-limiting growth behavior within a specific ALD temperature window, leading to uniform MoS₂ layers. Notably, this process has been successfully scaled up to achieve highly uniform film growth on large 300 mm SiO2/Si wafers, marking its potential for industry-level manufacturing. The ability to maintain uniformity and thickness control on such wafers emphasizes the potential of ALD in integrating MoS₂ into next-generation electronic devices and further underscores the significance of selecting appropriate precursors for optimal deposition outcomes. Other precursors have been investigated. MoCl₅ and MoF₆ serve as alternative molybdenum sources. For the sulfur component, H₂S is commonly paired with molybdenum precursors, but (CH₃)₂S has also been explored. The choice of these precursors directly impacts the properties of the resulting MoS₂ film in the ALD process and therefore precursor development for 2D MoS2 is a hot field of ongoing research.

While deposition methods are abundant, etching processes are comparatively scarce. Recent research by Elton Graugnard et al also introduces a thermal Atomic Layer Etching (ALE) technique for MoS2, leveraging MoF6 for fluorination, alternated with H2O exposures, to etch both crystalline and amorphous MoS2 films. This process has been characterized using various analytical techniques like QCM, FTIR, and QMS. The etching is temperature-dependent, with a significant increase in mass change per cycle as temperature rises. The mechanism involves two-stage oxidation of Mo, producing volatile byproducts. The resultant etch rates were established for different films, and post-etch annealing rendered crystalline MoS2 films. The thermal MoS2 ALE introduces a promising low-temperature method for embedding MoS2 films in large-scale device manufacturing.

Chem. Mater. 2023, 35, 3, 927-936

Sources:

 https://www.ieee-iedm.org/press-kit

https://pubs.acs.org/doi/10.1021/acs.chemmater.2c02549

Bottom-up PEALD of SiO2 by growth inhibition for seamless gap-fill process

Bottom-up plasma-enhanced atomic layer deposition of SiO2 by utilizing growth inhibition using NH3 plasma pre-treatment for seamless gap-fill process

Yoenju Choi, Taehoon Kim, Hangyul Lee, Jusung Park, Juhwan Park, Dongho Ryu & Woojin Jeon

Scientific Reports volume 12, Article number: 15756 (2022)

The design-rule shrinkage in semiconductor devices is a challenge at every step of the integration process. In the gap-fill process for isolation, the seam and void formation cannot be suppressed by using a deposition process, which even has excellent step coverage. To achieve seamless gap fill in the high-aspect-ratio structure, which has a non-ideal etch profile such as a negative slope, the deposition process should be able to realize the “bottom-up growth” behavior. In this work, the bottom-up growth of a SiO2 plasma-enhanced atomic layer deposition (PE-ALD) process in a trench structure was investigated by using a growth inhibition process employing plasma treatment. N2 and NH3 plasma pre-treatments were employed to suppress the growth of the SiO2 PE-ALD process without any contamination, and the inhibition mechanism was investigated by performing surface chemistry analyses using X-ray photoelectron spectroscopy. Furthermore, the gap-fill characteristics of the SiO2 PE-ALD process were examined, depending on the process conditions of NH3 plasma pre-treatment, by performing cross-sectional field emission scanning electron microscopy measurements. Finally, a seamless gap-fill process in a high-aspect-ratio trench pattern was achieved by the bottom-up growth behavior of SiO2 PE-ALD using NH3 plasma pre-treatment.

From: Bottom-up plasma-enhanced atomic layer deposition of SiO2 by utilizing growth inhibition using NH3 plasma pre-treatment for seamless gap-fill process

Webinar - Decadal Plan for Semiconductors: New Compute Trajectories for Energy Efficiency

SIA/SRC [LINK]: Computing and, more generally, Information and Communication Technologies (ICT) is the social-economic growth engine of the modern world. Rapid advances in computing have provided increased performance and enhanced features in each new generation of products in nearly every market segment, whether it be servers, PCs, communications, mobile, automotive, or entertainment, among others.

The use of information and communication technologies continues to grow without bounds dominated by the exponential creation of data that must be moved, stored, computed, communicated, secured and converted to end user information. Ever-rising energy demands for computing versus global energy production are creating new risk, therefore new computing paradigms need to be discovered that would result in dramatically improved energy efficiency of computing.

This webinar intends to identify a compelling research agenda based on the Decadal Plan for Semiconductors, led by SRC to discover new approaches to computing with a focus on changing the current mainstream compute trajectory. The underlying technical challenge is bit-utilization efficiency in computation.

The US Patent Office has approved AlixLabs’ patent application for nanofabrication by ALE Pitch Splitting (APS)

(30 April 2021, Lund Sweden). The US Patent Office has approved AlixLabs’ (AlixLabs AB) patent application for nanofabrication by ALE Pitch Splitting (APS).

The US Patent Office has issued a patent (US10930515) on February 23, 2021. The patent covers methods to split nanostructures in half by a single process step using Atomic Layer Etching (ALE). The method has the potential to have a big impact on the semiconductor industry by enabling sustainable scaling of electronic components and shrink chip designs further in a cost-effective way. The method is complementary for single exposure Immersion and Extreme UV (EUV) Lithography and corresponding multiple patterning technologies like self-aligned double and quadruple patterning (SADP resp. SAQP) as well as directed self-assembly (DSA).

In direct comparison to mentioned more complicated and expensive methods, APS may cut the need for certain fab equipment investments considerably, reduce manufacturing cost and energy consumption as well as reduce greenhouse gas emission during the patterning processing by up to 50%, allowing greener and affordable way forward for the semiconductor industry.

AlixLabs aims at applications for the manufacturing of leading-edge sub 5nm Logic Devices and Memory Chips that are used for everyday consumer electronic devices, 5G and AI.

The company’s CEO Dr. Jonas Sundqvist comments:

After founding the company in 2019 we now move into very exciting times. The team has been expanded with Dr. Mohammad Karimi as Principal Scientist and we have several applications and projects in the pipeline for broadening our patent protection and creating further opportunities for commercial agreements starting now. Currently, we are taking on the first round of private investments and will expand operations for both core activities in Lund, Sweden, at NanoLund and Lund Nano Lab, and the IDEON Science Park in Sweden. In addition, we are heading to the heart of the European semiconductor industry in Dresden Germany for a lab to fab transfer to 300 mm silicon wafer process verification to get ready for customer demonstrations of APS.

The company’s CTO Dr. Dmitry Suyatin comments:

This patent is built on a surprising discovery by the inventors, which took place at Lund Nano Lab during the Master project by Dr. Sabbir A. Khan who has recently received his PhD from the University of Copenhagen and now continues his postdoctoral work at Niels Bohr Institute in Copenhagen.

About AlixLabs AB:

AlixLabs (www.alixlabs.com) is an innovative startup enabling the semiconductor industry to scale down Logic and Memory components in a cost-effective manner by the use of ALE Pitch Splitting (APS).

Background Information:

Lund Nano Lab: https://www.nano.lu.se/facilities/lund-nano-lab

IDEON Science Park: https://www.ideoninnovation.se/our-startups

Picture:

Thermal ALE of germanium rich SiGe by CU Boulder and ASM Microchemistry

Epitaxially grown SiGe is an important material for CMOS Logic. It is integrated as the channel material and by inserting a higher concentration of germanium the mobility of the transistor can be improved. The industry calls it Epi, but what is really referred to a thermal CVD process producing an epitaxially grown layer of silicon or silicon-germanium onto a single crystalline silicon wafer.

As CMOS scaling has progressed the IDMs and Foundries have moved from the planar field-effect transistor (FET) architecture to a narrow fin-based transition the FinFET. The next evolutionary step on the horizon will be the transition to a nanowire-based architecture forming a gate-all-around FET (GAA-FET). At some point in time beyond the 2 nm node, the lateral scaling possibility will hit a wall and it is foreseen that the CMOS scaling will gup upwards like other technologies in order to cram in more devices per unit area. In a first approach, it may be that the NMOS and PMOS transistors are rearranged from being processed next to each other to put one of them on top of the other. Intel recently presented this at IEDM2020 (LINK). Having done that you can foresee continuing on a vertical scaling path also for CMOS just like 3DNAND and start to build those skyscrapers.

When going vertical, you will need highly conformal deposition processes as provided by ALD and in high volume production since the event of 90 nm DRAM (Samsung) and 45 nm Logic (Intel), however, etch is a problem since the reactive ion etching process are typically directional with the plasma under low-pressure processing conditions used. Also, the Argon plasma ALE processes to etch Silicon, silicon Germanin gallium nitride, and III/V materials are directional or anisotropic as the etch guys say or non-conformal as we ALD people say.

Typically the best way to achieve isotropic etch conditions, meaning you remove material at the same rate or as for ALE the same amount per cycle (etch per cycle EPC), is to skip the plasma that causes the anisotropic etch. Here Dr Abdulgatov and co-workers in the famous SM George Lab, CU Boulder together with Varun Sharma and friends from ASM Microchemistry, one of Dresden's best shining ALD-Stars, publish a paper on Thermal ALE of germanium rich SiGe that is quite clever. Here using PVD Si0.15Ge0.85 samples, which are difficult to make by Epi due to the high Ge content. I think we will see more of this for also GaN, SiC and III/V materials coming up.

Thermal atomic layer etching of germanium-rich SiGe using an oxidation and “conversion-etch” mechanism

AI Abdulagatov, V Sharma, JA Murdzek, AS Cavanagh, SM George

Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films

Abstract: The thermal atomic layer etching (ALE) of germanium-rich SiGe was demonstrated using an oxidation and “conversion-etch” mechanism with oxygen (O2) or ozone (O3), hydrofluoric acid (HF), and trimethylaluminum [TMA, Al(CH3)3] as the reactants. The crystalline germanium-rich SiGe film was prepared using physical vapor deposition and had a composition of Si0.15Ge0.85. In situ spectroscopic ellipsometry was employed to monitor the thickness of both the SiGe film and the surface oxide layer on the SiGe film during thermal ALE. Using a reactant sequence of O2-HF-TMA, the etch rate of the SiGe film increased progressively with temperatures from 225 to 290 °C. At 290 °C, the SiGe film thickness decreased linearly at a rate of 0.57 Å/cycle with a surface oxide thickness of 18–19 Å. This etch rate was obtained using reactant pressures of 25, 0.2, and 0.4 Torr and doses of 1.5, 1.0, and 1.0 s for O2, HF, and TMA, respectively. The TMA and HF reactions were self-limiting and the O2 reaction was reasonably self-limiting at 290 °C. Using an O3-HF-TMA reaction sequence, the SiGe ALE etch rate was 0.42 Å/cycle at 290 °C. This etch rate was obtained using reactant pressures of 15, 0.2, and 0.4 Torr and dose times of 0.5, 1.0, and 1.0 s for O3, HF, and TMA, respectively. The O3, TMA, and HF reactions were all self-limiting at 290 °C. Atomic force microscopy images revealed that thermal ALE with the O2-HF-TMA or O3-HF-TMA reaction sequences did not roughen the surface of the SiGe film. The SiGe film was etched selectively compared with Si or Si3N4 at 290 °C using an O2-HF-TMA reaction sequence. The etch rate for the SiGe film was >10 times faster than Si(100) or Si3N4 that was prepared using low-pressure chemical vapor deposition. This selectivity for the SiGe film will be useful to fabricate Si nanowires and nanosheets using SiGe as the sacrificial layer.

Full text open source: LINK

Figure from Journal of Vacuum Science & Technology A 39, 022602 (2021); https://doi.org/10.1116/6.0000834

LIVE Stream - Advanced Process Technologies to Enable Future Devices and Scaling (invited), Rob Clark Tokyo Electron

SEMICON Korea SEMI Technology Symposium (STS) 2021 - The invited presentation titled "Advanced Process Technologies to Enable Future Devices and Scaling" can be streamed starting Feb. 3 in S. Korea (2/2 evening U.S.). 

This is an overview of new processing technologies required for continued scaling of leading-edge and emerging semiconductor devices. The main drivers and trends affecting future semiconductor device scaling are introduced to explain how these factors are influencing and driving process technology development. Topics explored in this presentation include atomic layer deposition (ALD), atomic layer etching (ALE), selective deposition and etching. In order to enable self-aligned and multiple patterning schemes as well as emerging devices for future manufacturing, atomic level process technologies need to be leveraged holistically. Real-world examples of current and future integration schemes, as well as emerging devices, will be presented and explained so that attendees can understand how advanced process technologies will be used in future device manufacturing as well as what benefits and tradeoffs may be encountered in their use.

LINK: https://www.semiconkorea.org/ko/node/3701

Master Thesis in Nanotechnology with Alixlabs in Sweden on Atomic Level Fragmentation

Come and join us in Lund Sweden for an exciting Master Thesis in Atomic Level Fragmentation - the new option for extending optical lithography cheaper, greener, and faster than any advanced multi-patterning scheme!

Operating within Lind Nano Lab we guarantee a safe & flexible workplace under ISO 5 and ISO 7 Cleanroom conditions, 24/7 operation, and remote working from wherever you need to be when outside the cleanroom.

Lund Nano Lab : LINK

Thesis description and application : LINK

View across The Science City of Lund in South Sweden direction Copenhagen in Denmark across the straight of Öresend connected by the longest bridge in Europe.

Imec introduces 2D materials in the logic device scaling roadmap

[IEDM 2020 Virtual, Imec Belgium LINK] At the 2020 IEDM conference, imec proposes that 2D semiconductors like tungsten disulfide (WS2) can further extend the logic transistor scaling roadmap. The team laid the groundwork for integrating 2D semiconductors in a 300mm CMOS fab, and worked towards improved device performance. These findings are presented in four IEDM papers, one of which was selected as IEDM highlight.

More details can be found in 4 papers presented at the 2020 IEDM conference:

[1] ‘Introducing 2D-FETs in device scaling roadmap using DTCO’, Z. Ahmed et al.
[2] ‘Wafer-scale integration of double gated WS2-transistors in 300mm Si CMOS fab’, I. Asselberghs et al.
[3] ‘Dual gate synthetic WS2 MOSFETs with 120µS/µm Gm 2.7µF/cm2 capacitance and ambipolar channel’, D. Lin et al.
[4] ‘Sources of variability in scaled MoS2 FETs’, Q. Smets et al. (IEDM highlight paper)

TEM image of a 2D device fabricated with 300mm processes. (Source: Imec)