ASM Charts the Future of ALD: Scaling Innovation, Integration, and Intelligence Toward 2030

ASM used its 2025 Investor Day to set a bold 2030 ambition of more than €5.7 billion revenue, operating margins above 30%, and free cash flow above €1 billion. The company has consolidated a leading position in ALD with over 55% market share in their segments they where they chose to compete and is scaling its Epi business from 12% in 2020 to 25% in 2024. ALD remains the central growth driver, with the market for single-wafer ALD expected to outpace overall wafer fab equipment and reach $5.1–6.1 billion by 2030, while Si Epi is forecast at $2.5–3.2 billion with a 9–13% CAGR. 

The single-wafer ALD market is projected to grow strongly from about 3.0 billion dollars in 2024 to between 5.1 and 6.1 billion dollars by 2030, representing a 9–13 percent compound annual growth rate, outpacing the overall wafer fab equipment market, which is expected to grow at 6 percent annually from 110 billion dollars in 2024 to 155 billion dollars in 2030. This growth is driven by the increasing number of ALD layers required in leading-edge logic and foundry processes as well as in advanced DRAM, both in the cell and peripheral CMOS areas. By 2030, ASM aims to maintain a market share above 55 percent, sustaining its lead in logic and foundry while also expanding its position in memory.

Node and memory inflections significantly expand ASM’s served markets, adding $400 million in their served available market from 3nm FinFET to 2nm GAA, and a further $450–500 million from 2nm to 1.4nm, while DRAM transitions contribute another $400–450 million. FEOL ALD layers grow fastest, with roughly 60% of ALD demand at 1.4nm coming from the transistor front end. In advanced packaging, a total available market of $11.5 billion by 2030 supports ASM’s plan to double its served available market to more than 30% of that market. 

Services are projected to grow at more than 12% CAGR through 2030, with half of revenues moving to outcome-based models and new “dry clean” refurbish technology delivering ~10× selectivity, ~5× part life, over 95% CO₂e reduction, and more than 2× cost-of-ownership benefits. 

ASM also introduced its XP8E common platform integrating clean, treat, inhibit, and ALD steps for 2nm ASD flows, and highlighted AI/ML deployment in high-volume manufacturing for anomaly detection, predictive maintenance, and improved first-time-right performance.

ASM’s XP8E common platform is positioned as a key enabler for the 2nm and beyond era, where Area-Selective Deposition and advanced integration schemes require multiple tightly coupled process steps. By bringing clean, treat, inhibit, and ALD into a single cluster, XP8E reduces wafer handling, shortens cycle times, and improves process control. This integration is critical for scaling as the number of ALD steps grows with each node, and it directly addresses challenges in pattern fidelity, defectivity, and variability that can otherwise undermine yield at 2nm. The platform is designed to be modular and flexible, so customers can configure it for different ASD and high-k/metal gate flows, while also benefiting from a common hardware base that simplifies fab operations, service, and parts management.

Alongside new hardware, ASM is embedding AI and machine learning capabilities into high-volume manufacturing. These tools enable real-time anomaly detection to flag subtle deviations in process behavior before they impact yield, and provide “top contributor” insights that help engineers rapidly identify root causes. Predictive maintenance, including ASM’s PM-Bot automation, improves precision and ensures higher first-time-right rates, cutting downtime and labor intensity. Over time, this creates a closed-loop system where data from thousands of wafers continuously refines process windows, stabilizes tool performance, and enhances cost-of-ownership. In combination, XP8E’s process integration and AI-driven control systems aim to deliver the repeatability, selectivity, and productivity gains required for the 2nm transition and future GAA nodes.

ASMs ALD History - from 1974 to 2024, 50+ years of ALD

The timeline highlights key milestones in the history of ALD and ASM’s leadership in the field. It begins in 1974 with Dr. Tuomo Suntola’s invention of ALD, followed by the founding of Microchemistry in Helsinki in 1987. ASM entered the scene in 1998 with the release of its first 200 mm Pulsar tool and strengthened its position by acquiring Microchemistry from Neste in 1999 and securing Sherman PEALD patents in 2000. Growth continued with the acquisition of Genitech in 2004. In 2008, ASM’s Pulsar tool was recognized as Product of the Year, cementing its reputation. More recently, ASM expanded its product portfolio with the introduction of the dual-chamber Synergis ALD system in 2018, the XP8 quad chamber module in 2019, and the Prominis ALD and XP8E platform in 2024. Strategic acquisitions, such as Reno Sub-Systems in 2022, further enhanced ASM’s technology base, illustrating a steady path of innovation and consolidation in ALD leadership over five decades.

The timeline illustrates ASM’s journey in atomic layer deposition from its origins to modern platforms. ALD was invented by Dr. Tuomo Suntola in 1974, followed by the founding of Microchemistry in 1987. ASM entered the field with the release of its first 200 mm Pulsar tool in 1998, strengthened its position by acquiring Microchemistry from Neste in 1999 (Finland), and expanded its patent base with Sherman PEALD patents in 2000. Key milestones include the acquisition of Genitech (Korea) in 2004, industry recognition for Pulsar in 2008, the introduction of Synergis in 2018 and XP8 in 2019, and the acquisition of Reno Sub-Systems in 2022. Most recently, ASM launched the Prominis ALD and XP8E platform in 2024, underscoring more than 50 years of continuous innovation and leadership in ALD.

The Finnish angle in ASM’s ALD story is both historic and ongoing. Atomic Layer Deposition was invented in Finland in 1974 by Dr. Tuomo Suntola, originally called Atomic Layer Epitaxy. The technology was developed at Microchemistry Ltd., a Finnish company founded in Helsinki in 1987 under Neste. When ASM acquired Microchemistry in 1999, they started gaining the pioneering ALD patents, know-how, and expertise that underpin its leadership today. Finland continues to play an active role through the University of Helsinki and ASM’s Chemical Innovation Group in Helsinki, where precursor chemistry and process research are carried out in close collaboration with Finnish scientists. In this way, Finland provided both the origin of ALD for ASM and remains an important innovation hub supporting ASM’s growth and leadership.

The ASM Pulsar “HIG source” for solids (or the solid precursor delivery subsystem) is a core enabler for ASM’s ability to use low-vapor-pressure solid precursors in ALD. The original innovation from ASM Microchemistry has been further developed over decades and is now still a key technology on the new platform for Molybdenum ALD seen below. It involves a heated sublimation mechanism (sometimes mounted close to or integrated with the reactor), controlled inert gas valves, purge isolation, and precise flux control to feed vapor from a solid into the ALD chamber. The architecture seeks to avoid cold spots or condensation and maintain consistent, controllable precursor delivery pulses.

Genitech was a South Korean company specializing in plasma enhanced ALD and thin film deposition. ASM acquired the company in 2004 to expand its capabilities in plasma based processes and complement its existing thermal ALD portfolio. The acquisition gave ASM a stronger position in PEALD for applications such as high k dielectrics and metal gate stacks used in advanced logic and memory. Genitech’s technology was integrated into ASM’s Pulsar and subsequent platforms, helping establish ASM’s leadership in both thermal and plasma ALD.

ASM acquired Reno Sub-Systems in 2022. Reno is a US-based company specializing in RF power delivery systems and matching networks for plasma tools. Their solid-state RF technology is valued for faster response times, higher precision, and better process stability compared to legacy RF solutions. By integrating Reno’s subsystems into its platforms, ASM strengthened its capability in plasma-based ALD and PEALD, where fine RF control is critical for uniformity, repeatability, and advanced film properties.

Future Outlook

ASM ties its deposition processing capability to its tool portfolio—Pulsar, EmerALD, Synergis, Prominis, XP8E, and others—which are engineered with small-volume reactors, advanced plasma control, and integrated multi-step clustering (clean, treat, inhibit, deposit).

Looking ahead, ASM is uniquely positioned to remain the clear leader in atomic layer deposition as the semiconductor industry advances to 2nm and beyond. The company’s deep history in ALD, dating back to Dr. Tuomo Suntola’s invention in 1974, has evolved into a robust technology portfolio that now commands more than 55 percent market share where ASM chooses to compete. 

With single-wafer ALD forecast to nearly double in size by 2030 and outpace overall wafer fab equipment growth, ASM is set to capture outsized value from both logic and memory inflections. Its proven expertise in solid source precursor delivery, trailing back to the the Pulsar HIG sublimation system and F120 Microchemistry research reactors, now expands to new material capabilities such as molybdenum ALD for advanced node metallization. At the same time, ASM is broadening its impact through the XP8E common platform, which integrates multiple critical steps into one cluster with embedded AI and machine learning into high-volume manufacturing for real-time control. ASM’s combination of process innovation, equipment integration, and data-driven intelligence places the company at the center of semiconductor scaling, ensuring its leadership in enabling Moore’s Law through the next decade.

Sources:

ASM InvestorDay 2025

JSR, Lam Research, and SK hynix Push the Boundaries of ASML´s EUV Semiconductor Manufacturing

JSR Corporation, including its subsidiary Inpria Corporation, and Lam Research have entered into a cross-licensing and collaboration agreement to accelerate the development of next-generation semiconductor manufacturing technologies. The partnership combines JSR’s expertise in photoresists and advanced materials—anchored by Inpria’s metal-oxide resists (MORs) for extreme ultraviolet (EUV) lithography—with Lam’s leadership in wafer fabrication equipment and process technology. By sharing intellectual property and integrating complementary capabilities, the companies aim to address scaling and patterning challenges as chipmakers pursue smaller, denser, and more energy-efficient devices for advanced logic and memory applications.

Inpria’s MORs, based on spin-on tin-oxide materials, provide high EUV photon absorption, excellent etch resistance, and reduced line edge roughness compared with conventional organic resists. These materials are fully compatible with existing lithography systems, making them attractive for high-volume production. To meet growing demand, JSR is expanding its global footprint with new R&D facilities in Japan and a production plant in Korea set to begin operations in 2026. Lam Research complements this with its Aether® dry resist technology, which replaces wet spin-coating and development with fully dry, vapor-phase processes. This innovation improves uniformity, reduces stochastic defects, and strengthens EUV absorption, enabling higher resolution and sensitivity. Aether has demonstrated direct-print 28 nm pitch patterning for logic and is already being adopted by leading memory manufacturers, offering both performance advantages and sustainability gains through reduced chemical and energy use.

These advances align with a broader industry shift toward tighter integration of materials and equipment solutions, exemplified by SK hynix’s installation of the world’s first commercial High-NA EUV lithography tool, ASML’s TWINSCAN EXE:5200B, at its M16 fab in Icheon, South Korea. Featuring a numerical aperture of 0.55—compared with 0.33 in current Low-NA EUV systems—the High-NA platform boosts resolution by 40%, enabling transistors about 1.7× smaller and wafer transistor densities nearly 2.9× higher. For SK hynix, this milestone supports the development of next-generation DRAM, reduces process complexity, lowers costs, and strengthens competitiveness in AI memory and advanced compute markets.

As one of the “big three” memory makers alongside Samsung and Micron, SK hynix has established itself as the leader in high-volume DRAM manufacturing. It was the first to mass-produce DDR5 and high-bandwidth memory (HBM3), both essential for AI and high-performance computing. Its early adoption of EUV lithography for DRAM production—and now the industry-first deployment of ASML’s High-NA EUV system—underscores its position at the forefront of DRAM scaling and density. Together, the innovations from JSR, Inpria, Lam Research, and SK hynix illustrate how collaboration across the semiconductor ecosystem is driving the breakthroughs required to sustain Moore’s Law in the era of AI and advanced computing.

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Do you want me to keep the headline-style opening as above, or make it read more like a press release introduction with a formal lead sentence?

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JSR Corporation/Inpria Corporation and Lam Research Enter Cross Licensing and Collaboration Agreement to Advance Semiconductor Manufacturing

Dry Resist Patterning Progress and Readiness Towards High NA EUV Lithography

INPRIA | A world leader world leader in metal oxide photoresist design, development and manufacturing

Inpria Co-Developing Metal Oxide Resist with SK hynix to Reduce Complexity of Patterning for Next-Generation DRAM | 2022 | News | JSR Corporation

SK hynix Introduces Industry’s First Commercial High NA EUV

Breaking the Copper Bottleneck: Lam Research’s Mo-ALD ALTUS Halo Enables Next-Generation Hybrid Metallization

Lam Research now offers molybdenum (Mo) atomic layer deposition (ALD) with its ALTUS Halo platform, introduced in 2025 as the first high-volume ALD tool designed for Mo metallization. The system enables conformal and selective, bottom-up deposition of low-resistivity, void-free Mo films, targeting advanced logic, memory, and 3D NAND applications where conventional copper and tungsten interconnects face scaling and reliability limits. This positions Lam’s Mo-ALD as a key enabler for next-generation BEOL hybrid metallization schemes.

Current density of various metal/via schemes. Red and green areas indicate higher current density.  

Hybrid metallization using Mo shows strong potential to overcome the scaling limitations of conventional copper dual damascene (Cu DD) processes in advanced semiconductor BEOL interconnects. As device dimensions shrink, Cu faces challenges such as increased resistivity, barrier thickness limitations, and stress-induced voids (SIVs), all of which degrade performance. Mo hybrid metallization, which uses bottom-up barrierless metal deposition before a conventional Cu process, significantly reduces resistance—by about 55% compared to Cu DD—and further by 15% with selective barrier deposition (SBD). This lower resistance translates into higher current densities and improved reliability. Stress distribution studies also reveal that Mo hybrid vias exhibit lower void formation risks than Cu due to smaller stress gradients at the via/barrier interfaces.

Comparison of via and line resistance for conventional Cu dual damascene and Mo hybrid metallization schemes. Mo vias reduce total resistance by ~35% without selective barrier deposition (SBD), with an additional ~20% reduction when fully replacing Cu. Applying SBD further lowers resistance, achieving up to ~55% reduction compared to the Cu baseline.

Optimization studies, performed with SEMulator3D® simulations, identified key parameters like via critical dimensions, height, and material stress properties that impact resistance, capacitance, and hydrostatic stress. Findings show that increasing Mo via height lowers resistance but raises stress, suggesting an optimal fill height around 25 nm for balancing performance and reliability. Intrinsic stress of Mo and process temperature tuning were also shown to mitigate stress-induced reliability issues, with 400°C identified as a favorable condition. Ultimately, hybrid metallization with Mo offers a scalable path forward, combining electrical and mechanical benefits, while virtual DOE and process modeling enable predictive optimization without extensive wafer-based experiments.

Sources:

Breaking the Copper Bottleneck With Molybdenum Hybrid Metallization

Lam Research Ushers in New Era of Semiconductor Metallization with ALTUS® Halo for Molybdenum Atomic Layer Deposition - Feb 19, 2025

TSMC’s 2 nm Fabs Lock Out China OEMs, Securing ALD and Process Tool Demand for US, European, and Japanese Tier-1 Suppliers

TSMC’s decision to exclude Chinese equipment vendors from its 2 nm fabs in Taiwan and the US reshapes the competitive landscape in favor of Japanese, American, and European suppliers. With the 2 nm node set to become the largest in history by wafer volume and revenue potential, this policy shift effectively concentrates demand among a handful of Tier 1 players —ASMI, TEL, Applied Materials, and Lam Research—who already dominate in deposition, etch, and cleaning tools essential for nanosheet GAA and backside power delivery. No need to mention ASML.

Announced in January: TSMC is advancing with its 2 nm (N2) technology, establishing a pilot line at its Hsinchu Baoshan Fab 20 with an initial monthly output of around 3,000–3,500 wafers. By combining production from Hsinchu and Kaohsiung, the company expects to exceed 50,000 wafers per month by the end of 2025 and reach about 125,000 wafers per month by the end of 2026. Output at Hsinchu should rise to 20,000–25,000 wafers per month by late 2025 and 60,000–65,000 by early 2027, while Kaohsiung is projected to produce 25,000–30,000 wafers monthly by late 2025 and also expand to 60,000–65,000 by early 2027. Chairman C.C. Wei has highlighted that demand for 2 nm exceeds that of 3 nm, driven by its 24–35% lower power consumption, 15% performance boost at the same power, and 15% higher transistor density. Apple will be the first adopter, followed by MediaTek, Qualcomm, Intel, NVIDIA, AMD and Broadcom.

TSMC will start 2 nm mass production in Taiwan in the second half of 2025, initially with Fab 22 in Kaohsiung as the anchor site for yield learning. The first ramp is set at 40,000 wafers per month, expanding to 100,000 wafers per month in 2026 and reaching 200,000 wafers per month by 2027, making N2 the largest and most profitable node in TSMC’s history.

In the US, Arizona Fab 21 is being developed in phases. Phase 1 is already producing 4 nm chips, Phase 2 will start 3 nm by late 2025 or early 2026, and Phase 3 is planned for 2 nm and A16-class chips toward the end of the decade. This ensures that while Taiwan remains the cost-optimized base for N2 production, Arizona provides premium, subsidy-supported capacity for US customers, diversifying geographic and geopolitical risk.

Overall, Taiwan will carry the bulk of N2 output and cost efficiency, while Arizona secures local supply for strategic US clients like Apple, Nvidia, AMD, and Intel. By 2027, with 200,000 wafers per month globally, N2 alone could generate nearly $50 billion annually, cementing TSMC’s central role in powering AI and HPC expansion.

The move aligns directly with Washington’s Chip EQUIP Act, which ties subsidies to avoiding “foreign entities of concern.” By pre-emptively removing Chinese tools, TSMC safeguards its access to US incentives while giving its global customers—Apple, Nvidia, AMD, and Intel—assurance that supply chains are insulated from geopolitical risk. This codifies the leading suppliers as the “trusted” baseline for advanced-node capacity worldwide, effectively reinforcing their moat at the most profitable process node ever.

For ASMI, TEL, AMAT, and Lam, the outlook is very positive. With Chinese competitors pushed out, these companies can win more business and have stronger pricing power. At the same time, 2 nm wafer prices are climbing toward $30,000, far above older smartphone-focused nodes. TSMC is reviewing its suppliers for profit margins and China ties, but these four are essential for 2 nm production, so they are more likely to gain from rising demand and higher-value tools than lose ground. Put simply, the 2 nm era is set to drive lasting growth and profits for them as AI adoption accelerates through 2027.

Chinese semiconductor equipment OEMs that are cut out from TSMC’s 2 nm fabs under the new restrictions and supplier realignment:

• AMEC (Advanced Micro-Fabrication Equipment Inc.) – leading Chinese etch tool supplier, with relevance in dielectric etch and epitaxy
• Naura Technology Group – broad portfolio in etch, deposition, and cleaning tools
• Mattson Technology (China-owned, via E-Town Dragon Semiconductor) – focuses on dry strip, rapid thermal processing (RTP), and etch
• SMEE (Shanghai Micro Electronics Equipment) – China’s only domestic lithography tool maker (far behind in capability, but relevant in domestic fabs)
• Kingsemi – maker of ALD/CVD equipment, mainly for memory and advanced logic
• Piotech – deposition (CVD, PECVD, ALD) equipment vendor
• ACM Research (China) – cleaning and electrochemical deposition tools (though headquartered in the US, its operations are China-based and increasingly seen as China OEM)

At TSMC’s 2 nm fabs, the exclusion of Chinese equipment vendors channels ALD equipment demand entirely to US, European, and Japanese suppliers. ASM International (Europe) remains the clear leader in single-wafer ALD for high-k metal gate stacks and nanosheet spacers, with Applied Materials and Lam Research (US) competing in selective and plasma ALD for gate-all-around and backside power steps, while Tokyo Electron and Kokusai Electric (Japan) cover both single-wafer and batch ALD, particularly for spacer and liner deposition. By contrast, Chinese ALD players such as Naura, Kingsemi, and Piotech, while active in domestic logic and memory at 28–14 nm and some 7 nm non-EUV capacity, will not gain any capability at N2 and are explicitly excluded under TSMC’s supplier policy and US subsidy rules, leaving the largest and most profitable ALD opportunity in history to be divided among the established US, European, and Japanese Tier-1 suppliers.

Sources:

TSMC reportedly cuts Chinese chipmaking tools from 2nm fabs as suppliers face scrutiny due to emerging new US restrictions | Tom's Hardware

https://open.substack.com/pub/drrobertcastellano/p/tsmcs-2-nm-era-technology-leadership?r=l0uj0&utm_campaign=post&utm_medium=web&showWelcomeOnShare=false

TSMC Is Getting Ready to Launch Its First 2nm Production Line | TechPowerUp

SiCarrier Seeks $2.8 Billion to Advance Chipmaking Equipment

SiCarrier, a Chinese chip equipment manufacturer closely associated with Huawei and owned by the Shenzhen city government, is seeking $2.8 billion in funding to advance its ambitions of becoming China's leading chipmaking equipment provider. Founded in 2021, the company aims to surpass domestic rivals such as Naura and AMEC, amid U.S. export restrictions that have fueled China's drive for semiconductor self-sufficiency. The fundraising, targeting a valuation of $11 billion, is expected to conclude soon, with proceeds allocated primarily to R&D. State-owned firms and domestic investors have shown strong interest. Despite showcasing 30 products at Semicon China 2025, most of its tools remain under development and are not yet production-ready. SiCarrier has filed 92 patents, indicating plans to offer a comprehensive suite of chipmaking tools, including lithography and AI-driven inspection systems. However, its deep ties to Huawei have raised concerns among potential customers over data security and trade secret protection. Industry experts suggest full operational independence from Huawei is essential for broader market acceptance and long-term growth.

"Founded in 2021 and owned by the Shenzhen city government, SiCarrier is largely seen as a Huawei supplier. But it wants to become the leading domestic provider of chipmaking equipment in China, surpassing Naura and Advanced Micro-Fabrication Equipment China (AMEC), according to four people with knowledge of its goals."

A Reuters review of 92 patents filed by Shenzhen SiCarrier Industry Machines and its parent Shenzhen SiCarrier Technologies between October 2022 and March 2025 reveals the company’s ambitious plan to establish itself as a comprehensive supplier of semiconductor manufacturing equipment. Unlike domestic peers such as Naura and AMEC, which have taken more focused approaches, SiCarrier is pursuing an expansive product roadmap that spans the entire chip production chain—from wafer metrology and defect inspection to etching and atomic layer deposition (ALD) systems. These filings, verified through Anaqua’s AcclaimIP database, illustrate SiCarrier’s intention to compete head-on with established global players such as KLA, Lam Research, and Tokyo Electron, particularly in process-critical segments like thin-film deposition and etch uniformity control. Notably, SiCarrier is investing in AI-powered wafer defect recognition, a frontier area aimed at enhancing production yields, especially important in advanced nodes where precision is paramount. Industry observers cited by Reuters suggest metrology and inspection tools offer SiCarrier the most immediate opportunity, given the absence of a dominant Chinese competitor in that space. The patent portfolio also reveals efforts to close the technological gap in lithography by focusing on components for deep ultraviolet (DUV) systems and multi-patterning techniques. These are presented as domestic alternatives to extreme ultraviolet (EUV) lithography, which remains out of reach due to US export controls. However, experts like Dan Hutcheson of TechInsights caution that the multi-patterning approach—though pioneered by Intel and used by TSMC at 7 nm—carries known drawbacks such as increased complexity and yield challenges, stemming from its reliance on sequential deposition and several etch processes. 

Sources:

Exclusive: SiCarrier - Huawei partner in chips - seeks $2.8 billion in funds, sources say | Reuters

Tokyo Electron Delivers Record FY2025 Results Amid AI Boom, Eyes Growth Through CVD Innovation and Geopolitical Resilience

Tokyo Electron (TEL) achieved a record-breaking financial year in FY2025, with strong top- and bottom-line growth driven by robust global demand for advanced semiconductor equipment. Net sales rose by 32.8% year-on-year to approximately ¥2.43 trillion (around $15.7 billion USD), marking the highest in the company's history. Operating profit surged to ¥697.3 billion (about $4.5 billion USD), supported by an improved operating margin of 28.7%. Growth was underpinned by increased investment in leading-edge logic and memory, particularly High Bandwidth Memory (HBM) and advanced DRAM nodes, where TEL maintained or expanded market share through key Process of Record (POR) wins in etch and wafer bonding technologies. Revenue contributions diversified geographically, with notable gains in South Korea and Taiwan, even as China remained a key market. TEL also demonstrated strong cash flow, increased its R&D and capital investments, and returned significant value to shareholders through dividends and buybacks. Looking ahead, TEL forecasts continued growth in FY2026, positioning itself to capitalise on accelerating AI, 2nm logic, and heterogeneous integration trends.

Tokyo Electron TEL has demonstrated strong financial performance and strategic market expansion through FY2025, according to their investor presentation dated April 30, 2025. Their net sales, gross profit, operating profit, and net income have all reached record highs, signaling both operational efficiency and favorable market conditions.

LINK: Tokyo Electron Limited 2025 Q4 - Results - Earnings Call Presentation (OTCMKTS:TOELY) | Seeking Alpha

Tokyo Electron's Q4 FY2025 earnings call highlighted strong financial performance and an optimistic forward outlook amid geopolitical uncertainties. Despite global concerns around US tariffs and export controls—particularly in China, which saw its WFE market share fall to 35%—TEL stated that it has not observed any significant changes in customer investment sentiment or competitive dynamics. The company reaffirmed its strategy of focusing on long-term innovation rather than short-term regulatory shifts, underscoring its commitment to developing higher-productivity tools to offset potential external headwinds. Looking ahead, TEL forecasts continued double-digit WFE market growth into calendar 2026, driven by AI infrastructure demand, 2nm logic, and HBM scaling. The company plans record-high investments of ¥300 billion in R&D and ¥240 billion in CapEx for FY2026, reflecting confidence in sustained momentum across DRAM, advanced logic, and packaging technologies. TEL aims to expand global market share and reach ambitious mid-term goals, including over ¥1 trillion in operating profit and 35%+ OPM, by capitalising on technology transitions such as GAA, backside PDN, and heterogeneous integration.

LINK: Tokyo Electron Limited (TOELY) Q4 2025 Earnings Call Transcript | Seeking Alpha

Revenue and Profitability Growth:

Net sales increased significantly from ¥1,399.1 billion in FY2021 to ¥2,431.5 billion in FY2025, a 74% increase over four years. The gross profit also rose steadily, reaching ¥1,146.2 billion in FY2025, up from ¥564.9 billion in FY2021. Operating profit followed suit, more than doubling from ¥320.6 billion to ¥697.3 billion. These trends underscore TEL’s ability to scale profitably, with operating margins rising from 22.9% in FY2021 to 28.7% in FY2025. Return on equity (ROE) also remained strong, peaking at 37.2% in FY2022 and settling at 30.3% in FY2025, a testament to effective capital management.

Regional Sales Composition:

The revenue breakdown by region from Q1 FY2024 to Q4 FY2025 shows growing diversification. Notably, China has remained the single largest market, although its share declined from 47.4% in Q4 FY2024 to 34.3% in Q4 FY2025, reflecting a strategic balancing across geographies. South Korea, Taiwan, and North America significantly increased their contributions, with South Korea reaching ¥147.0 billion and Taiwan ¥135.8 billion in Q4 FY2025. This reflects growing demand from advanced logic and memory fabrication customers in these regions.

In FY2025, Tokyo Electron’s semiconductor production equipment (SPE) sales reached ¥1.86 trillion, driven by a sharp rise in DRAM-related investments, particularly for high-bandwidth memory (HBM), which accounted for 31% of total sales. Non-volatile memory (NAND) remained stable at 7%, while non-memory segments, including logic and foundry, continued to dominate with 62%, reflecting robust demand from both advanced and mature nodes. The overall recovery and expansion of customer investments across segments underpinned this strong performance.

Market Segment Performance

Tokyo Electron’s global market share in CY2024 demonstrates its leadership across multiple core segments of the semiconductor production equipment market. The company holds a commanding 92% share in coater/developer systems, underlining its unparalleled position in photoresist processing for advanced lithography applications. It also leads the wafer prober segment with a 38% share and maintains robust positions in key deposition categories, including 38% in CVD and 37% in oxidation/diffusion systems. In contrast, TEL’s market share in ALD stands at 16%, notably behind ASM International, highlighting an opportunity for expansion in this strategically important technology as the industry moves towards GAA and other 3D device structures. Performance in dry etch (27%), cleaning systems (21%), and wafer bonding (32%) rounds out a broadly competitive portfolio that positions TEL to effectively support ongoing advancements in scaling, heterogeneous integration, and high-performance packaging across logic, memory, and AI-related applications.

To further expand our future profit, we made steady progress in penetrating into new technology domains. Specifically, we released multiple new outstanding products contributing to the semiconductor technology innovation. For example, penetration to untapped segments such as single-wafer plasma CVD and PVD, gas cluster beam system which improves efficiency of leading-edge lithography, and laser-lift-off system to drastically decrease environmental footprint of processing. In fiscal 2025, we conducted share repurchase of about ¥150 billion in total.

- Toshiki Kawai - Representative Director, President and CEO

 

New product 2025 Episode™ single-wafer CVD platform

Episode™ 1 is Tokyo Electron's latest single-wafer CVD platform, launched in 2024 to address the challenges of advanced device scaling in logic, DRAM, and future AI processors. It supports up to eight process modules, enabling complex, uninterrupted multi-step processing. The system integrates the OPTCURE™ module for native oxide removal and ORTAS™ for titanium CVD, allowing immediate Ti deposition to minimise contact resistance in advanced interconnects. Episode™ 1 replaces traditional PVD with CVD to achieve uniform, low-resistivity films in high aspect ratio structures such as deep contact holes. With a 45% smaller footprint than its predecessor and advanced edge computing, data analytics, and environmental tracking capabilities, the system enhances fab productivity, engineer efficiency, and readiness for new materials in next-generation device manufacturing.

The TEL Episode™ 1 system shown in the image seems to feature twin or dual single-wafer process chambers, which is typical in modular CVD tools designed for high throughput. Each visible module (with two load ports per unit) likely contains two process chambers within the same footprint to maximise wafer handling efficiency and enable parallel processing—common in tools aimed at advanced logic and memory manufacturing.

Episode™ 1 offers a reduced footprint. Compared with the Triase+™ series, twice as many smaller modules can be installed in a system. With the same number of modules installed, Episode™ 1 takes up about 45% less fab space than its predecessor

LINK: Episode™ 1 Single-Wafer Deposition System for Semiconductors: Driving the Evolution of AI Semiconductors to Transform Everyday Life | Blog | Tokyo Electron Ltd.

ASM International Strengthens ALD Market Leadership Amid Strong Q1 Results, Growing GAA Adoption, and Strategic Positioning for Advanced Node Demand

ASM International’s Q1 2025 results reaffirm its leadership in Atomic Layer Deposition (ALD), a technology central to enabling advanced semiconductor nodes such as 2nm and beyond. With ALD accounting for more than half of its equipment revenue and strong customer engagement in leading-edge logic and memory, ASM is well-positioned to capitalise on rising demand driven by GAA architectures, high-bandwidth memory, and ongoing technology node transitions.

ASM International’s Q1 2025 results reinforce its leadership in ALD, a foundational technology for enabling advanced semiconductor nodes. ALD represented more than half of ASM’s equipment revenue, with the market expected to grow at a compound annual rate of 10–14% through 2027, and ASM maintaining a leading market share above 55% in the segments they compete in:

Single-Wafer ALD Tools

ASM’s flagship ALD platforms are single-wafer systems, which provide high precision, conformality, and process flexibility. These are used primarily in leading-edge logic and memory production.

• Key Platforms:

  • XP8 and XP8 QCM: High-productivity platforms supporting multiple process chambers; widely used for high-volume manufacturing.

  • Previum and Previum Pro: Previum systems incorporate an integrated epitaxial (EPI) pre-clean step that effectively removes 15–20 monolayers of native oxide from the substrate surface. This step is crucial for ensuring high-quality EPI film growth.

  • Pulsar®: Specialised for high-k dielectrics, such as hafnium oxide (HfO₂) typically used in gate stacks.

  • Eagle® XP8: Designed for advanced metal ALD (e.g. TiN, W), often used in logic and memory applications including barrier and liner layers.

ASM International’s strategic alignment with the prevailing trends in the wafer fab equipment (WFE) market and its concentrated customer base. Logic and foundry applications are set to remain the dominant segment of WFE spending through 2026, reinforcing ASM’s focus on enabling advanced nodes such as FinFET and GAA, where Epitaxy (Epi) and atomic layer deposition (ALD) are critical. The company’s FY24 revenue profile shows that its top five customers accounted for 51% of sales, while the top ten represented 70%, indicating strong relationships with leading-edge semiconductor manufacturers. These likely include TSMC, Samsung, Intel, SK hynix, and Micron—ASM’s probable top customers given their leading-edge node adoption and high ALD utilisation. Others may include GlobalFoundries, UMC, SMIC, and select IDMs. 

The industry’s shift to gate-all-around (GAA) transistor architectures at 2 nm and beyond is driving increased demand for single-wafer ALD and silicon epitaxy (Si Epi) processes, which are essential for integrating high-k dielectrics, advanced metals, and high aspect ratio features in both logic and memory devices. ASM’s deep engagement with leading-edge customers—particularly in logic/foundry and high-bandwidth memory (HBM) DRAM—has already translated into strong revenue contributions. Additionally, early tool shipments for the 1.4nm node reflect continued confidence from top-tier clients and extend ASM’s growth visibility as chipmakers prepare for more complex architectures requiring precise material deposition.

ASMI presented a robust growth trajectory of the single-wafer Atomic Layer Deposition (ALD) market, projected to reach between US$4.2 billion and US$5.0 billion by 2027, with a compound annual growth rate (CAGR) of 10–14% from 2022.

Summary from ASM International Q1 2025 Earnings Call:

1. ALD Market Outlook:
ALD continues to be a key growth driver for ASM, with equipment sales led by ALD and expectations of a strong increase in GAA (gate-all-around) related demand throughout 2025. ALD intensity is rising as leading-edge nodes (2 nm and 1.4 nm) require more deposition steps for complex 3D structures, high-k dielectrics, and metal gate stacks. ASM confirmed ongoing R&D engagement for 1.4nm and highlighted that ALD demand will further accelerate in next-gen nodes, backside power delivery, and in advanced DRAM (e.g. HBM), which increasingly adopt logic-like ALD layers. ASM remains confident in long-term ALD market growth, forecasting double-digit increases in application layers per node.

2. Trade, Tariffs, and Geopolitical Risk:
ASM addressed potential impacts from new US tariff announcements, noting no immediate effect on equipment, but acknowledging possible indirect macroeconomic consequences. The company has prepared multiple mitigation scenarios, including flexible global manufacturing—already expanding in Korea and establishing capability in Arizona (set to scale in 2H 2026). ASM emphasised its ability to localise production quickly if needed. While there’s been no pull-forward of tool orders due to tariff concerns, the company is monitoring the situation closely and maintaining optionality in its supply chain to navigate shifting trade conditions.

ASM International NV (ASMIY) Q1 2025 Earnings Call Transcript | Seeking Alpha

"ASM International: Upgrade To Strong Buy On Better Growth Visibility And Strength"

ASM International (ASMIY) delivered a strong Q1 FY25, exceeding expectations in revenue, margins, and orders, driven by robust AI infrastructure demand, early ramp-up of 2nm nodes, and resilient performance in China. Despite macroeconomic risks and export controls, ASM saw solid contributions from mature logic foundries and high-bandwidth memory (HBM), which relies on advanced techniques like ALD and Epi. The company’s improved operational efficiency, growing AI demand, and clearer long-term growth visibility led the author to upgrade the stock to a “strong buy,” supported by a belief that ASM can reach the high end of its FY27 revenue target with continued margin expansion.

LINK: ASM International: Upgrade To Strong Buy On Better Growth Visibility And Strength (OTCMKTS:ASMIY) | Seeking Alpha

Beneq’s Transform® ALD Tool Qualified for High-Volume GaN Power Device Production by Leading Asian Manufacturer

Beneq has announced the qualification of its Transform® ALD cluster tool for high-volume production of GaN-based power devices on 8-inch GaN-on-Si wafers by a major Tier 1 manufacturer in Asia. This achievement marks a significant step in the adoption of Beneq’s ALD technology for high-performance, scalable, and reliable GaN semiconductor applications, which are essential for power electronics and RF devices in sectors such as automotive, datacenters, and consumer electronics. The Transform system’s unique three-step process—including plasma-based surface pre-cleaning, plasma-enhanced ALD, and thermal ALD—ensures high-quality dielectric integration for wide-bandgap semiconductors like GaN and SiC.

Beneq Transform® establishes a completely new class of ALD cluster tool products in it’s versatility and adaptability to address a broad range of applications and market segments. Beneq Transform® configure with multiple ALD process modules to meet a specific wafer capacity requirement or be later upgraded in response to growing volumes or with new ALD applications. (Beneq.com)

According to Yole Intelligence, the power GaN market is set to surpass $2.2 billion by 2029, growing at a robust 41% CAGR from 2023. This tenfold expansion since 2019 is driven primarily by consumer electronics—especially fast chargers—followed by strong momentum in automotive, data center, telecom, and industrial applications. GaN's adoption is expanding into 300W mobile chargers, automotive LiDAR and onboard chargers (OBCs), high-efficiency power supplies for data centers, and future intermediate bus converters. Bidirectional GaN devices and applications in e-bikes, home appliances, and over-voltage protection (OVP) units are also contributing to market penetration.

The ecosystem is rapidly evolving, with over $4 billion invested in Power GaN since 2019 and major M&A activity including Infineon’s acquisition of GaN Systems and Renesas buying Transphorm. IDMs like STMicroelectronics, Nexperia, and Samsung are building capacity, while 8-inch GaN-on-Si is becoming standard, and early work on 12-inch is underway. Technical advances include 1200V GaN devices, bidirectional switches, and GaN-on-QST substrates. While the market is promising, failures like NexGen and BelGaN highlight the risks and capital intensity required for success​. (Yole Development)

The Beneq Transform tool's vacuum-integrated cluster design supports nitride and oxide film deposition with high throughput and competitive cost-of-ownership, making it suitable for HEMTs, integrated circuits, and vertical devices. Seventeen Transform units are now deployed globally in GaN manufacturing and R&D. The company also strengthens its GaN process innovation through its partnership with imec, where a newly installed Transform system supports ongoing research in GaN surface treatment and dielectric integration.

Key Features of the Transform GaN ALD Process

1. Three-Step ALD Process (Proprietary Architecture):

• Plasma-based surface pre-cleaning: Critical for removing contaminants and native oxides from GaN or SiC surfaces to ensure interface integrity.
• Plasma-enhanced ALD (PEALD) of interfacial layers: Enables low-temperature, conformal deposition with precise control, which is essential for GaN where thermal budgets are constrained.
• Thermal ALD of dielectric films: Offers dense and high-quality films with excellent electrical properties for gate dielectrics and passivation layers.

2. Materials Supported:

• Nitrides: AlN, SiN – important for barrier layers, passivation, or etch stops.
• Oxides: Al₂O₃, HfO₂, SiO₂ – used for gate dielectrics, field plates, and interface engineering.

Sources:

Beneq Transform® Qualified for GaN Power Device Production by Tier 1 Asian Manufacturer

Yole Group - Follow the latest trend news in the Semiconductor Industry

Jusung Engineering Records Strong Financial Performance and Expands ALD Equipment Shipments in 2024

Jusung Engineering Ltd. (KOSDAQ:036930) maintains a strong financial position with a net cash balance of ₩187.2 billion, as its cash reserves of ₩232.2 billion significantly exceed its ₩45.0 billion in debt. Despite total liabilities exceeding cash and receivables by ₩109.4 billion, the company's market capitalization of ₩1.37 trillion suggests that these obligations do not pose a substantial risk. Jusung Engineering's EBIT grew by an impressive 211% over the past year, further strengthening its ability to manage debt. Additionally, with free cash flow amounting to 80% of EBIT over the last three years, the company demonstrates solid cash flow management, reducing concerns over its debt burden. Given these factors, Jusung Engineering appears financially stable, with strong earnings and liquidity to support future growth.

Jusung Engineering shipped atomic layer deposition equipment for DTC silicon capacitor production on the 17th of last month.

In May 2024, Jusung Engineering unveiled plans to restructure its business by spinning off its semiconductor, solar, and display divisions into separate entities. The strategic move aimed to enhance operational efficiency and create greater shareholder value. However, by October 2024, the company decided to cancel the spin-off due to opposition from shareholders. The total stock purchase price for the stocks exercised in opposition exceeded KRW 50 billion, leading to the decision to maintain the company's current structure.

Beyond its financial success, Jusung Engineering made notable advancements in its technology offerings. In November 2024, the company shipped Atomic Layer Deposition (ALD) equipment for the production of Deep Trench Capacitor (DTC) Silicon Capacitors to Elspeth. 

Jusung Engineering's strong financial results, strategic decisions, and technological advancements reinforce its position as a key player in the global semiconductor industry. 

References:

JUSUNG ENGINEERINGLtd (KOSDAQ:036930) Could Easily Take On More Debt - Simply Wall St News

https://www.mk.co.kr/en/business/11231493
https://www.businesskorea.co.kr/news/articleView.html?idxno=216376
https://www.marketscreener.com/quote/stock/JUSUNG-ENGINEERING-CO-LTD-6494704/news/JUSUNG-ENGINEERING-Co-Ltd-cancelled-the-Spin-Off-of-Semiconductor-equipment-research-and-developme-48189649/
https://www.mk.co.kr/en/business/11164246

Forge Nano Expands ALD Capabilities with New TEPHRA™ Cluster Tool and State-of-the-Art Cleanroom

Forge Nano has significantly expanded its semiconductor atomic layer deposition (ALD) capabilities with the completion of a new 2,000 sq ft cleanroom dedicated to manufacturing its TEPHRA™ ALD cluster tools. This expansion comes in response to increased demand for high-throughput ALD solutions in the 200mm wafer market, particularly for advanced packaging, power semiconductor, and microelectromechanical system (MEMS) applications. The new facility, featuring Class 10 (ISO 4) cleanroom space and a dedicated metrology lab, will enable Forge Nano to accelerate production, conduct customer demonstrations, and validate ALD process integration for commercial-scale adoption.

The TEPHRA™ cluster tool is designed to deliver ultrathin, uniform coatings with 10x the throughput of traditional ALD systems, supporting applications such as conformal metal barrier seed layers for through-silicon and through-glass vias (TSVs and TGVs). With customer tool deliveries expected in early 2025, Forge Nano is inviting industry partners to on-site demonstrations showcasing TEPHRA’s capabilities. This expansion reinforces Forge Nano’s position as a key enabler of next-generation semiconductor manufacturing, offering efficient and scalable ALD solutions for the growing demand in advanced node technologies.

Sources:

Blog - Forge Nano

Lam Research’s Dry Resist: A Breakthrough in EUV Lithography for Next-Generation Logic and Memory Manufacturing

Lam Research’s dry resist technology represents a major shift in EUV lithography and semiconductor patterning, addressing critical challenges such as stochastic defectivity, resolution limitations, and cost-efficiency. With recent qualifications for advanced DRAM and 2nm logic manufacturing, along with a growing ecosystem for high-volume production, dry resist is positioned to disrupt traditional chemically amplified resists (CARs) and enable future High-NA EUV adoption.

One of the most significant recent developments is Lam’s qualification of dry resist for 28nm pitch BEOL logic at 2nm and below in collaboration with imec. This qualification confirms that dry resist can eliminate multi-patterning steps, reducing complexity and improving EUV throughput. The process is designed to work with both low-NA and high-NA EUV scanners, ensuring its relevance for sub-2nm logic scaling. This represents a key milestone in extending direct EUV printing to future logic nodes, an approach that could significantly lower lithography costs while improving pattern fidelity.

In addition, a leading DRAM manufacturer has selected Lam’s Aether dry resist technology as its production tool of record for advanced DRAM nodes. This decision highlights dry resist’s low-defect, high-fidelity patterning capabilities, which are essential for scaling memory architectures. The technology enables lower exposure doses while reducing stochastic defects, which are a major concern in EUV-based DRAM production. Given that Samsung, SK Hynix, and Micron are all increasing their reliance on EUV for next-generation DRAM, Lam’s dry resist is well-positioned for widespread adoption in the memory sector.

To ensure a stable supply chain for dry resist materials, Lam Research has partnered with Entegris and Gelest, a Mitsubishi Chemical Group company. This collaboration ensures reliable dual-source precursor production, providing chipmakers with long-term process stability. The partnership also focuses on the development of next-generation high-NA EUV precursors, further strengthening dry resist’s role in future sub-2nm manufacturing.

SEM images of 28 nm pitch line/space patterns imaged with 0.33NA EUV in dry resist from Entegris precursor.

A critical enabler of dry resist technology is its atomic layer deposition (ALD) process, which replaces traditional spin-coating used in CARs. ALD-based vapor-phase deposition offers higher uniformity, eliminating polymer chain variations found in conventional resists. It also allows precise thickness control, which is essential for optimizing EUV photon absorption and etch selectivity. Unlike CARs, which rely on a complex mixture of polymers, dry resist materials are based on single-component metal-organic precursors such as organo-tin oxides. These materials provide higher EUV photon absorption, improving sensitivity and pattern resolution.

Another key advantage of dry resist is its anisotropic dry development process, which replaces wet solvent-based development. Traditional CAR-based EUV resists require organic solvents or aqueous bases, leading to stochastic defects, material loss, and waste. Dry resist, by contrast, is developed entirely in the gas phase, selectively removing unexposed regions and forming a negative-tone image. This eliminates line collapse and delamination issues, improving yield stability. Additionally, the elimination of wet chemistries significantly reduces chemical waste, making dry resist a more sustainable solution with five to ten times lower material consumption compared to traditional resists.

Lam’s dry resist technology is poised to disrupt traditional CAR-based EUV lithography, particularly as the industry moves toward High-NA EUV adoption. By reducing multi-patterning dependency, the technology enhances cost-effective EUV scaling, making it an attractive solution for both logic and memory manufacturers. This positions Lam as a key leader in next-generation EUV resist solutions, challenging conventional resist suppliers like JSR, TOK, and Inpria.

From a sustainability perspective, dry resist significantly lowers EUV exposure dose requirements, leading to higher scanner throughput and lower energy consumption. Its reduced defectivity translates to higher yield per wafer, further enhancing cost-efficiency. The collaboration with Entegris and Gelest ensures supply-chain stability, making dry resist a viable and scalable technology for sub-2nm nodes.

The patent US20220020584A1 mentions several Lam Research tools that play a role in the dry resist deposition, patterning, and development process for EUV lithography. The Altus system is referenced for deposition, likely for metal or dielectric films in the dry resist stack, while the Striker plasma-enhanced atomic layer deposition (PEALD) system may be used for precise resist or underlayer deposition. The Versys platform, known for plasma processing, is relevant to the dry development process, and the Syndion system, typically used for deep silicon etching, may have applications in pattern transfer. Additionally, the Reliant tool is designed for volume manufacturing, possibly adapted for integrating dry resist technology, and the Kiyo plasma etch system is likely involved in etching after the dry resist development stage. These tools collectively enable Lam’s dry resist process to achieve improved resolution, defect reduction, and cost efficiency in advanced EUV lithography.

The patent US20220020584A1, filed by Lam Research Corporation, describes an innovative dry development process for EUV photoresists, which eliminates the need for traditional wet chemical development methods. The patent details a dry resist system deposited via vapor-phase precursors, forming a highly uniform, single-component material that enhances EUV photon absorption and sensitivity. The dry development process selectively removes unexposed resist regions using plasma-based or plasma-free chemical methods, significantly reducing line collapse and defectivity while improving resolution at sub-2nm nodes. By integrating dry resist deposition, EUV exposure, and dry development into a single cluster tool, the patented technology enables scalable, high-volume EUV manufacturing with lower chemical consumption and improved process sustainability, positioning it as a key enabler for High-NA EUV lithography.

Lam Research’s dry resist technology represents a significant development in EUV lithography by addressing key challenges in stochastic defectivity, process cost, and sustainability. Its qualification for 2nm logic and advanced DRAM manufacturing confirms its readiness for high-volume production. By utilizing ALD for precise resist deposition and securing a stable precursor supply through partnerships with Entegris and Gelest, Lam has established a strong foundation for scaling the technology. 

Sources:

Lam Research Press Release on DRAM Adoption (Jan 2025): Lam Research

imec Qualification of Dry Resist for 2nm Logic (Jan 2025): imec

Entegris and Gelest Collaboration Announcement (July 2022): Entegris

Overview of Dry Resist ALD and Precursor Chemistry: SemiAnalysis

ASML High-NA EUV Roadmap and Implications for Dry Resist: ASML

Lam Reserach patent application US20220020584A1: US20220020584A1.pdf

Game-Changing ALD Breakthrough: KJLC Achieves First Scandium Nitride PEALD Process

Revolutionizing Atomic Layer Deposition: Kurt J. Lesker Company's Groundbreaking ALD Publication

January 08, 2025 | By KJLC Innovate 

In the ever-evolving world of semiconductor technology, innovation is the key to staying ahead. At Kurt J. Lesker Company, we are proud to announce a groundbreaking achievement that promises to revolutionize the field of Atomic Layer Deposition (ALD). Our latest publication, featuring the patented Precursor Focusing Technique (PFT) and Ultra-High Purity (UHP) process capability, marks a significant milestone in our commitment to advancing next-generation applications.

The First of Its Kind: Scandium Nitride by PEALD

For the first time, scandium nitride (ScN) has been successfully deposited using plasma-enhanced atomic layer deposition (PEALD) on silicon, sapphire, and magnesium oxide substrates under UHP conditions. This innovative process utilizes a new scandium precursor, bis(ethylcyclopentadienyl)scandium-chloride [ClSc(EtCp)2], combined with N2-H2 plasma species, allowing for the deposition of high-quality ScN films at relatively low temperatures (200−300°C).

Why This Publication is a Game-Changer

The significance of this publication lies in its potential to transform various advanced electronic applications. The ScN films produced by this process exhibit high crystalline quality and excellent electrical properties, with high mobility and low resistivity. These characteristics make them suitable for a wide range of applications, including thermoelectric devices and as an interlayer for epitaxial gallium nitride (GaN) growth.

Moreover, the ability to conformally coat high aspect ratio (HAR) structures is particularly valuable for applications in 3D embedded memory and piezoelectric microelectromechanical systems (piezoMEMS). Traditional sputtering techniques are not suitable for these applications involving complex 3D architectures, making this new ALD process a significant advancement.

The Commercial Relevance of ScN

Scandium nitride is commercially relevant primarily because it forms a solid solution with aluminum nitride (AlN), resulting in aluminum scandium nitride (Al1-xScxN), which enables ferroelectric switching. Al1-xScxN thin films are traditionally deposited via reactive magnetron sputtering, which yields highly c-axis oriented columnar grains. However, sputtering is not suitable for coating high-aspect ratio (HAR), vertically layered structures such as those desired for use in 3D embedded memory.

Recently, there have been several reports of piezoelectric AlN grown by atomic layer deposition (ALD) techniques that have shown promising crystalline quality and properties. However, there are no reports of ALD Al1-xScxN, principally because there are no reported ALD processes for ScN. This publication addresses this gap, providing a new method for depositing high-quality ScN films.

Looking Ahead

As KJLC continues to push the boundaries of ALD technology, we are excited about the possibilities our new research and development opens up. From thermoelectrics to applications involving high-aspect ratio (HAR) architectures such as 3D embedded memory and piezoMEMS technology, the high crystalline and electrical quality demonstrated here for ScN by PEALD techniques is just the beginning.

Sources:

https://www.lesker.com/blog/revolutionizing-ald-kjlcs-groundbreaking-ald-publication - Blog article

https://www.lesker.com/newweb/vacuum_systems/pdf/jva24-le-gl2025-00618.pdf - Paper Download