TSMC’s
New, Industry-Leading 2nm CMOS Logic Platform: In a late-news paper, TSMC researchers will
unveil the world’s most advanced logic technology. It is the company’s
forthcoming 2nm CMOS (i.e., N2), platform, designed for energy-efficient
computing in AI, mobile, and HPC applications. It offers a 15% speed gain (or
30% power reduction) at >1.15x chip density versus the most advanced logic
technology currently in production, TSMC’s own 3nm CMOS (N3) platform,
introduced in late 2022.
The new N2 platform features GAA nanosheet
transistors; middle-/back-end-of-line interconnects with the densest SRAM macro
ever reported (~38Mb/mm2); and a holistic, system-technology
co-optimized (STCO) architecture offering great design flexibility. That
architecture includes a scalable copper-based redistribution layer and a flat
passivation layer (for better performance, robust CPI, and seamless 3D
integration); and through-silicon vias, or TSVs (for power/signal with F2F/F2B
stacking). The researchers say the N2 platform is currently in risk production
and scheduled for mass production in 2H’ 25. N2P (5% speed enhanced version of
N2) targets to complete qualification in 2025 and mass production in 2026.
The cross-sectional
image shows that the N2 platform’s Cu redistribution layer (RDL) and
passivation provide seamless integration with 3D technologies.
Graph showing that the new N2 high-density cells gain 14~15% speed@power vs. N3E FinFlex 2-1 fin cells across the Vdd range; a 35% power savings at higher voltage; and a 24% power savings at lower voltage
The graph above compares two CMOS technology nodes, TSMC's N3E and N2, specifically for Arm's A715 core. N3E FinFlex (2-1 Fin) architecture, represented by the blue dotted line, operates at higher power but achieves higher speed than previous nodes. Operating at voltages between 0.5V and 0.9V, the N3E design can achieve significant performance levels but comes with a power increase. Now, N2 NanoFlex HD (High-Density) Energy-Efficient Cells as in the The N2 node, marked by the green dotted line, introduces "NanoFlex" cells that are optimized for energy efficiency. Compared to N3E, it achieves similar speeds but with substantially lower power consumption, marking a shift toward lower power designs in advanced nodes.
Key Improvements:
- When shifting from 0.6V to 0.55V in the N3E architecture, there's a 15% reduction in speed but a 24% reduction in power.
- For N2, at 0.85V, there's a 14% reduction in speed and a 35% reduction in power compared to similar performance points in N3E.
- These efficiency improvements are essential for high-performance applications in power-sensitive environments.
In summary, TSMC's N3E focuses on performance with FinFlex technology, while N2's NanoFlex HD cells target power efficiency, marking a clear trend in CMOS architecture evolution for balancing power and speed.
For the latest insights from the 2024 IEEE International Electron Devices Meeting (IEDM), including groundbreaking advancements in 2nm CMOS logic, extremely scaled transistors, monolithic CFET inverters, energy-efficient 3D computing-in-memory, and novel device technologies, you can explore the full press kit
here.
Sources:
IEDM Press kit Paper #2.1, “2nm Platform Technology Featuring Energy-Efficient Nanosheet Transistors and Interconnects Co-Optimized with 3DIC for AI, HPC and Mobile SoC Applications,” G. Yeap et al, TSMC
https://www.ieee-iedm.org/press-kit
%20(1).png)
