4F² DRAM developed by a Kioxia using ALD IGZO

The new 4F² DRAM developed by a Kioxia-led team combines gate-all-around (GAA) IGZO (indium-gallium-zinc oxide) vertical channel transistors (VCTs) with a unique design that places transistors above high-aspect-ratio capacitors to reduce thermal stress and suppress electrical interference like "row hammer." This structure increases memory density and efficiency, providing a high on/off current ratio essential for low-power operation. The team demonstrated a 275Mbit array with this technology, indicating its potential to enable high-density, low-power DRAM for advanced computing applications.

Kioxia is traditionally known for its expertise in NAND flash memory rather than DRAM. They are one of the leading companies in the NAND space, focusing primarily on storage solutions. However, this new venture into DRAM with innovative 4F² cell structures signals an expansion of their research and development scope, possibly to leverage their materials and process expertise in a closely related area. It suggests Kioxia may be exploring ways to diversify its technology portfolio, potentially addressing high-density memory needs beyond traditional NAND storage

ALD offers atomic-level precision and is beneficial for creating uniform, conformal layers of IGZO in complex, high-aspect-ratio surfaces demonstrated here, which is particularly advantageous in advanced semiconductor applications. ALD works by exposing the substrate to alternating pulses of indium, gallium, and zinc precursors, separated by purges to prevent unwanted reactions. This controlled process achieves a smooth and consistent IGZO layer with excellent thickness control, crucial for sensitive electronic applications like DRAM devices.

New Type of 4F² DRAM: DRAM is the workhorse memory of electronic systems, but patterning the extremely small features of conventional silicon 6F² DRAM memory cells and suppressing “row hammer” electrical interference from nearby cells are major challenges. To overcome them, the industry has been actively developing denser 4F² DRAM designs made with different materials. A Kioxia-led team will describe a new type of 4F² DRAM, comprising GAA IGZO (indium-gallium-zinc oxide) vertical channel transistors (VCTs) and a new integration scheme, where the heat-sensitive transistors are placed on the top of high aspect-ratio capacitors instead of on the bottom, to reduce the thermal impact from BEOL processing below. The vertical architecture also fully suppresses row hammer interference, because the active region isn’t shared with adjacent cells. The InGaZnO VCT achieved more than 15µA/cell ON current and 1aA/cell OFF current. The researchers demonstrated the technology by successfully building a 275Mbit array with it, demonstrating its potential for future high-density, low-power DRAM technologies.

 

Above:

(a)   is a schematic of the oxide-semiconductor channel transistor DRAM. The InGaZnO VCT was integrated on a capacitor array, a different architectural scheme from silicon-based 4F2 DRAM devices.

(b)   is a cross-sectional TEM image of the InGaZnO VCT test structure, with the key technologies needed for DRAM applications described on the right nearby. The gate oxide and InGaZnO were formed in a 26nm-diameter vertical hole.

(c)   is a cross-sectional TEM showing the InGaZnO VCTs on high-aspect-ratio capacitors.

 Source:

IEDM2024 Paper #6.1, “Oxide-Semiconductor Channel Transistor DRAM (OCTRAM) with 4F² Architecture,” S. Fujii et al, Kioxia Corp./Nanya Technology Corp. https://www.ieee-iedm.org/press-kit