Spatial ALD vs Temporal ALD - HERALD workshop on Fundamentals of ALD at TU/e

As reported earlier, there will be a Cost Action "HERALD" workshop on Fundamentals of ALD - June 8 & 9, Eindhoven organized by Erwin Kessels Professor in Applied Physics at Eindhoven University of Technology. June 8 (start at noon) to June 9 (end mid-afternoon). Please see http://www.nanomanufacturing.nl/ .

One of the sessions will be on Spatial ALD vs Temporal ALD as described by this two pager (here) and briefly summarized below. 

"Spatial Atomic Layer Deposition is an ALD method that emerged the past few years, allowing high throughput ALD for a number of applications and processes. It relies on a spatial separation of precursor exposures instead of temporal separation in conventional ALD. Spatial ALD has found use particular in large - area and/or flexible electronics, such as photovoltaics, OLED lighting and displays, where the unique qualities of ALD are a clear asset, but where high throughput processing (e.g, roll-to-roll) is required. There are several different ways to do Spatial ALD (atmospheric vs low-pressure, R2R, S2S, plasma, etc.)but in all cases it is an equipment enabled method and they share a common feature: it is all ALD."

A Spatial ALD reaction scheme where the precursors are dosed simultaneously and continuously in half-reaction precursor zones separated by inert gas zones. Moving the substrate through two half-reaction zones completes one ALD cycle (Poodt et al., J. Vac. Sci. Technol. A 30, 010802 (2012))

The following topics will be addressed during the introduction:

• Basic introduction Spatial ALD and comparison with conventional ALD
• Time scales in ALD, and what does “deposition rate” mean in ALD
• Atmospheric vs. low-pressure ALD
• Kinetics of Spatial ALD
• The balance between deposition rate, uniformity, performance and costs

  

InAs Nanowire Transistors with Multiple Independent Wrap-Gate Segments

The Nanometer Structure Consortium (nmC) at, Lund University Sweden and School of Physics, University of New South Wales, Australia demonstrate a method for making horizontal wrap-gate nanowire transistors with up to four independently controllable wrap-gated segments. The excellent scalability potential of horizontal wrap-gate nanowire transistors makes them highly favorable for the development of advanced nanowire devices and possible integration with vertical wrap-gate nanowire transistors in 3D nanowire network architectures.

InAs Nanowire Transistors with Multiple, Independent Wrap-Gate Segments
A. M. Burke, D. J. Carrad, J. G. Gluschke, K. Storm, S. Fahlvik Svensson, H. Linke, L. Samuelson, and A. P. Micolich
Nano Lett., Article ASAP, DOI: 10.1021/nl5043243

AN InAs Nanowire Transistors with Multiple, Independent Wrap-Gate Segments (Graphical Abstracts Nano Lett., Article ASAP, DOI: 10.1021/nl5043243)

We report a method for making horizontal wrap-gate nanowire transistors with up to four independently controllable wrap-gated segments. While the step up to two independent wrap-gates requires a major change in fabrication methodology, a key advantage to this new approach, and the horizontal orientation more generally, is that achieving more than two wrap-gate segments then requires no extra fabrication steps. This is in contrast to the vertical orientation, where a significant subset of the fabrication steps needs to be repeated for each additional gate. We show that cross-talk between adjacent wrap-gate segments is negligible despite separations less than 200 nm. We also demonstrate the ability to make multiple wrap-gate transistors on a single nanowire using the exact same process. The excellent scalability potential of horizontal wrap-gate nanowire transistors makes them highly favorable for the development of advanced nanowire devices and possible integration with vertical wrap-gate nanowire transistors in 3D nanowire network architectures.

The world smallest crak created by UCSD

Interesting work on making the smallest possible crack using graphene or so called nano gaps. In this case the use of single-layer graphene is used as a template for the formation of subnanometer plasmonic gaps using a scalable fabrication process called “nanoskiving.” The research was carried out by the University of California, San Diego (UCSD) and has been published in the journal Nano Letters.

Read more in the Digital Journal: http://www.digitaljournal.com/science/graphene-yields-the-world-s-smallest-crack/article/432079#ixzz3YttHgLeo

Athermally photoreduced graphene oxides for three-dimensional holographic images

Aliaksandr V. Zaretski , Brandon C. Marin , Herad Moetazedi , Tyler J. Dill , Liban Jibril , Casey Kong , Andrea R. Tao , and Darren J. Lipomi
Nano Lett., 2015, 15 (1), pp 635–640, DOI: 10.1021/nl504121w

This work demonstrates the use of single-layer graphene as a template for the formation of subnanometer plasmonic gaps using a scalable fabrication process called “nanoskiving.” These gaps are formed between parallel gold nanowires in a process that first produces three-layer thin films with the architecture gold/single-layer graphene/gold, and then sections the composite films with an ultramicrotome. The structures produced can be treated as two gold nanowires separated along their entire lengths by an atomically thin graphene nanoribbon. Oxygen plasma etches the sandwiched graphene to a finite depth; this action produces a subnanometer gap near the top surface of the junction between the wires that is capable of supporting highly confined optical fields. The confinement of light is confirmed by surface-enhanced Raman spectroscopy measurements, which indicate that the enhancement of the electric field arises from the junction between the gold nanowires. These experiments demonstrate nanoskiving as a unique and easy-to-implement fabrication technique that is capable of forming subnanometer plasmonic gaps between parallel metallic nanostructures over long, macroscopic distances. These structures could be valuable for fundamental investigations as well as applications in plasmonics and molecular electronics.



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Major a step towards atomically thin integrated circuitry by Cornell

A major a step towards atomically thin integrated circuitry has been taken by Cornell University. Nature reports that atomically thin layers of semiconductor transition-metal dichalcogenides have been grown uniformly on the square-centimetre scale by the reserachers from Cornell — possibly paving the way for the ultimate miniaturization of electronic applications.

High-mobility three-atom-thick semiconducting films with wafer-scale homogeneity
Kibum Kang, Saien Xie, Lujie Huang, Yimo Han, Pinshane Y. Huang, Kin Fai Mak, Cheol-Joo Kim, David Muller & Jiwoong Park

Nature 520, 656–660 (30 April 2015) doi:10.1038/nature14417

The large-scale growth of semiconducting thin films forms the basis of modern electronics and optoelectronics. A decrease in film thickness to the ultimate limit of the atomic, sub-nanometre length scale, a difficult limit for traditional semiconductors (such as Si and GaAs), would bring wide benefits for applications in ultrathin and flexible electronics, photovoltaics and display technology. For this, transition-metal dichalcogenides (TMDs), which can form stable three-atom-thick monolayers, provide ideal semiconducting materials with high electrical carrier mobility, and their large-scale growth on insulating substrates would enable the batch fabrication of atomically thin high-performance transistors and photodetectors on a technologically relevant scale without film transfer. In addition, their unique electronic band structures provide novel ways of enhancing the functionalities of such devices, including the large excitonic effect, bandgap modulation, indirect-to-direct bandgap transition, piezoelectricity and valleytronics. However, the large-scale growth of monolayer TMD films with spatial homogeneity and high electrical performance remains an unsolved challenge. Here we report the preparation of high-mobility 4-inch wafer-scale films of monolayer molybdenum disulphide (MoS₂) and tungsten disulphide, grown directly on insulating SiO₂ substrates, with excellent spatial homogeneity over the entire films. They are grown with a newly developed, metal–organic chemical vapour deposition technique, and show high electrical performance, including an electron mobility of 30 cm² V⁻¹ s⁻¹ at room temperature and 114 cm² V⁻¹ s⁻¹ at 90 K for MoS₂, with little dependence on position or channel length. With the use of these films we successfully demonstrate the wafer-scale batch fabrication of high-performance monolayer MoS₂ field-effect transistors with a 99% device yield and the multi-level fabrication of vertically stacked transistor devices for three-dimensional circuitry. Our work is a step towards the realization of atomically thin integrated circuitry.



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OLED Encapsulation: technological introduction and market status | OLED-Info

OELD-info has a very good  technological introduction and market review on OLED encapsulation, whis you can read here. Check it out and read about the main players of ALD OEMs in this field as published by OLED-info:

• Vacuum Polymer Technology: developed at Vitex and bought by Samsung in 2010, this is the technology currently used by Samsung. It is a multi-layer barrier that is relatively slow to deposit as it requires several stages (SDC recently managed to reduce them from 6 to 3) and so Samsung is looking to replace it with a more cost effective solution.
• LG's Faceseal: LG's own encapsulation technology, this is a a multi-layered organic and in-organic film. LG Display currently uses Faceseal for both flexible OLED display and lighting panels.
• Atomic Layer Deposition (ALD): ALD can be used to quickly and efficiently deposit barrier films on flexible substrates. Several companies are developing OLED encapsulation systems based on ALD. One example is Veeco with their FAST-ALD tech (which they acquired in 2013 for $185 million) which is being evaluation by Samsung. Other OLED ALD developers include Beneq and Encapsulix.
• Ink Jet Printing: While ink-jet is usually associated with micro-scale patterning, it can also be used to accurately and efficiently deposit encapsulation layers. In November 2014 Kateeva launched an Ink Jet Printing based Encapsulation system, and already shipped a mass-scale system - presumably to Samsung Display. 
• PECVD: Plasma Enhanced Chemical Vapor Deposition (PECVD) is another deposition technology that can be adapted for encapsulation barrier films. In 2015 Aixtron acquired PlasmaSi, a PECVD OLED encapsulation developer - and plans to incorporate those systems into its OLED deposition clusters.
• UniversalBarrier: This technology, developed by Universal Display (UDC), can be used to deposit single-layer encapsulation films. According to the latest update from UDC, the technology is not yet ready for mass production, but it is already being evaluation by Samsung Display.
• Flexible glass: Yes, it is possible to make flexible glass - which is a great barrier, but still not as durable as thin-film encapsulation materials. Corning for example is promoting its Willow Glass as a possible flexible glass encapsulation (and substrate) technology.