Showing posts with label DRAM. Show all posts
Showing posts with label DRAM. Show all posts

Monday, September 12, 2016

Major memory manufacturer qualifies AIXTRON’s QXP-8300 mini-batch ALD system

AIXTRON reaches important milestone for its silicon semiconductor manufacturing technology

AIXTRON SE (FSE: AIXA; NASDAQ: AIXG), a worldwide leading provider of advanced deposition equipment to the semiconductor industry, announced today that a major memory manufacturer has qualified its

 QXP-8300 Atomic Layer Deposition (ALD) mini-batch system (www.aixtron.com)

QXP-8300 Atomic Layer Deposition (ALD) mini-batch system suitable for high-k oxide films in various advanced memory applications including 3D structure devices. 

“We are delighted that our customer has completed the evaluation of our QXP-8300 ALD system for the manufacturing of the most advanced high performance memory devices. The QXP-8300 ALD system enables the manufacturing of advanced films with excellent electrical and device properties. AIXTRON is looking forward to further support its customer’s memory development plans by providing the production equipment to address the challenges of a rapidly evolving industry,” says Bill Bentinck, Vice President and General Manager of AIXTRON Inc., USA. 

As the semiconductor memory cell size continues to be scaled down, manufacturers need advanced technologies for the deposition of precise layers of dielectric, metal and non-volatile memory materials. AIXTRON’s QXP-8300 ALD system includes the patented TriJet vaporizer technology integrated with the unique close coupled showerhead design that enables the use of low vapor pressure precursors as needed in making higher-k dielectrics and metal nitrides for the performance improvement.

Thursday, August 11, 2016

Tokyo Electron to Begin Accepting Orders for Triase+™ EX-II™ TiON

Simultaneously as Lam Research launches Fluorine free Tungsten for 3DNAND and DRAM, Tokyo Electron is launching their newset version of the market leading TiN Trias Tool that has been dominated the TiN MIM Capacitor electrode (e.g. DRAM memory cells) market since there was a market for it. The first version that was rolled out to most DRAM fabs at the introduction of high-k used a processes called SFD - Sequential Flow Deposition, which is a sort of pulsed CVD with  proprietary reductive gas flow pulses by NH3. Later a even more advanced processes called ASFD -  Advanced Sequential Flow Deposition has been developed. The key to these type of TiCl4/NH3 based processes is that it will always beat ALD in terms of throughput without compromising in film quality including great stepcoverage, i.e., conformal growth. Yet another reason why Tokyo Electron has been dominating the TiN market is the use of in-situ clean by ClF3. 
 




 
Tokyo Electron to Begin Accepting Orders for Triase+™ EX-II™ TiON, a Single-Wafer Metallization System

Aug 8, 2016 Tokyo Electron Limited (TEL) announced today that it would begin accepting orders for the Triase+TM EX-IITM TiON (titanium oxynitride) single-wafer metallization system in August 2016.

The Triase+ EX-II TiON is a high-speed, single-wafer ASFD  [1] system capable of oxidizing TiN (titanium nitride) films. This new system inherits the optimized reactor chamber and unique gas injection mechanism that characterize the Triase+ EX-II TiN system. Because the TiON film deposited by the Triase+ EX-II TiON has a higher work function [2] than that of a conventional TiN film, it effectively reduces leakage current when used to form the electrodes of an MIM capacitor [3]. Customers already using the TiN system can upgrade to the TiON system by modifying their existing systems, thereby reducing investment costs.

"The Triase+ EX-II TiON is a product with significant cost and performance benefits that can meet the continual demand for miniaturization in semiconductor manufacturing processes," said Shingo Tada, Vice President and General Manager of Thin Film Formation BU at TEL. "We intend to keep expanding the type of films the Triase+ EX-II series can handle, enabling it to cover an even greater variety of metallization applications in the future."

Leveraging its ability to develop innovative technologies, TEL will continue to deliver products that add high value and optimize solutions to the technological problems associated with advanced devices.


[1] ASFD: Advanced Sequential Flow Deposition. A low-temperature processing method for forming nanoscale metal films with highly-engineered properties.
[2] Work function: The minimum quantity of energy required to remove an electron from the surface of a solid.
[3] MIM capacitor: Metal-Insulator-Metal capacitor. It consists of an insulator layer between two metal layers.

Wednesday, August 10, 2016

[UPDTAE] Lam Research launch New ALTUS(R) Max E Series for Low-fluorine, Low-stress, and Low-resistivity ALD Tungsten

[UPDATE] :  Lam Blog - Innovative Tungsten ALD Process Provides Pathway to New Memory Chip Production : http://blog.lamresearch.com/innovative-tungsten-ald-process-provides-pathway-to-new-memory-chip-production/


 ALTUS Max E Series 4 station chambers (Picture from Lam Blog)

FREMONT, CA -- (Marketwired) -- 08/09/16 -- Lam Research Corp. (NASDAQ: LRCX), an advanced manufacturer of semiconductor equipment, today introduced an atomic layer deposition (ALD) process for depositing low-fluorine-content tungsten films, the latest addition to its industry-leading ALTUS® family of products. With the industry's first low-fluorine tungsten (LFW) ALD process, the ALTUS Max E Series addresses memory chipmakers' key challenges and enables the continued scaling of 3D NAND and DRAM devices. Building on Lam's market-leading product portfolio for memory applications, the new system is gaining market traction worldwide, winning production positions at leading 3D NAND and DRAM manufacturers and placement at multiple R&D sites.

ALTUS Max E Series 4 station chambers shuffling wafers (Picture from Lamresearch.com)

"Consumer demand for ever more powerful devices is driving the need for high-capacity, high-performance storage, and deposition and etch are key process technology enablers of advanced memory chips," said Tim Archer, Lam's chief operating officer. "With the addition of the ALTUS Max E Series, we are expanding our memory portfolio and enabling our customers to capitalize on this next wave of industry drivers. Over the past twelve months, as the 3D NAND inflection has accelerated, we have doubled our shipments for these applications, leading to the largest deposition and etch installed base in our 3D NAND served markets."

As manufacturers increase the number of memory cell layers for 3D NAND, two issues have become apparent for tungsten deposition in the word line fill application. First, fluorine diffusion from the tungsten film into the dielectrics can cause physical defects. Second, higher cumulative stress in devices with more than 48 pairs has resulted in excessive bowing. The resulting defects and stress can cause yield loss, as well as degraded electrical performance and device reliability. Because of these issues, tungsten films for advanced 3D NAND devices must have significantly reduced fluorine and intrinsic stress. Further, as critical dimensions shrink, resistance scaling becomes more challenging for the DRAM buried word line, as well as for metal gate/metal contact applications in logic devices.

"As memory chip manufacturers move to smaller nodes, the features that need to be filled are increasingly narrow and have higher aspect ratios," said Sesha Varadarajan, group vice president, Deposition Product Group. "Lam's new LFW ALD solution uses a controlled surface reaction to tune stress and fluorine levels and to lower resistance, all while delivering the required tungsten fill performance and productivity. When compared to chemical vapor deposition tungsten, the ALTUS Max E Series lowers fluorine content by up to 100x, lowers stress by up to 10x, and reduces resistivity by over 30%, solving some of our customers' most critical scaling and integration challenges."

The ALTUS Max E Series with LFW ALD technology offers a unique all-ALD deposition process that leverages Lam's PNL® (Pulsed Nucleation Layer) technology, which is the industry benchmark for tungsten ALD with 15 years of market leadership and more than 1,000 modules in production. Lam led the transition of chemical vapor deposition (CVD) tungsten nucleation to ALD tungsten nucleation with its PNL technology. The company continued that leadership by advancing low-resistivity tungsten solutions with its products ALTUS® Max with PNLxT™, ALTUS® Max with LRWxT™, and ALTUS® Max ExtremeFill™ for enhanced fill performance.

The ALTUS products use Lam's quad-station module (QSM) architecture to allow per-station optimization of tungsten nucleation and fill for fluorine, stress, and resistance without compromising fill performance since station temperature can be set independently. The QSM configuration also maximizes productivity of the all-ALD process by providing up to 12 pedestals per system, enabling the highest footprint productivity in the industry.

Friday, June 24, 2016

Harvard University initiates ALD patent infringement suits towards US chip makers

Harvard University initiates patent infringement suits to protect inventors’ rights in atomic layer deposition alkyl amide precursor used for High-k applications like DRAM and other high aspect ratio capacitor based technologies. 
 
 

Harvard has now filed patent-infringement suits against two major US chip makers, Micron and Globalfoundries. The University believes that these companies have violated patents that claim inventions created in Gordon’s lab of famous ALD Prof. Roy Gordon.
 
The article in The Harvard Gazette reports:
 
Over a few years, Gordon, his graduate students Jill Becker [Founder of Cambridge Nanotech] and Dennis Hausmann [Lam Research], and postdoctoral fellow Seigi Suh [DuPont] would play central roles in making that high-k dielectric insulator work. Their primary innovation, filed at the U.S. Patent Office in 2000 and described in scientific papers in 2001 and 2002, was to create a novel carrier molecule, one never before seen outside of Gordon’s lab, as well as to identify a class of precursor molecules ideally suited to use in a method called atomic layer deposition (ALD) to create thin films. This precursor molecule delivered the insulator where it had to go. Once there it released the metal atoms to form a uniform layer, while its other components — such as carbon, nitrogen, and hydrogen — were easily removed, leaving behind the pure insulator layer.

Isaac T. Kohlberg, Harvard’s senior associate provost, said it’s important that Harvard protect the intellectual property rights of faculty, postdoctoral researchers, students, and the University itself, particularly in an era when corporations increasingly look to academia for significant advances in science, engineering, and technology.

Here you can read the whole intriguing story from Gordon Lab in the Harvard Gazette : Defending breakthrough research. Here is also one of the well cited publications form 2002 on using TEMAHf and TEMAZr and water in deep trench DRAM stuctures (from Infineon) by Hausman et al : http://faculty.chemistry.harvard.edu/files/gordon/files/aldhf_3.pdf

There are many angles to this story and it will be interesting to follow this case.

Thursday, April 7, 2016

Samsung Starts Mass Producing Industry’s First 10-Nanometer Class DRAM

Samsung just announced that they start Mass Producing Industry’s First 10-Nanometer Class DRAM now. According to the press release (here) the key technology developments include:
  • improvements in proprietary cell design technology
  • QPT - quadruple patterning technology lithography 
  • Ultra-thin dielectric layer deposition.
The two later ones should mean a lot of ALD business for High-k, Electrodes and dielectric spacers.

Below is a DRAM Technology Roadmap published by TechInsights last summer and here you can see that Samsung is nailing it and next we should expect announcements from SK Hynix and The Micron Camp.


Here is an earlier post form IEDM 2015 in December when Samsung revieled some details - if thoose are used here is unknown so hopefully some reverse engineering study will surface next:

Samsung to present low cost manufacturing of 20 nm DRAM and beyond at IEDM2015

Some advancement in keeping low cost manufacturing of 20 nm DRAM will be presented by Samsung at IEDM 2015. Key elements are:

  • avoiding EUV lithography
  • honeycomb structure (see figure below)
  • air-spacer technology


According to Solid State Technology an air-gap spacer arrangement achieves a 34% reduction in bitline capacitance for faster operation.

20nm DRAM: A New Beginning of Another Revolution (Invited), J. Park, Y.S. Hwang, S.-W. Kim, S.Y. Han, J.S. Park, J. Kim, J. W Seo, B.S. Kim, S.H. Shin, C.H. Cho, S.W. Nam, H.S. Hong, K.P. Lee, G.Y. Jin, and E.S. Jung, Samsung Electronics Co.


For the first time, 20nm DRAM has been developed and fabricated successfully without EUV lithography using the honeycomb structure and the air-spacer technology. These low-cost and reliable schemes are promising key technologies for 20nm technology node and beyond.



Tuesday, February 9, 2016

Sub 20nm DRAM High-k from NaMLab, RWTH, KU Leuven and Samsung

NaMLab in Dresden, RWTH Aachen,Germany, KU Leuven, Belgium and Samsung has quite successfully since some years been collaborating on further high-k development for sub 20 nm DRAM. The research is lead by Uwe Schröder (ex-Qimonda High-k Principal) and Kyhyo Cho from Samsung. Here is a recent paper on how to push the ZrO2 based high-k further to even lower CET and leakage performance by introducing SrO inter layer high-k. Please enjoy this open source publication - abstract is given below.

Instead of STO based high-k that is physically too thick to fit in a sub 20nm DRAM cell, two different new approaches to develop a new ZrO based DRAM capacitor stack are presented:

1) by changing the inter-layer material from AlO to SrO 
2) the exchange of the top electrode material from TiN to Pt 

Low leakage ZrO based capacitors for sub 20 nm dynamic random access memory technology nodes

Milan Pešić, Steve Knebel, Maximilian Geyer, Sebastian Schmelzer, Ulrich Böttger, Nadiia Kolomiiets, Valeri V. Afanas'ev, Kyuho Cho, Changhwa Jung, Jaewan Chang, Hanjin Lim, Thomas Mikolajick and Uwe Schroeder
J. Appl. Phys. 119, 064101 (2016); http://dx.doi.org/10.1063/1.4941537
 
 
 

During dynamic random access memory (DRAM) capacitor scaling, a lot of effort was put searching for new material stacks to overcome the scaling limitations of the current material stack, such as leakage and sufficient capacitance. In this study, very promising results for a SrTiO based capacitor with a record low capacitance equivalent thickness value of 0.2 nm at target leakage current are presented. Due to the material properties of SrTiO films (high vacancy concentration and low band gap), which are leading to an increased leakage current, a physical thickness of at least 8 nm is required at target leakage specifications. However, this physical thickness would not fit into an 18 nm DRAM structure. Therefore, two different new approaches to develop a new ZrO based DRAM capacitor stack by changing the inter-layer material from AlO to SrO and the exchange of the top electrode material from TiN to Pt are presented. A combination of these two approaches leads to a capacitance equivalent thickness value of 0.47 nm. Most importantly, the physical thickness of <5 nm for the dielectric stack is in accordance with the target specifications. Detailed evaluation of the leakage current characteristics leads to a capacitor model which allows the prediction of the electrical behavior with thickness scaling.

Tuesday, December 1, 2015

Samsung to present low cost manufacturing of 20 nm DRAM and beyond at IEDM2015

Some advancement in keeping low cost manufacturing of 20 nm DRAM will be presented by Samsung at IEDM 2015. Key elements are:

  • avoiding EUV lithography
  • honeycomb structure (see figure below)
  • air-spacer technology


According to Solid State Technology an air-gap spacer arrangement achieves a 34% reduction in bitline capacitance for faster operation.

20nm DRAM: A New Beginning of Another Revolution (Invited), J. Park, Y.S. Hwang, S.-W. Kim, S.Y. Han, J.S. Park, J. Kim, J. W Seo, B.S. Kim, S.H. Shin, C.H. Cho, S.W. Nam, H.S. Hong, K.P. Lee, G.Y. Jin, and E.S. Jung, Samsung Electronics Co.


For the first time, 20nm DRAM has been developed and fabricated successfully without EUV lithography using the honeycomb structure and the air-spacer technology. These low-cost and reliable schemes are promising key technologies for 20nm technology node and beyond.

Friday, November 27, 2015

ACHTUNG High-k Samsung supply ALD High-k for Audi

Vorsprung durch Technik - Advancement through technology - finally some ALD high-k will be introduced also for automotive electronics! As reported by Computer Business Review : "Samsung Electronics has become the first semiconductor memory supplier for Audi's Progressive SemiConductor Programme. Samsung will provide 20-nanometer LPDDR4 DRAM and 10-nanometer class eMMC (embedded multimedia card) 5.1 chips to Audi. "

Press release from Samsung : http://news.samsung.com/global/samsung-joins-audis-progressive-semiconductor-program-to-create-the-drive-of-tomorrow






Dr. Kinam Kim, President of Semiconductor Business form the Device Solutions Division of Samsung Electronics, and Ricky Hudi, Executive Vice President Electronic Development of Audi.
President of Samsung Electronics Semiconductor Business Kim Ki-nam (left) signs a contract with Executive Vice President of Audi Ricky Hudi to supply automotive semiconductors on Nov. 23 (local time). - See more at: http://www.businesskorea.co.kr/english/news/industry/13112-progressive-semiconductor-samsung-electronics-supply-automotive-semiconductors#sthash.a68eYl61.dpuf
President of Samsung Electronics Semiconductor Business Kim Ki-nam (left) signs a contract with Executive Vice President of Audi Ricky Hudi to supply automotive semiconductors on Nov. 23 (local time). - See more at: http://www.businesskorea.co.kr/english/news/industry/13112-progressive-semiconductor-samsung-electronics-supply-automotive-semiconductors#sthash.a68eYl61.dpuf

"The chips are expected to be used to power Audi's future infotainment, dashboard and driver assistance applications. Audi presently has an advanced driver assistance system which includes a predictive efficiency assistant, adaptive cruise control, and traffic jam assist. In September, Samsung launched the 12Gb LPDDR4 that has the largest capacity and highest speed available for a DRAM chip. It provides 50% greater density than the existing 8GB chips used in current smartphones, and it is also expected to help smartphones and tablets to have up to 6GB of RAM."


LPDDR4 DRAM from Sasmsung

Audi Electronic Development executive vice president Ricky Hudi said: "Samsung is leading memory technology development with its high-performance, high-density DRAM and NAND flash memory solutions based on the industry's most advanced process technology.


From a Chipworks report abstract that can be bought here, we can see a cross section of the stack capacitor array Samsung is using at 26 nm (see below). For 20 nm I have not been able to find any free available information yet

"Through the PSCP strategic partnership with Samsung, Audi will utilize Samsung's high speed memory products to provide the best user experience to our customers.



I am not an Audi driver but I like this picture (Picture from Audi)




Monday, July 27, 2015

Hynix high bandwidth memory in an AMD Radeon ALD High-k Fury

Check it out - this is like the coolest thing I have ever seen so far - the two leading ALD High-k products (DRAM & High performance CMOS) merged into one ultra high performance graphics chip by AMD. TechInsights has investigated the AMD Fury X cards in their lab  and published it in a series of articles in EE Times:

The Hunt for Hynix HBM - Hynix high bandwidth memory addresses bandwidth limitations


Accordingly, SK Hynix announced its high bandwidth memory (HBM) product in early 2014, claiming it to be the world’s first 8Gb module made using 2Gb, 20nm node, DDR4 SDRAM. Now the HBM modules has shown up in product - AMD’s Radeon 390X Fury X graphics card.



According to TechInsight : "Hynix disclosed a via middle process for their HBM in two papers (Electronics Components & Technology Conference 2013 and VLSI Tech. Digest 2014). The TSV openings are formed after the tungsten contacts to the gates and source/drain regions are made, using a Bosch TSV etch. An oxide liner is then deposited along the via sidewalls, lined with a Ta-based barrier and Cu seed layers, and filled with electroplated Cu. A thermal anneal process is used as a Cu stress relief. A CMP and etch process is used to thin the backsides of the DRAM wafer and expose the Cu TSVs. The backsides of the DRAM wafers are then passivated with oxide, followed by the formation of the backside micro bumps."


AMD Radeon Fury X (Source: TechInsights)


Some facts from the reports:

  • The GPU die has four Hynix HBM memory modules arranged around its perimeter. 
  • Both the GPU and the HBM modules are flip-chip bumped to a UMC fabbed interposer. 
  • The interposer is, in turn, bumped to a laminate substrate. 
  • The GPU itself is a massive measuring in at 23mm by 27mm large, and is believed to be fabricated using TSMC’s 28nm HKMG process.


"The GPU die is seen in the center of the module with four Hynix HBM memory modules arranged around its perimeter. Both the GPU and the HBM modules are flip-chip bumped to a UMC fabbed interposer. This interposer is, in turn, bumped to a laminate substrate. The GPU is massive measuring in at 23mm by 27mm large, and is believed to be fabricated using TSMC’s 28nm HKMG process." (EE Times, TechInsight)




Schematic cross section of HBM module. (Source: AMD HBM brochure, TechInsights)




Hynix HBM memory (Source: Package Analysis of the SK-Hynix HBM, TechInsights)




Friday, June 12, 2015

Samsung and SNU identifies the next Super High-k

Here is another publication from Samsung on high-k screening in collaboration with Academia. This time in collaboration with researchers from the home base at Seoul National University. This is somehow a new behavior of Samsung who actually withdrew talks in front of ALD 2012 in Dresden on anything realting to high-k and DRAM development and I have not seen that much publishing from Samsung since then on these topics. Calculated results do usually not tend to interest me but this one is very, very interesting and I think it will take me some time to go there it - fully understand I will not.



"Except for c-BeO, we could not find any outstanding high-κ dielectrics with eitherEg or κ larger than those of the HfO2 thin films currently used in CPU or DRAM (Eg~6.0 eV and κ~20–25; see t-HfO2)"


Cubic BeO will probably be a hot ALD topic for the rest of 2015 and I do wonder if Prof. Wang will mention BeO in Portland at the AVS ALD 2015 in Portland when he gives his invited talk: 

Cheol Seong Hwang, Seoul National University
“Capacitor Dielectric and Electrodes for DRAM with sub-20 nm Design Rule”

Check out the paper - it is Open Access - thank you Samsung!

Novel high-κ dielectrics for next-generation electronic devices screened by automated ab initio calculations (Open Access)

Kanghoon Yim, Youn Yong, Joohee Lee, Kyuhyun Lee, Ho-Hyun Nahm, Jiho Yoo, Chanhee Lee, Cheol Seong Hwang and Seungwu Han

NPG Asia Materials (2015) 7, e190; doi:10.1038/am.2015.57
Published online 12 June 2015



The experimental band gap and dielectric constant for well-known oxides. The property region ideal for dielectrics is also shown.


Abstract:
As the scale of transistors and capacitors in electronics is reduced to less than a few nanometers, leakage currents pose a serious problem to the device’s reliability. To overcome this dilemma, high-κ materials that exhibit a larger permittivity and band gap are introduced as gate dielectrics to enhance both the capacitance and block leakage simultaneously. Currently, HfO2 is widely used as a high-κ dielectric; however, a higher-κ material remains desired for further enhancement. To find new high-κ materials, we conduct a high-throughput ab initiocalculation for band gap and permittivity. The accurate and efficient calculation is enabled by newly developed automation codes that fully automate a series of delicate methods in a highly optimized manner. We can, thus, calculate >1800 structures of binary and ternary oxides from the Inorganic Crystal Structure Database and obtain a total property map. We confirm that the inverse correlation relationship between the band gap and permittivity is roughly valid for most oxides. However, new candidate materials exhibit interesting properties, such as large permittivity, despite their large band gaps. Analyzing these materials, we discuss the origin of large κ values and suggest design rules to find new high-κ materials that have not yet been discovered.



Eg vs κ plot for computed structures for 1158 oxides. Each point is color coded according to the figure of merit (Eg·κ). The candidate oxides that have not yet been tested are indicated by the chemical formula. The rough boundary of material properties that are adequate for each device type is marked by dashed lines. CPU, central processing unit.

Worth to mention also in this context is that Han Jin Lim from Samsung Semiconductor R&D Center will give a tutorial at the AVS ALD2015 conference at the end of June in Portland.

Han Jin Lim, Samsung Electronics, “ALD Technologies and Applications in Semiconductor Device Fabrication”


Abstract:
As semiconductor devices of both memory and logic have been smaller than 20nm feature size and beyond, it is most important to acquire the conformal high-quality thin films that effect on the electrical performance enhancement in the three dimensional patterned scheme. ALD technology has been required in such critical steps as transistor and capacitor and also increased its applications including DPT (double patterning technology).

This talk consists of two parts. The first part covers the ALD in general. Those introduce the general ALD technologies including processes, precursors, reactants and equipment. The second part deals with its applications in semiconductor device fabrication. Major applications include oxide for transistor gate and DPT pattrening, nitide for transistor spacer, high-k dielectrics for transistor as well as capacitor, and metal electrode.

Thursday, June 11, 2015

Samsung, NaMLab and KU Leuven present novel DRAM capacitor stack

There was a long time since I came across a publication on materials screening for the DRAM capacitor stack. That is why it is especially interesting to read of the joint work by NaMLab in Dresden , K.U. Leuven and Samsung. The team was able to enhance the properties of the high-k stack by replacing the Al2O3 interlayer with SrO to increase the overall k-value of the capacitor dielectric without degrading the barrier and leakage properties of the dielectric stack.



Introduction: For many years, the dynamic random access memory (DRAM) was the scaling driver in semiconductor industry. Continuous downscaling of the cell dimension led to the introduction of high-k materials in a three-dimensional cylindrical capacitor geometry with metal electrodes. Currently, the most common DRAM capacitor consists of a ZrO2/Al2O3/ZrO2 (ZAZ) stack. Intensive research is done on strontium titanate (STO) and Al doped TiO2 based capacitors, but here, the thickness scaling of the dielectric is difficult to reach due to the low band gap value of the TiO2 based dielectrics. Accordingly, additional research is necessary to scale the current ZrO2 based material stack.

Ultra-thin ZrO2/SrO/ZrO2 insulating stacks for future dynamic random access memory capacitor applications


Steve Knebel, Milan Pešić, Kyuho Cho, Jaewan Chang, Hanjin Lim, Nadiia Kolomiiets, Valeri V. Afanas'ev, Uwe Muehle, Uwe Schroeder and Thomas Mikolajick

J. Appl. Phys. 117, 224102 (2015); http://dx.doi.org/10.1063/1.4922349




(a) TEM micrograph of a ZAZ MIM film stack. The stack thickness is 10 nm. A distinct Al2O3 layer is visible in the center of the ZrO2 layer. ZrO2 grains stop growing at the Al2O3 interlayer. (b) TEM micrograph of a ZSrZ MIM film stack. Stack thickness is 5 nm. No distinct SrO layer is visible and the ZrO2 crystals are growing through the whole ZrO2 layer. (c) EDX line scan of the ZAZ film: a small Al peak can be seen in the center of the ZrO2 layer. (Inset) Zoom of the EDX line scan showing the Al peak and the background signal, which proves the position of the Al2O3 layer.
Citation: J. Appl. Phys. 117, 224102 (2015); http://dx.doi.org/10.1063/1.4922349


Aiming for improvement of the ZrO2-based insulator properties as compared to the state-of-the-art ZrO2/Al2O3/ZrO2 stacks beyond 20 nm dynamic random access memory (DRAM) technology applications, ultra-thin (5 nm) ZrO2/SrO/ZrO2 stacks with TiN electrodes deposited by physical vapor deposition are addressed. By replacing the Al2O3 interlayer with SrO, the effective dielectricpermittivity of the stack can be increased as indicated by electrical analysis. At the same time, no degradation of the insulating properties of the SrO-containing stacks and minor changes in the reliability, compared to an Al2O3 interlayer, are found. These results are indicating the possibility of further reducing the effective oxide thickness of the ZrO2-based stacks to come close to 0.5 nm for future DRAM capacitors.

Sunday, May 17, 2015

2016 will be another growth year for OEM stocks and Atomic Layer Processing

2016 will be another growth year for OEM stocks and Atomic Layer Processing. In a report recently published by JP Morgan, analysts predicted another growth year in 2016 for Semiconductors stocks, driven by technology transitions in memory and 10nm FinFET. So this is good news for all Tier 1 OEMs with a number of ALD and ALE technologies in the game.

Technology transitions by memory companies :
  • continued 3D NAND ramps
  • additional 20nm conversions
  • initial 1Xnm DRAM deployments
Foundry and logic companies :
  • deploying FinFET technologies (especially 10nm FinFET) 
  • multi-patterning steps and vertical transistors
"In general, we see capital intensity increasing by 10-15% on a per wafer basis when transitioning from 14nm/16nm FinFET to 10nm FF and by 15+% when transitioning to 20nm and below DRAM / 3D NAND. The number of critical patterning layers is increasing dramatically – in the foundry/logic segment, the number of critical layers is increasing by over 3x going from 28 nm node to the 10nm node…a significant increase," the analysts added.
Read more: http://www.benzinga.com/analyst-ratings/analyst-color/15/05/5488523/jp-morgan-sees-another-growth-year-for-semiconductors-th#ixzz3aNRgk5q0

Below is an overview of some of the ALD and ALE technologies offered by the leading OEMs. It is ion sense complete yet so please let me know what is missing (jonas.sundqvist@baldengineering.com).

LAM Research



LAM Research reported in 2014 that "The latest in Lam's market-leading tungsten deposition product line, the ALTUS Max ICEFill system controls variability by providing void-free fill of the geometrically complex 3D NAND wordlines. Using a proprietary filling technique, the new system creates the tungsten wordlines with an inside-out atomic layer deposition (ALD) process. The ICEFill process completely fills the lateral (horizontal) lines without any voids, while at the same time minimizing deposition in the vertical channel area. As a result, both electrical performance and yield are enhanced."


Lam’s ALTUS systems combine CVD and ALD technologies to deposit the highly conformal films needed for advanced tungsten metallization applications (http://www.lamresearch.com/products/deposition-products).

Lam's new ALE capability on the 2300 Kiyo F Series conductor etch system provides both the productivity and technology needed. The product leverages fast gas switching and advanced plasma techniques in the reactor to boost throughput, while dynamic RF bias enables the directional etching required to remove material in high aspect ratio (deep and narrow) features. As the latest offering in Lam's market-leading Kiyo family, the 2300 Kiyo F Series system continues to provide superior uniformity and repeatability enabled by a symmetrical chamber design, advanced electrostatic chuck technology, and independent process tuning features.


  • Shallow trench isolation
  • Source/drain engineering
  • High-k/metal gate
  • FinFET and tri-gate
  • Double and quadruple patterning
  • 3D NAND

To learn how atomic layer deposition (ALD) and atomic layer etch (ALE) processes work, watch this video from LAM Research (www.youtube.com).

Applied Materials

CENTURA® ISPRINT™ TUNGSTEN ALD/CVD - The Applied Centura iSprint Tungsten ALD/CVD system provides complete contact/via fill for structures with aspect ratios ranging from 4:1 to 7:1 and extends the capability of tungsten technology to 20nm/16nm for logic and memory applications.


The iSprint system also delivers high throughput and low cost of consumables with an optimized ALD chamber design featuring a proprietary rapid gas delivery system and small chamber volume that enable fast, effective gas purging that uses less gas (www.appliedmaterials.com).

CENTURA® INTEGRATED GATE STACKThe system consists of an ALD HfO2 (hafnium oxide) deposition chamber and specialized chambers for interface layer oxide formation, post high-k nitridation, and post-nitridation anneal


The Centura Integrated Gate Stack system with ALD high-k chamber technology for 22nm and below uses Applied’s production-proven Centura Gate Stack platform to deliver the complete high-k process sequence in a controlled high vacuum environment without an “air break” (www.appliedmaterials.com).


Steven Hung, Ph.D. who specializes in integrating ALD into the transistor manufacturing process, dives deep into the chip to show what tomorrow's transistors look like, how they work, and how Applied can help the industry meet the challenges of fabricating these ultra-tiny structures to make faster, more power-efficient microchips 
(www.youtube.com).

Tokyo Electron

Tokyo electron has a number of ALD technologies and are very strong in batch processing that is used to large extent in DRAM production to get the cost per wafer down since DRAM is a commodity product.
  • TEL Formula - Mini batch, thermal processes including ALD for High-k, SiO2, SiN.
  • TEL INDY Plus - Large batch, thermal processes including ALD for High-k, SiO2, SiN.
  • TEL INDY IRad - Large batch, PEALD for ultra low temperature SiO2 and SiN.
  • TEL NT333 - Single wafer cluster tool for high t-put SiO2.

TEL INDY Large batch furnace for thermal processing and ALD (www.tel.com)


The NT333 applies inherent ALD concepts against conventional ALD processing to address the critical performance needs imposed by aggressive geometries. The NT333 can effectively deposit with a very tight thickness control, a range of less than 1A, while maintaining a productivity of 100+ wafers per hour. With a very unique reactor design, each of the ALD duty cycles enables the NT333 to deliver the high film quality which is typically compromised at low temperature regimes (<400C). (www.tel.com)

ASM International

ASM's ALD technologies, includes thermal ALD (Pulsar) for FinFET high-k metal gate stacks, and various applications of Plasma Enhanced ALD (Emerald) as an enabler for low temperature processing such as multiple patterning on resist and deposition of doped silicon oxide for solid state doping of FinFETs.


ASM’s Pulsar uses ALD to deposit the high-k dielectric materials required for advanced CMOS transistor gates ​and other applications. Pulsar is the benchmark ALD high-k tool for the industry. It was the first ALD system to be used for high-volume production at advanced customers for high-k metal gate transistors (www.asm.com).


EmerALD XP is a process module designed to deposit thin conformal metal and dielectric ​layers by atomic layer deposition (ALD) used for advanced CMOS gate stacks and other applications (www.asm.com).


​​​Eagle XP8 is a high productivity 300mm tool for PEALD applications. The Eagle XP8 PEALD system can be configured with up to four Dual Chamber Modules (DCM), enabling eight chambers in high volume production within a very compact footprint (www.asm.com).


ASM Chip Making Process (www.youtube.com)





Friday, May 16, 2014

ALE - Atomic Layer Etch emerges for 3D NAND, sub-20nm DRAMs and FinFETs

Atomic Layer Etch Finally Emerges - is a interesting blog post by Mark LaPedus (Executive Editor for manufacturing at Semiconductor Engineering) that you should really read if you want some insight into why we need ALE and why it has been difficult to develope this etch technique.
 
After nearly two decades of being confined to R&D labs, equipment makers are placing big bets on this next-gen plasma etch technology.
 
[...]
 
Lam’s Lill agrees that ALE will not replace RIE. “We will offer both technologies in one reactor,” Lill said. “We think they will be complementary for certain applications. But we are already seeing the transition (to ALE) in certain applications.”
 
ALE could be used for 3D NAND, sub-20nm DRAMs and finFETs, but there are still some challenges before ALE is running in the production fab. “There are still three grand challenges left,” Lill said. “One is that there are no secondary unintended reactions for ALE. For example, we don’t want extreme UV radiation in the reactor. Second, we want the unit steps to be discrete. And finally, we need self-limiting single unit steps. They are very difficult to find.”
 
Read more here and additional comments from experts from LAM Research, Applied Materials and Sematech : http://semiengineering.com/atomic-layer-etch-finally-emerges/ 

 
Illustration of the process steps in a plasma-enhanced ALE cycle for a silicon film etched by chlorine and argon. (Source Electroiq)
 
[please note that we used to know ALE as Atomic Layer Epitaxy until ALD - Atomic Layer Deposition took over]

Saturday, March 22, 2014

Samsung: A modified double patterning using ALD allows for continued scaling of DRAM for 10nm class technology

Samsung reports that they are  now mass producing industry’s most advanced 4Gb DDR3, using 20 nanometer process technology:

"Samsung has pushed the envelope of DRAM scaling, while utilizing currently available immersion ArF lithography, in its roll-out of the industry’s most advanced 20-nanometer (nm) 4-gigabit (Gb) DDR3 DRAM."



"With DRAM memory, where each cell consists of a capacitor and a transistor linked to one another, scaling is more difficult than with NAND Flash memory in which a cell only needs a transistor. To continue scaling for more advanced DRAM, Samsung refined its design and manufacturing technologies and came up with a modified double patterning and atomic layer deposition."

"Samsung’s modified double patterning technology marks a new milestone, by enabling 20nm DDR3 production using current photolithography equipment and establishing the core technology for the next generation of 10nm-class DRAM production. Samsung also successfully created ultrathin dielectric layers of cell capacitors with an unprecedented uniformity, which has resulted in higher cell performance."

Here is a folow up blog post from the Samsung Blog: So…About Samsung Mass Producing the Most Advanced 20nm DDR3 DRAM explaining why the dielectric layers (high-k) in the DRAM capacitor memory cell need to be a ‘ultrathin dielectric layer’ for the 20nm DDR3 DRAM compared to the 25 nm cell.

"Why are the 20nm DDR3 DRAM’s dielectric layers ultrathin rather than ultra-thick? Because the thicker the dielectric layers are, the fewer electrical charges are stored in the cell’s transistors; there is simply less room for them. Then how is it that Samsung 20nm DDR3 DRAM’s ultrathin layers are effective?

The material used in the 20nm DDR3 DRAM is measured in Angstrom (Å), a unit of length equal to 10−10 m, basically the size of an atom. The ultrathin dielectric layers of Samsung are composed of atomic materials, aka atomic layer deposition. This is why the amount of electric charges stored in the capacitor of the 20nm DDR DRAM doesn’t change much, in a significantly scale downed cell. Overall, the quality of the each cell of Samsung’s 20nm DDR DRAM is superior to the preceding 25nm DDR3 DRAM. Consequently, 20nm DDR3 DRAM’s superior cells enable high-speed operation, which is the most important characteristic of a DRAM, and low power consumption. Making the dielectric layers of the 20nm capacitor much denser and thinner than the 25nm capacitor was one of the keys to the successful development and now mass producing Samsung’s new 20nm 4G DDR3."

From a Chipworks report abstract that can be bought here, we can see a cross section of the stack capacitor array Samsung is using at 26 nm (see below). For 20 nm I have not been able to find any free available information yet.


The Samsung K4B4G0846C-BCK0 is a 4Gb DDR3 SDRAM manufactured at 26 nm, based on the half minimum pitch ("20nm generation"). The technology features capacitor-over-bitline DRAM cell arrays.

 
Wikipedia on Multiple Patterning: Multiple patterning is a class of technologies for manufacturing integrated circuits (ICs), developed for photplithography to enhance the feature density. The simplest case of multiple patterning is double patterning, where a conventional lithography process is enhanced to produce double the expected number of features. The resolution of a photoresist pattern begins to blur at around 45 nm half-pitch. For the semi conductor industry, therefore, double patterning was introduced for the 32 nm half-pitch node and below, mainly using state-of-the-art 193 nm immersion lithography tools.
 
 
A basic example of a double patterning techniques using Spacer mask: first pattern; deposition by e.g. SiO2 ALD or PEALD; spacer formation by etching; first pattern removal; etching with spacer mask;  final pattern [Source Wikipedia]
 

There are many types of double patterning and when used in combination it iscalled  multiple patterning. Those are:
  • Dual-tone photoresist
  • Dual-Tone Development
  • Self-aligned spacer
  • Double/Multiple exposure
  • Double Expose, Double Etch (mesas)
  • Double Expose, Double Etch (trenches)
  • Directed self-assembly (DSA)
Please see Wikipedia on more information on each type.