Saturday, January 6, 2018

New ALD High-k / 2D MoS2 light-erasable memory suitable for large area manufacturing technology

Phys.Org reports that researchers at the Institute of Microelectronics Chinese Academy of Sciences (IMECAS), and Fudan University have used 2D MoS2 to design a new light-erasable memory.

According to the article in Applied Physics Letter, the memory stack is based on an high-k dielectric stack (Al2O3/HfO2/Al2O3) and an atomically thin MoS2 channel, where he HfO2 act as the charge trapping layer. The holes in the HfO2 charge-trapping layer will tunnel to the MoS2 channel through the 4 nm Al2O3 tunnel layer. 
 
 
Schematic band diagrams of the MoS2/Al2O3/HfO2/Al2O3/Gate structure at (a) flat-band condition, (b) programming operation, and (c) erasing operation. (Supplementary information, Applied Physics Letters. DOI: 10.1063/1.5000552)

"In general, system-on-panel (SOP) describes a new display technology in which both active and passive components are integrated in one panel package, typically on the same glass substrate (sometimes system-on-panel is also named system-on-glass)," coauthor Hao Zhu at Fudan University told Phys.org. "This is different from traditional display technologies such as cathode ray tube (CRT) displays. One major characteristic of SOP is the application of thin-film technology, such as low-temperature poly-silicon (LTPS) thin-film transistor (TFT) arrays on the glass substrate. However, silicon-based thin-film transistors are being replaced by TFTs with new materials with improved properties. The indium gallium zinc oxide (IGZO) or zinc tin oxide (ZTO) thin film mentioned in our paper is also a good example. [Phys.org]

"Currently, we are working on the large-scale integration of such light-erasable 2-D memory devices using programmable light pulses with controllable wavelength and pulse duration," he said. "We are using new material synthesis methods such as atomic layer deposition to grow large-area MoS2 and other 2-D ultra-thin films for circuit-level applications." 
[Phys.org]

The future prospects for large scale manufacturing are there. Except for the MoS2 channel, both Al2O3 and HfO2 are standard ALD processing technologies since more than 10 years in the semiconductor industry and recent developments for flexible OLED Display manufacturing  has made the ALD technology also available for large panel processing and roll to roll technology is just looking for an excuse high volume manufacturing.
 
Article: Long-Fei He et al. "Light-erasable embedded charge-trapping memory based on MoS2 for system-on-panel applications." Applied Physics Letters. DOI: 10.1063/1.5000552

Full story: LINK

Lam Research and Tokyo Electron took market shares in 2017

Currently the fabs are running hot and expanding and 2018 is expected to continue to grow according to OEMs and market research companies like o VLSI Research (CEO Dan Hutcheson, see below). Solid State Technology reports, based on recent market research by The Information Network (LINK) that Market leader Applied Materials lost market shares in 2017 to the main competitor Tokyo Electron and Lam Research.

"Applied Materials 1.3 share points, dropping from 28.2% in 2016 to 26.9% YTD (year to date). Gaining share are Tokyo Electron Ltd. (TEL), which gained 2.4 share points while rising from 17.0% in 2016 to 19.4% in 2017 YTD. Lam Research gained 1.6 share points and growing from a 19.0% share in 2016 to a 20.6% share in 2017 YTD."


The three companies compete in the following areas with huge growth due to the memory boom in 2017 (3DNAND and DRAM):

  • conductor and dielectric etch equipment
  • deposition equipment - single/multiwafer ALD and CVD
CVD equipment share is roughly 3X that of ALD and ALD passed PVD in 2015 (according to VLSI Research). Furnace ALD and CVD is dominated by Tokyo Electron and Kokusai, however it is a smaller segment as compared to single and multi wafer ALD and CVD. ASMI, the leader in ALD single wafer equipment does not seem to have been able to grow with memory, down from 2.0% to 1.7%.

Please find the full article here: LINK

 


Friday, January 5, 2018

Memory chips led the way in 2017 boosting a 22% record semiconductor growth in revenue

Memory chips (DRAM & FLASH) led the way in 2017 boosting a 22% record semiconductor growth in revenue. Samsung Electronics became the number 1 in overall semiconductor sales for the first time, displacing Intel, which had held the top spot in sales every year since 1992. 



EE Times reports : Semiconductor sales grew by 22 percent to reach a record $419.7 billion — with memory chips leading the way — according to a preliminary estimate by market research firm Gartner.

Gartner (Stamford, Conn.) estimates that increased sales of memory chips due to shortages of NAND flash and DRAM accounted for about two-thirds of overall chip market growth in 2017. Memory also become the single largest semiconductor products category last year, according to the firm.

Full story: LINK


Gartener 2016 to 2017 revenue change for Top 10 Semiconductor companies [replotted]

Thursday, January 4, 2018

Call for Abstracts - AVS 18th International Conference on Atomic Layer Deposition (ALD 2018)


The  AVS 18th International Conference on Atomic Layer Deposition (ALD 2018)  featuring the  5th International Atomic Layer Etching Workshop (ALE 2018)  will be a three-day meeting dedicated to the science and technology of atomic layer controlled deposition of thin films and now topics related to atomic layer etching. The conference will take place Sunday, July 29-Wednesday, August 1, 2018 , at the Songdo Convensia in Incheon, South Korea.

As in past conferences, the meeting will be preceded (Sunday, July 29) by one day of tutorials and a welcome reception. Sessions will take place (Monday-Wednesday, July 30-August 1) along with an industry tradeshow. All presentations will be audio-recorded and provided to attendees following the conference (posters will be included as PDFs). Anticipated attendance is 600+.

Key Deadlines:
Abstract Submission Deadline: February 16, 2018
Author Acceptance Notifications: April 9, 2018
Student Award Applications Deadline: May 1, 2018
Early Registration Deadline: June 1, 2018
Hotel Reservation Deadline: June 26, 2018
JVST Special Issue Deadline: September 5, 2018

Wednesday, January 3, 2018

Picosun and Inert has made a new glovebox-ALD install at the Chemical and Technical Institute in Prague

Picosun and Inert has made a new glovebox-ALD install at the Chemical and Technical Institute, Prague. The Inert box is integrated with a R-200 tool for Atomic Layer Deposition of platinum and metal oxides.

Check out the details below!

 

Cornell University fabricate cell-sized origami robots by an ALD & graphene nanotechnology

Cornell University reports that one of their researcher teams has made a robot exoskeleton that can rapidly change its shape upon sensing chemical or thermal changes in its environment. And, they claim, these microscale machines – equipped with electronic, photonic and chemical payloads – could become a powerful platform for robotics at the size scale of biological microorganisms. Their work is outlined in “Graphene-based Bimorphs for Micron-sized, Autonomous Origami Machines,” published Jan. 2 in Proceedings of the National Academy of Sciences. Miskin is lead author; other contributors included David Muller, the Samuel B. Eckert Professor of Engineering, and doctoral students Kyle Dorsey, Baris Bircan and Yimo Han. [Graphene-based bimorphs for micron-sized, autonomous origami machines. Marc Z. Miskin et al (2018), PNAS https://doi.org/10.1073/pnas.1712889115 ]

Please check out this interview video for more amazing details - some snapshots are given below in  the form of screen dumps from vimeo [LINK]
 
 
 
The bimorph is built using atomic layer deposition of atomically thin layers (2 nm) of silicon dioxide onto aluminum over a cover slip – then wet-transferring a single atomic layer of graphene on top of the stack. The result is the thinnest bimorph ever made. [Vimeo Screen dump]
 

Processing has been taken place in Cornell University Clean room - Cornell NanoScale Facility for Science and Technology, here showing the ALD reactor and rpocessing of the SiO2 layer (Oxford Instruments, FlexAl) [Vimeo Screen dump]


The researchers can fabricate many different forms of origami shapes ranging from simple tetrahedrons to cubes and helix shaped objects [Vimeo Screen dump]
 

 
With this new amazing technology, the Cornell rersearchers are developing robotic ‘exoskeleton’ for electronics with integrated microchips. [Vimeo Screen dump]
 
 
 

Get back to work - SEMI projects continued boom in fab equipment spending for 2018

MILPITAS, Calif. ─ January 2, 2018 ─ The year-end update to the SEMI World Fab Forecast report reveals 2017 spending on fab equipment investments will reach an all-time high of $57 billion. High chip demand, strong pricing for memory, and fierce competition are driving the high-level of fab investments, with many companies investing at previously unseen levels for new fab construction and fab equipment. See figure 1.
World Fab Forecast Figure 1
Figure 1


The SEMI World Fab Forecast data shows fab equipment spending in 2017 totaling US$57 billion, an increase of 41 percent year-over-year (YoY). In 2018, spending is expected to increase 11 percent to US$63 billion.

While many companies, including Intel, Micron, Toshiba (and Western Digital), and GLOBALFOUNDRIES increased fab investments for 2017 and 2018, the strong increase reflects spending by just two companies and primarily one region.

Tuesday, January 2, 2018

Single Atomic Layer Ferroelectric on Silicon by PVD ZrO2


A team of mainly US based researchers from (Yale, MIT, Université de Genève and Globalfoundries) have been able to scale down ferroelectric ZrO2 to only one atomic layer on silicon using PVD. This record breaking thin monolayer ferroelectric allows for more aggressively scaled devices than bulk ferroelectrics as compared to the most current 5–10 nm thick layers based on e.g. Si:HfO2 and HfZrOx. 

They found that:
  • single atomic layer ZrO2 exhibits ferroelectric switching behavior when grown with an atomically abrupt interface on silicon
  • ZrO2 gate stack demonstrate that a reversible polarization of the ZrO2 interface structure couples to the carriers in the silicon.
Single Atomic Layer Ferroelectric on Silicon
Mehmet Dogan, Stéphanie Fernandez-Peña, Lior Kornblum, Yichen Jia, Divine P. Kumah, James W. Reiner, Zoran Krivokapic, Alexie M. Kolpak, Sohrab Ismail-Beigi, Charles H. Ahn, and Frederick J. Walker

Nano Lett., Article ASAP, DOI:10.1021/acs.nanolett.7b03988

Abstract: A single atomic layer of ZrO2 exhibits ferroelectric switching behavior when grown with an atomically abrupt interface on silicon. Hysteresis in capacitance–voltage measurements of a ZrO2 gate stack demonstrate that a reversible polarization of the ZrO2 interface structure couples to the carriers in the silicon. First-principles computations confirm the existence of multiple stable polarization states and the energy shift in the semiconductor electron states that result from switching between these states. This monolayer ferroelectric represents a new class of materials for achieving devices that transcend conventional complementary metal oxide semiconductor (CMOS) technology. Significantly, a single atomic layer ferroelectric allows for more aggressively scaled devices than bulk ferroelectrics, which currently need to be thicker than 5–10 nm to exhibit significant hysteretic behavior (Park, et al. Adv. Mater. 2015, 27, 1811).

Reprinted with permission from (Single Atomic Layer Ferroelectric on Silicon, M. Dogan et al, Nano Letters, Dec 2017). Copyright (2018) American Chemical Society.

High‐resolution STEM image and EDX intensity profiles of Si, Al and Zr. The Supporting Information is available free of charge on the ACS Publications website at "Single Atomic Layer Ferroelectric on Silicon" https://figshare.com/collections/Single_Atomic_Layer_Ferroelectric_on_Silicon/3961401

General Motors and Forge Nano has co-developed ALD technology for lithium batteries

According to recent news releases General Motors and Forge Nano has co-developed and been rewarded for ALD for lithium battery technology featuring:
  • ultrathin (thickness < 5nm) multifunctional hybrid coatings and processes.
  • solutions to critical issues involved with gas generation, manganese dissolution induced capacity loss and safety issue associated with polymeric separators.
  • scale-up production and commercialization of this innovation for both automotive and non-automotive applications.
  • semi-continuous ALD systems (the tall pilot-scale stack, as well as the large single-cycle stack), have the production capacity of more than 1 MT/day, making it possible to implement the advanced surface coating technologies into the next generation of lithium ion batteries.
 
Background information:

LOUISVILLE, CO - Forge Nano, Louisville, Colorado, recently won a 2017 R&D 100 Award as co-developer with General Motors for the development of the Ultrathin Multifunctional Hybrid Coatings and Processes. The R&D 100 Awards have served as an innovation awards program for the past 55 years, honoring great R&D pioneers and their revolutionary ideas in science and technology.

“Forge Nano was founded with a vision to deploy precision nano-coatings to make many other technologies safer, less expensive and more efficient. That vision is now a reality, and it is extremely gratifying to be honored by the R&D 100 Awards for introducing one of 2017’s most innovative and influential technology solutions,” said Forge Nano Founder and CEO Dr. Paul Lichty, who accepted the award at the R&D 100 Conference in Orlando, Florida.

Forge Nano launched in 2013 with breakthrough technology that makes nano-coatings fast, affordable and scalable in manufacturing. The company specializes in nano-coatings and atomic film deposition, serving functions from corrosion resistance to electrical insulation or conduction. As demands for next-generation materials become more and more extreme, nano-engineered surface coatings can fulfill the need for enhanced properties and precise characteristics.


The R&D 100 Award - Ultrathin multifunctional hybrid coatings and processes (LINK)

The majority of battery failure initiates from active material surfaces in the electrodes. Surface coatings, as an effective mitigating strategy, have been widely applied into battery material manufacturing process to protect active materials. Conventional coating technologies, such as chemical vapor deposition, physical vapor deposition and wet chemistry, typically generate non-uniform coating particularly on nano-sized particles. The thickness control becomes difficult, and the thicker coating typically induce high much impedance. To tackle this challenge, General Motors—a pioneer in applying surface coating using the Atomic Layer Deposition (ALD) technique—has developed several Ultrathin multifunctional hybrid coatings and processes. These ultrathin (thickness < 5nm) multifunctional coatings solve critical issues involved with gas generation, manganese dissolution induced capacity loss and safety issue associated with polymeric separators. Forge Nano has developed the technologies that enable scale-up production and commercialization of this innovation for both automotive and non-automotive applications. Their semi-continuous ALD systems (the tall pilot-scale stack, as well as the large single-cycle stack), have the production capacity of more than 1 MT/day, making it possible to implement the advanced surface coating technologies into the next generation of lithium ion batteries.

Monday, January 1, 2018

HHV launch ALD System based on technology transferred from IIT Bombay

Hind High Vacuum Co. Pvt. Ltd. (HHV), a vacuum science and technology company with major clients like HAL, ISRO, BARC, Titan etc, announced the launch of its first indigenously developed Atomic Layer Deposition (ALD) System based on technology transferred from IIT Bombay. This tool was developed entirely by HHV’s Thin Film Technology Division out of its Bengaluru facility as a part of the company’s on-going ‘Make in India’ initiative.


A picture of the ALD 150 system, which seems to be a top loaded tool very similar in layout to e.g. a CNT Savannah. Judging by the name this is a 150 mm system (picture from HHV webpage)

Full story: HHV develops Atomic Layer Deposition System based on technology transferred from IIT Bombay

Press release: LINK

Link to HHV ALD product page: LINK

Encapsulation of homogeneous catalysts in mesoporous materials by diffusion limited ALD

Researches from the Chinese Academy of Sciences demonstrate ALD encapsulation of metal complexes into nanochannels of mesoporous materials is. The pore size of the hollow plug is precisely controlled on the sub-nanometer scale by the number of ALD cycles to fit various metal complexes with different molecular sizes. They claim that this ALD-assisted encapsulation method can be extended to the encapsulation of other homogeneous catalysts into different mesoporous materials for various heterogeneous reactions. Please find the paper below!
Beautiful TEM analysis of carbon nanofibers that have beencoated with 400 cycles TiO2 (supporting information, LINK)
Reference: Zhang, S., Zhang, B., Liang, H., Liu, Y., Qiao, Y. and Qin, Y. (2017), Encapsulation of Homogeneous Catalysts in Mesoporous Materials Using Diffusion-Limited Atomic Layer Deposition. Angew. Chem. Int. Ed.. doi: 10.1002/anie.201712010

Picture from Tweet above

Purdue University demonstrate negative capacitance MoS2 transistors using ferroelectric HfZrOx

WEST LAFAYETTE, Ind. –  Researchers have experimentally demonstrated how to harness a property called negative capacitance for a new type of transistor that could reduce power consumption, validating a theory proposed in 2008 by a team at Purdue University.

The researchers used an extremely thin, or 2-D, layer of the semiconductor molybdenum disulfide to make a channel adjacent to a critical part of transistors called the gate. Then they used a “ferroelectric material” called hafnium zirconium oxide to create a key component in the newly designed gate called a negative capacitor.

A new type of transistor (a) harnesses a property called negative capacitance. The device structure is shown with a transmission electron microscopy image (b) and in a detailed “energy dispersive X-ray spectrometry” mapping (c). (Purdue University photo/Mengwei Si)

Capacitance, or the storage of electrical charge, normally has a positive value. However, using the ferroelectric material in a transistor’s gate allows for negative capacitance, which could result in far lower power consumption to operate a transistor. Such an innovation could bring more efficient devices that run longer on a battery charge.

Aveni extends copper interconnects to 5nm and below for BEOL integration employing ALD TaN & CVD Co barrier/seed

Recently at IEDM 2017 IBM announced that copper is here to stay and can continue to be scaled for the future back end of line (BEOL) interconnects - 20 Years of Cu BEOL in Manufacturing, and its Future Prospects (Invited), D. Edelstein, IBM TJ Watson Research Center (LINK)

Before the actual copper plating process, the advanced dual-damascene structures for interconnects employ two very important conformal deposition processes :
  • an atomic layer deposition tantalum nitride (ALD TaN) copper diffusion barrier
  • a thin chemical vapor deposition cobalt (CVD Co) liner
More detailed information on Cobalt CVD for barrier/seed and selective encapsulation of copper from the leader Applied Materials can be found here (LINK).

According to a press release below (LINK), Aveni has announced it has obtained results that support the continued use of copper in the BEOL for advanced interconnects, at and beyond the 5nm technology node. Aveni is a French developer and manufacturer of wet deposition technologies and chemistries for 2D interconnects and 3D through silicon via packaging. The company was originally founded in 2001 as a spinoff from the Commissariat à l’énergie atomique et aux énergies alternatives (CEA) to develop and market groundbreaking nanometric deposition technologies for a variety of electronic applications.  

MASSY, France – Dec. 12, 2017 – aveni S.A., developer and manufacturer of market-disrupting wet deposition technologies and chemistries for 2D interconnects and 3D through silicon via packaging, today announced it has obtained results that strongly support the continued use of copper in the back end of line (BEOL) for advanced interconnects, at and beyond the 5nm technology node.