Ultratech Cambridge NanoTech announced that the 1000th paper using one of their ALD tools

I previously posted this paper (here) and it turns out that this is as announced today by Ultratech Cambridge NanoTech, the 1000th peer-reviewed paper written on its ALD systems was published in July 2015 inChemistry of Materials. 

The paper entitled "Atomic Layer Deposition of the Solid Electrolyte LiPON" was authored by Alexander Kozen, Ph.D, a member of the Nanostructures for Electrical Energy Storage (NEES) group at the University of Maryland. This milestone figure underscores the fact that today, almost one-fifth of the total peer-reviewed ALD publications worldwide, since the founding of the company in 2003, have been written based on using Ultratech-CNT systems (based on Web of Science analysis). 

University of Maryland Professor and principal investigator at the Energy Frontier Research Center (EFRC) Gary Rubloff said, "The performance and flexibility of our Ultratech Fiji systems have driven our group's nano research since 2011. The role played by these systems has been critical in many of the advances made in Nanostructures for Electrical Energy Storage (NEES)--our DOE, Energy Frontier Research Center. The research undertaken has involved a variety of collaborations across the Center to exploit ALD films as cathode, anode, current collector, solid electrolyte, and passivation/stabilization layers distributed as highly conformal, high quality layers on 3-D structures in the most demanding nano-geometries. As part of our most recent work, we have just developed the first reported ALD process for lithium phosphorous oxy-nitride (LiPON), a well-known, solid-state electrolyte for safe batteries. Through the use of real-time, in-situ ellipsometry, the process was optimized in a systematic fashion. ALD allows us to grow very thin LiPON layers that we are applying to passivation of high-energy lithium anodes as well as to solid-state batteries."

Ultratech-CNT Vice President of Research and Engineering Ganesh Sundaram, Ph.D. said, "While the traditional gauge of system productivity has focused on metrics such as wafer output, we have chosen to concentrate on creating products which motivate and enable intellectual output. The 1000th paper milestone attests to the fact that the Ultratech-CNT ALD systems are at the forefront for generating high quality, and strongly-cited research in this fast growing field. Furthermore, the large library of research papers based on our systems also provides substantial benefits to new researchers entering the field as they will be able to take advantage of the solid foundation of published research that underpins these ALD systems."

Dr. Kozen is part of The Rubloff Group at the University of Maryland where Professor Gary Rubloff heads the Nanostructures for Electrical Energy Storage (NEES), Energy Frontier Research Center (EFRC), a program of the Department of Energy (DOE). The paper was published in Chemistry of Materials (DOI: 10.1021/acs.chemmater.5b01654).

BALD 2015 in Tartu LATE-NEWS ABSTRACT SUBMISSION FOR POSTER PRESENTATIONS.

LATE-NEWS ABSTRACT SUBMISSION FOR POSTER PRESENTATIONS.

We are pleased to announce that a limited number of late-news poster presentations  can be included into the program of the 13th International Baltic Conference on Atomic Layer Deposition. 

The abstract submission deadline is August 17, 2015.

Please find here the call for late-news abstracts.

Please use the online form below for uploading your abstract. Guidlines for formation of the abstract can be found from here. In addition to the abstract file all the graphics should be also uploaded separately via online form to ensure the good print quality.

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Abstract submission rules:

• Abstract must be submitted in word and pdf format, using the guidelines that can be found from here.
• In order to ensure sufficient print quality, the figure(s) should be uploaded as separate files (TIFF for halftone images and PDF for line drawings) in addition to MS Word and PDF files of the abstract with embedded figure(s) and figure caption(s). File size 300-700KB.
• One Abstract can include up to two pictures or graphics.
• Up to two poster presentations per Full Registration can be accepted.
• One Presentation per Student Registration can be accepted.

Rice U. discovery may boost ReRAM memory technology

My favorite high-k metal oxide Ta2O5 is used again for a resistive RAM memory - this time with my least favorite material - Grrrraphene. Just can´t stand the hype I guess. Anyhow considering recent developments in cross bar Memory cell technology by Intel and Micron this could prove to be a future prospect.

A schematic shows the layered structure of tantalum oxide, multilayer graphene and platinum used for a new type of memory developed at Rice University. The memory device overcomes crosstalk problems that cause read errors in other devices. 

(Tour Group/Rice University)

PUBLIC RELEASE: 10-AUG-2015Rice U. discovery may boost memory technology

Rice University scientists make tantalum oxide practical for high-density devices

Scientists at Rice University have created a solid-state memory technology that allows for high-density storage with a minimum incidence of computer errors.

The memories are based on tantalum oxide, a common insulator in electronics. Applying voltage to a 250-nanometer-thick sandwich of graphene, tantalum, nanoporous tantalum oxide and platinum creates addressable bits where the layers meet. Control voltages that shift oxygen ions and vacancies switch the bits between ones and zeroes.

The discovery by the Rice lab of chemist James Tour could allow for crossbar array memories that store up to 162 gigabits, much higher than other oxide-based memory systems under investigation by scientists. (Eight bits equal one byte; a 162-gigabit unit would store about 20 gigabytes of information.)

Details appear online in the American Chemical Society journal Nano Letters. More details can be found here: http://www.eurekalert.org/pub_releases/2015-08/ru-rud081015.php

Applications Engineer - ALD at Oxford Instruments’ Plasma Technology

Applications Engineer - ALD, Yatton, Bristol

 

 

Oxford Instruments’ Plasma Technology business is looking for an Applications Engineer to play a key role in the Atomic Layer Deposition (ALD) team by developing processes within design boundaries and timescales. In this role you will process and demonstrate customer samples, liaise with customers, support system acceptances and provide customer training both in the UK and overseas. Ideally you will have a background in chemistry and experience of the semiconductor industry, and/or chemical engineering experience.

The Role

Key responsibilities of the role will include (but not be limited to):

• To push the performance boundaries of existing technology to process and demonstrate samples. 
• To contribute to the process development for the ALD project. Liaise with all members of the project team and interpret their requirements into sample processing requirements.
• Analyse the results of the test samples and produce technical reports.
• Develop an excellent working knowledge of the technology to facilitate fault finding and root cause analysis on processing results or equipment performance.
• Carry out customer training both at Plasma Technology and at customer sites.

The Person

A relevant science or engineering degree. Chemistry or Chemical engineering would be an advantage. Ideally, experience of the semiconductor industry and/or chemical engineering experience. Exposure to atomic layer deposition or reactive ion/high density plasma etching processes an advantage.

• Nanotechnology measuring skills (e.g. SEMS, Nanospecs, Ellipsometry).
• MOCVD (metal organic chemical vapour deposition).
• PECVD (plasma enhanced chemical vapour deposition).
• ALD (atomic layer deposition).
• Self-starting, diligent and enthusiastic. A professional approach to working independently and managing your own time.
• Highly innovative and good lateral thinking skills.
• Focused on excellent customer service.
• Good diagnostic skills and problem solving abilities. Positive and enthusiastic attitude to technical challenges, and flexibility to cope effectively with changes to specifications or priorities.
• Excellent written and oral communication. Able to articulate, present and report on technical or complex issues clearly and succinctly.

Business Overview

Oxford Instruments Plasma Technology provides a range of high performance, flexible tools to semiconductor processing customers involved in research and development, and production. Oxford Instruments plc is a global company with manufacturing facilities, offices and service centres, worldwide.

To apply, please submit your CV to caroline.read@oxinst.com

www.oxford-instruments.com/businesses/nanotechnology/plasma-technology

Follow us at www.twitter.com/oxinst or www.facebook.com/oxinst

Note to recruitment agencies: Oxford Instruments does not accept agency CV’s. Please do not forward details to our jobs alias, Oxford Instruments employees or any other company location. Oxford Instruments is not responsible for any fees related to unsolicited CV’s

Ferroelectric HfO2 by ALD Key Breakthrough in ITRS “Beyond CMOS” Update 2015

Following the ITRS Summer Meeting, Palo Alto, CA, July 11-12, 2015 Ferroelectric HfO2 by Fraunofer CNT and NaMLab in Dresden Germany is showcased as a "Key Breakthrough" in the ITRS “Beyond CMOS” Update 2015. You can find this presentation in by ITRS Emerging Research Devices (ERD) amongst others in the excellent new ITRS 2.0 website : http://www.itrs2.net/

ALD listed as Top 10 Advanced Manufacturing and Automation Technologies

Research and Markets has announced the addition of the "2015 Top Technologies in Advanced Manufacturing and Automation" report to their offering and Atomic layer Deposition is up in the Top 10 among technologies like Advanced Lithography, Agile Robots and Magnetic Leviatation(!)

Top 10 Advanced Manufacturing and Automation Technologies - Deep Dive Analysis

1. 3D Printing
2. Multimaterial Joining Technologies
3. Composites Manufacturing
4. Atomic Layer Deposition
5. Nanomanufacturing
6. Digital Manufacturing
7. Micromanufacturing
8. Agile Robots
9. Advanced Lithography
10. Magnetic Levitation

Peking University demonstrate a ALD modified nanochannels for protein sensing

Peking University demonstrate a new type of nanopore device based on ALD Al2O3 modified track-etched conical nanochannels for protein sensing. The conformal Al2O3 film on the conical nanochannels was performed in a homemade flow-through ALD system with TMA and H2O as the precursors at a low deposition temperature of 120 °C to prevent thermal damage to the polymer PET.

Atomic Layer Deposition Modified Track-Etched Conical Nanochannels for Protein Sensing

Ceming Wang, Qibin Fu, Xinwei Wang, Delin Kong, Qian Sheng, Yugang Wang, Qiang Chen, and Jianming Xue

Anal. Chem., Article ASAP
DOI: 10.1021/acs.analchem.5b01501

 

Nanopore-based devices have recently become popular tools to detect biomolecules at the single-molecule level. Unlike the long-chain nucleic acids, protein molecules are still quite challenging to detect, since the protein molecules are much smaller in size and usually travel too fast through the nanopore with poor signal-to-noise ratio of the induced transport signals. In this work, we demonstrate a new type of nanopore device based on atomic layer deposition (ALD) Al2O3 modified track-etched conical nanochannels for protein sensing. These devices show very promising properties of high protein (bovine serum albumin) capture rate with well time-resolved transport signals and excellent signal-to-noise ratio for the transport events. Also, a special mechanism involving transient process of ion redistribution inside the nanochannel is proposed to explain the unusual biphasic waveshapes of the current change induced by the protein transport.

Heliatek solar films awarded with World Economic Forum's Technology Pioneers

Heliatek, the Dresden-based German company that produces ultra-light, flexible and less than 1 mm thick Photovoltaic solar films, was awarded today as one of the World Economic Forum's "technology pioneers", a selection of the world's most innovative companies. Heliatek is a spin-off from the Technical University of Dresden and the University of Ulm. The company is a leader in the field of Organic Electronics Energy holding the world record efficiency of 12%. It started commercialization of its solar films in July 2014. 

 

The tandem cell: two solar cells stacked on top of each other. The active layers are only around 250 nm thick. (www.heliatek.com)

 

Heliatek was chosen by a professional jury from among hundreds of candidates as one of the 49 selected companies and was the only German company to do so. Thanks to its selection, it will have access to the most influential and sought-after business and political network in the world, and be invited to the World Economic Forum's "Summer Davos" in Dalian, China, this September, or the Annual Meeting in Davos in January.

Thibaud Le Séguillon, Heliatek CEO, remarks, "We are delighted to be recognized by The World Economic Forum as a Technology Pioneer. We have developed groundbreaking technology and manufacturing process that will have a significant impact on the way energy is produced. By integrating our solar films to building facades, we turn these into localized power stations."

 

Heliatek  hold the world record of 12% cell efficiency for opaque (non-transparent) organic solar cells. In production, they currently achieve 7-8 %. The latest development allows transparency levels up to 50% with an efficiency of 6%. The intrinsic lifespan of our small molecules is >25 years (extrapolated). (www.heliatek.com)

"We're glad to see a German company make it to the selection," says Fulvia Montresor, Head of Technology Pioneers at the World Economic Forum. "Heliatek is part of a group of entrepreneurs who are more aware of the crucial challenges of the world around them, and who are determined to do their part to solve those challenges with their company."

 

The innovative roll-to-roll production process offers many advantages: high throughput, high yield and low costs. For example only 1g of organic material is necessary for one square meter (1m²= 10.74 ft²) of active HeliaFilm®. Together with the low power consumption of the production process this leads to a uniquely short energy payback time of less than 3 months. (www.Heliatek.com)
 

The Technology Pioneers were selected from among hundreds of applicants by a selection committee of 68 academics, entrepreneurs, venture capitalists and corporate executives. Notable members of the committee include Arianna Huffington (founder, Huffington Post) and Henry Blodget (editor-in-chief, Business Insider). The committee based its decisions on criteria including innovation, potential impact, working prototype, viability and leadership.

Past recipients include Google (2001), Wikimedia (2007), Mozilla (2007), Kickstarter (2011) and Dropbox (2011). More information on past winners can be found here.

UPDATED: Maxima Sciences LLC announces the new ALD100 deposition system

Maxima Sciences LLC has announced the launch of the ALD100 deposition system. This system is designed with researchers in mind. It provides an economical solution with the flexibility needed to support multiple research projects. You can contact them at 859.474.2606 or info@max-sci.com for more information:

Korea University present wafer-scale graphene on silicon substrates

Researchers have a method to synthesize graphene at the wafer-scale. Their work, published in Applied Physics Letters, makes large-area synthesis of graphene compatible with silicon microelectronics. In the last decade, graphene has been intensively studied for its unique optical, mechanical, electrical and structural properties. The one-atom-thick carbon sheets could revolutionize the way electronic devices are manufactured and lead to faster transistors, cheaper solar cells, new types of sensors and more efficient bioelectric sensory devices. As a potential contact electrode and interconnection material, wafer-scale graphene could be an essential component in microelectronic circuits, but most graphene fabrication methods are not compatible with silicon microelectronics, thus blocking graphene's leap from potential wonder material to actual profit-maker. “For integrating graphene into advanced silicon microelectronics, large-area graphene free of wrinkles, tears and residues must be deposited on silicon wafers at low temperatures, which cannot be achieved with conventional graphene synthesis techniques as they often require high temperatures,” explained Professor Kim Jihyun of Korea University. Read more from Asian Scientist Magazine at: http://www.asianscientist.com/2015/08/tech/korea-wafer-scale-graphene-silicon-microelectronics/

 

As reported by AZONano: A team of researchers from Korea University, Seoul, has developed an easy and scalable technique for growing graphene, and have synthetically produced high-quality, multi-layer, wafer-scale graphene on silicon substrates. This latest breakthrough paves the way for using graphene in silicon microelectronics on a commercial scale. The study has been published in AIP Publishing’s journal Applied Physics Letters.

Wafer-scale (4 inch in diameter) synthesis of multi-layer graphene using high-temperature carbon ion implantation on nickel / SiO2 /silicon. CREDIT: J.Kim/Korea University, Korea

Full story: http://www.azonano.com/news.aspx?newsID=33336

Wafer-scale synthesis of multi-layer graphene by high-temperature carbon ion implantation

Janghyuk Kim, Geonyeop Lee and Jihyun Kim
Appl. Phys. Lett. 107, 033104 (2015); http://dx.doi.org/10.1063/1.4926605

Schematics of (a) E-beam evaporation of Ni on SiO2/Si substrate, (b) carbon ion implantation into Ni, (c) post-implantation activation annealing at various conditions, and (d) graphene synthesized on both sides of Ni layer. (e) Diagram of the post-implantation activation annealing conditions.
Citation: Appl. Phys. Lett. 107, 033104 (2015); http://dx.doi.org/10.1063/1.4926605

 

We report on the synthesis of wafer-scale (4 in. in diameter) high-quality multi-layer graphene using high-temperature carbon ion implantation on thin Ni films on a substrate of SiO2/Si. Carbon ions were bombarded at 20 keV and a dose of 1 × 1015 cm−2 onto the surface of the Ni/SiO2/Si substrate at a temperature of 500 °C. This was followed by high-temperature activation annealing (600–900 °C) to form a sp2-bonded honeycomb structure. The effects of post-implantation activation annealing conditions were systematically investigated by micro-Raman spectroscopy and transmission electron microscopy. Carbon ion implantation at elevated temperatures allowed a lower activation annealing temperature for fabricating large-area graphene. Our results indicate that carbon-ion implantation provides a facile and direct route for integrating graphene with Si microelectronics

Researchers have a method to synthesize graphene at the wafer-scale. Their work, published in Applied Physics Letters, makes large-area synthesis of graphene compatible with silicon microelectronics. In the last decade, graphene has been intensively studied for its unique optical, mechanical, electrical and structural properties. The one-atom-thick carbon sheets could revolutionize the way electronic devices are manufactured and lead to faster transistors, cheaper solar cells, new types of sensors and more efficient bioelectric sensory devices. As a potential contact electrode and interconnection material, wafer-scale graphene could be an essential component in microelectronic circuits, but most graphene fabrication methods are not compatible with silicon microelectronics, thus blocking graphene's leap from potential wonder material to actual profit-maker. “For integrating graphene into advanced silicon microelectronics, large-area graphene free of wrinkles, tears and residues must be deposited on silicon wafers at low temperatures, which cannot be achieved with conventional graphene synthesis techniques as they often require high temperatures,” explained Professor Kim Jihyun of Korea University. Read more from Asian Scientist Magazine at: http://www.asianscientist.com/2015/08/tech/korea-wafer-scale-graphene-silicon-microelectronics/

Nanjing Tech University stabilizes CNTs with block copolymers and add functionality by ALD

Here is a recent publication from from a lab at Nanjing Tech University stabilizes carbon nanotubes with block copolymers and add functionality by ALD TiO2.

Surface functionalization of carbon nanotubes by direct encapsulation with varying dosages of amphiphilic block copolymers

Xueping Yao et al 2015 Nanotechnology 26 325601. doi:10.1088/0957-4484/26/32/325601

Encapsulation of carbon nanotubes (CNTs) by amphiphilic block copolymers is an efficient way to stabilize CNTs in solvents. However, the appropriate dosages of copolymers and the assembled structures are difficult to predict and control because of the insufficient understanding on the encapsulation process. We encapsulate multiwalled CNTs with polystyrene-block-poly (4-vinyl pyridine) (PS-b-P4VP) by directly mixing them in acetic acid under sonication. The copolymer forms a lamellar structure along the surface of CNTs with the PS blocks anchoring on the tube wall and the P4VP blocks exposed to the outside. The encapsulated CNTs achieve good dispersibility in polar solvents over long periods. To increase our understanding of the encapsulation process we investigate the assembled structures and stability of copolymer/CNTs mixtures with changing mass ratios. Stable dispersions are obtained at high mass ratios between the copolymer and CNTs, i.e. 2 or 3, with the presence of free spherical micelles. Transmission electron microscopy and thermal gravimetric analysis determine that the threshold for the complete coverage of CNTs by the copolymer occurs at the mass ratio of 1.5. The coated copolymer layer activates the surface of CNTs, enabling further functionalization of CNTs. For instance, atomic layer deposition of TiO2 produces conformal thin layers on the encapsulated CNTs while isolated TiO2 bumps are produced on the pristine, inert CNTs.

Washington Nanofabrication Facility to invest $37 million

As reported today by University of Washington : For start-up companies looking to make chips with nanoscale features for sequencing DNA or wafers for industrial barcode printing, the equipment costs to fabricate those parts could easily devour every last dollar of seed funding.

The same goes for grant-funded researchers designing quantum information devices or micro-scale sensors to measure cell movement— which is where theWashington Nanofabrication Facility comes in.

Since the UW started operating the Washington Nanofabrication Facility in 2011, its users have included:

• 84 UW faculty
• 298 students
• 92 companies, including 7 UW spin-outs
• 36 outside academic institutions

The WNF makes things that aren’t practical, economical or possible to fabricate at commercial foundries — inconceivably tiny parts, chips made from unconventional materials that industrial factories won’t touch, devices that probe the boundaries of our universe. Part of the National Nanotechnology Infrastructure Network, the lab on the University of Washington campus is the largest publicly accessible nanofabrication facility north of Berkeley and west of Minneapolis.

To serve growing demand for nanofabrication services, the UW Board of Regents has approved spending up to $37 million to renovate the facility, which is housed in Fluke Hall. The overhaul, scheduled to begin in November, will upgrade basic building systems and roughly double the amount of highly-specialized fabrication space that academics and entrepreneurs increasingly rely on to build innovative devices.

Full story : http://www.washington.edu/news/2015/08/03/uw-to-invest-37-million-in-nanofabrication-lab-critical-to-researchers-start-ups/

Improved gate oxide quality for PEALD TiN vs PVD TiN for FDSOI CMOS

Gate dielectric quality is critical for advanced device fabrication, especially for low power, low leakage devices. In a recent study MIT shows a improved gate oxide quality for PEALD TiN vs PVD TiN. Using an Oxford Instruments OpAL system for PEALD of TiN from  tetrakis(dimethylamido)titanium (TDMAT) and an H2/N2 plasma mixture as precursors and plasma magnetron sputtered TiN films deposited at 300 °C using an Electrotech Sigma system the investigation concluded that:

• FDSOI transistors fabricated with either gate deposition process showed similar electrostatic performance.
• Gate dielectric quality metrics were significantly better when PE-ALD TiN was used compared to plasma sputtered TiN.
• A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current.
• A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PEALD source.

The study was conducted in The MIT Lincoln Laboratory Microelectronics Laboratory. The Lab has a fully depleted silicon-on-insulator (FDSOI) CMOS circuit prototyping capability.

MIT Lincoln Laboratory occupies 75 acres (20 acres of which are MIT property) on the eastern perimeter of Hanscom Air Force Base, which is at the nexus of Lexington, Bedford, Lincoln, and Concord. The MIT property and most of the Laboratory’s facilities are within the Lexington town boundaries.

Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates (OPEN ACCESS)

Christopher J. Brennan, Christopher M. Neumann and Steven A. Vitale

J. Appl. Phys. 118, 045307 (2015); http://dx.doi.org/10.1063/1.4927517

Fully depleted silicon-on-insulator transistors were fabricated using two different metal gatedeposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN.  A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.

The MIT Lincoln Laboratory Microelectronics Laboratory is a state-of-the-art semiconductor research and fabrication facility supporting a wide range of Lincoln Laboratory programs. The 70,000-square-foot facility has 8100 square feet of class-10 and 10,000 square feet of class-100 cleanroom areas. The Lab has a fully depleted silicon-on-insulator (FDSOI) CMOS circuit prototyping capability

Atomic Layer Deposition of the Solid Electrolyte LiPON for 3D solid state nanobatteries

Since its discovery in the early 1990s, LiPON (lithium phosphorus oxynitride) has been one of the most popular solid state electrolytes used for planar lithium ion microbatteries. University of Maryland demonstrate an ALD process for the solid electrolyte lithium phosphorousoxynitride (LiPON) using lithium tert-butoxide (LiOtBu), H2O, trimethylphosphate (TMP), and plasma N2 (PN2) as precursors using av Ultratech / Cambridge Naotech Fiji 200 PEALD reactor. The results are published in the Open Access article below.

ANSLab at the University of Maryland. Shown, from left to right, is a Cambridge Nanotech Fiji F200 ALD Tool (Luigi), a glovebox for working with air-sensitive materials, a rotary wafer transporter (R2P2), thermal evaporation chamber, and second Cambridge Nanotech Fiji F200 ALD tool (Mario). (source: http://www.terpconnect.umd.edu/~ackozen/Research.html)

Atomic Layer Deposition of the Solid Electrolyte LiPON (OPEN ACCESS)

Alexander C. Kozen, Alexander J. Pearse, Chuan-Fu Lin, Malachi Noked, and Gary W. Rubloff

Chem. Mater., Article ASAP
DOI: 10.1021/acs.chemmater.5b01654

We demonstrate an atomic layer deposition (ALD) process for the solid electrolyte lithium phosphorousoxynitride (LiPON) using lithium tert-butoxide (LiOtBu), H2O, trimethylphosphate (TMP), and plasma N2 (PN2) as precursors. We use in-situ spectroscopic ellipsometry to determine growth rates for process optimization to design a rational, quaternary precursor ALD process where only certain substrate–precursor chemical reactions are favorable. We demonstrate via in-situ XPS tunable nitrogen incorporation into the films by variation of the PN2dose and find that ALD films over approximately 4.5% nitrogen are amorphous, whereas LiPON ALD films with less than 4.5% nitrogen are polycrystalline. Finally, we characterize the ionic conductivity of the ALD films as a function of nitrogen content and demonstrate their functionality on a model battery electrode—a Si anode on a Cu current collector.

Sol-gel Capacitor Dielectric Offers Record-high Energy Storage

Here are new wonderful results on a sol gel capacitor technology that could beat batteries in the future aiming at both high power and energy density. Thanks Heiko for helping me to find this one.  Georgia Tech reports : Using a hybrid silica sol-gel material and self-assembled monolayers of a common fatty acid, researchers have developed a new capacitor dielectric material that provides an electrical energy storage capacity rivaling certain batteries, with both a high energy density and high power density.

Samples of the new hybrid sol-gel material are shown placed on a clear plastic substrate for testing. (Credit: John Toon, Georgia Tech)

If the material can be scaled up from laboratory samples, devices made from it could surpass traditional electrolytic capacitors for applications in electromagnetic propulsion, electric vehicles and defibrillators. Capacitors often complement batteries in these applications because they can provide large amounts of current quickly.

“This is the first time I’ve seen a capacitor beat a battery on energy density,” said Perry. “The combination of high energy density and high power density is uncommon in the capacitor world.”

The new material is composed of a silica sol-gel thin film containing polar groups linked to the silicon atoms and a nanoscale self-assembled monolayer of an octylphosphonic acid, which provides insulating properties. The bilayer structure blocks the injection of electrons into the sol-gel material, providing low leakage current, high breakdown strength and high energy extraction efficiency.

Full story: http://www.news.gatech.edu/2015/07/29/sol-gel-capacitor-dielectric-offers-record-high-energy-storage

Publication: Yunsang Kim, et al., “Bilayer Structure with Ultra-high Energy/Power Density Using Hybrid Sol-Gel Dielectric and Charge Blocking Monolayer, (Advanced Energy Materials, 2015).http://www.dx.doi.org/10.1002/aenm.201500767

Presentations from AVS ALD 2015 and the Atomic Layer Etching Workshop Are Now Available

Presentations from the 15th International Atomic Layer Deposition Conference and the Atomic Layer Etching Workshop Are Now Available to AVS Members

ALD 2015/ALE 2015 Workshop Attendees will also be mailed a USB with all presentations at the end of August.  For Access Login to the AVS Technical Library using your MyAVS Membership E-mail and Password  These audio-recorded Presentations on Demand may be sorted by Title or Session. Poster presentations are available as PDFs. AVS Membership provides exclusive access to the AVS Technical Library featuring: Presentations on Demand - Audio-Synchronized Slides from Previous AVS International Symposia and Sponsored Conferences like Atomic Layer Deposition. View Sample Presentations: Sample 1 | Sample 2 Educational and Technical Resources - Books, Monographs, Videos +  Recommend Practices - Historical Standards  Not an AVS Member? Join Today