Exploring SMIC's 7nm Semiconductor Advancements: Technology, Dimensions, and Future Prospects

The recent introduction of Huawei's Mate 60 Pro smartphone, featuring a 7 nm chip from Semiconductor Manufacturing International Corp. (SMIC), has raised questions about the authenticity of SMIC's technological strides and their implications. This summary dives into the heart of SMIC's 7 nm technology, shedding light on its dimensions, technological intricacies, challenges, and the outlook for the future.

However, it has been known for some time that SMIC has been developing at putting out 7 nm chips, and an early 2022 assessment published at Seeking Alpha can be found here: Applied Materials: SMIC Move To 7nm Node Capability Another Headwind (NASDAQ:AMAT) | Seeking Alpha

The SMIC 7 nm Technology Debate

Central to the debate surrounding SMIC's technology is the classification of whether it genuinely qualifies as 7 nm. Parameters such as Fin Pitch (FP), Contacted Poly Pitch (CPP), and Metal 2 Pitch (M2P) are scrutinized. While SMIC's FP pitches are larger than TSMC's 10 nm, its CPP and M2P dimensions match TSMC's 10 nm, creating a complex classification.

SMIC appears to have a serviceable first generation 7nm process now with a reasonable prospect to get to second generation 7nm/6nm in the near futures. 5nm and 3nm while theoretically possible would be highly constrained and expensive process versions if pursued due to the lack of EUV. - Scotten Jones, SemiWiki (LINK)

Design Technology Co-Optimization (DTCO) Features

SMIC's 7 nm process introduces Design Technology Co-Optimization (DTCO) features uncommon in traditional 10 nm processes. Notably, SMIC's track height is smaller than TSMC and Samsung's 10 nm processes, approaching 7 nm-class characteristics. These features add to the nuanced evaluation of SMIC's technological position.

Cell Density and Cut Masks

SMIC's high-density logic cell boasts an impressive 89 million transistors per millimeter squared, akin to Samsung and TSMC's first-generation 7 nm processes. This suggests that SMIC's technology aligns with the 7 nm category, though the debate on its dimensions continues. Notably, SMIC's process introduces larger Contacted Poly Pitch (CPP) dimensions, hinting at potential performance challenges that necessitated this adjustment.

The EUV Challenge and Future Prospects and Alternative Technologies

SMIC's journey toward further technological advancements faces significant hurdles due to the unavailability of extreme ultraviolet lithography (EUV) systems in China. EUV technology plays a pivotal role in pushing semiconductor boundaries. However, ongoing US restrictions on EUV system shipments to China constrain SMIC's options for achieving cutting-edge technology.

Self aligned multi patterning (SAMP) in Advanced Logic Semiconductor Manufacturing

In advanced logic semiconductor manufacturing, addressing the challenges posed by sub-5 nm nodes and dense metal layers is essential. SMIC can consider alternative technologies like Atomic Layer Deposition (ALD) and Directed Self-Assembly (DSA) to overcome these hurdles.

ALD stands out for its precision in depositing thin films, allowing for the creation of ultra-thin etch masks, spacers, and precise control over critical dimensions. On the other hand, DSA leverages materials' self-assembly properties to form predefined patterns, effectively dividing pitch sizes and simplifying lithography masks.

Incorporating ALD and DSA into semiconductor manufacturing processes has the potential to enhance the capabilities of immersion lithography, enabling smaller nodes without the need for EUV lithography. While these technologies require further research and development, they offer promise in helping semiconductor manufacturers advance their technology and remain competitive, particularly in the absence of EUV lithography equipment.

Together with self-aligned multi-patterning (SAMP) techniques like self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), and self-aligned litho-etch-litho-etch (SALELE), these alternative approaches provide SMIC with a range of options to navigate the complexities of advanced semiconductor manufacturing, ultimately shaping the future of Chinese advanced chip fabrication.

The Future of Nanoimprint Lithography: High-Volume Production Possibilities

Nanoimprint lithography (NIL) offers potential for high-volume production with sub-10 nm resolution, revolutionizing semiconductor manufacturing. TEL and Canon have showcased NIL's sub-10 nm capabilities, making it suitable for multiple memory generations using a single mask. Challenges like edge placement errors (EPE) are addressed through precision techniques like Quasi-Atomic Layer Etch (Quasi-ALE). To achieve aggressive scaling targets, overlay accuracy and critical dimension uniformity (CDU) management are vital. NIL's simplicity and cost-effectiveness make it a promising contender, with ongoing development poised to refine its integration into semiconductor fabrication.

Future Outlook for SMIC and China

SMIC's path forward may involve alternative fabrication technologies such as ALD, DSA, and NIL. that offers the potential for high-volume production with sub-10 nm resolution.

By mastering and integrating these advanced technologies into semiconductor manufacturing could potentially expand immersion lithography's capabilities, accommodating smaller nodes without depending on EUV lithography. While further research and development are essential, these technologies offer potential pathways for SMIC to advance its fabrication processes and sustain competitiveness, particularly in the absence of EUV lithography equipment. These strategies, alongside self-aligned multi-patterning techniques, stand to influence the future of advanced chip fabrication in China beyond 7 nm. 

The answer is as always - it depends. For how long will China have access to also Immersion Lithography? Will top tier OEMs be allowed to continue to export ALD and other process technology needed to China? What will be the cost using higher complexity and additional masks needed for SAQP (cut masks)? Is Huawei's limited chip demand, as compared to Apple & Co, enough to pay for the R&D needed? Will Chinese state support cover the development and fab expansion cost? 

Sources:

193i Lithography Takes Center Stage...Again (semiengineering.com)

Does SMIC have 7nm and if so, what does it mean - SemiWiki

Look Inside Huawei Mate 60 Pro Phone Powered by Made-in-China Chip - Bloomberg

BALD Engineering - Born in Finland, Born to ALD: The Future of Nanoimprint Lithography: Exploring Possibilities and Challenges for High-Volume Production

BALD Engineering - Born in Finland, Born to ALD: Comparison confirms that SMIC reaches 7nm without access to western equipment & technologies

Applied Materials: SMIC Move To 7nm Node Capability Another Headwind (NASDAQ:AMAT) | Seeking Alpha

Comparison confirms that SMIC reaches 7nm without access to western equipment & technologies

Similarities with TSMC 7nm have been found

After TechInsights revealed their initial findings on the SMIC MinerVa Bitcoin mining processor, their team did further analysis and comparison against TSMC 7nm. This new analysis confirms that despite current sanctions restricting access to the most advanced equipment technologies, Chinese Semiconductor Manufacturing International Corporation (SMIC) has used 7nm technology to manufacture the MinerVa Bitcoin Miner application-specific integrated circuit (ASIC).

The TechInsights analysis also uncovered many similarities between the SMIC 7nm and the TSMC 7nm, which are available in our comparison brief.

Source: SMIC 7nm is truly 7nm technology, how it compares to TSMC 7nm | TechInsights

According to the SeekingAlpha assessment earlier this year (Applied Materials: SMIC Move To 7nm Node Capability Another Headwind (NASDAQ:AMAT) | Seeking Alpha) SMIC is using a large amount of multiple pattering mask layers like in the first TSMC and Samsung 7 nm nodes (N7). 

"At 7nm, normally 15 DUV systems and 5 EUV systems are demanded, depending on chip type and company. However, since SMIC is not permitted to use EUV, then they will be substituted by DUV, and 20 DUV systems will be used.

In both cases, multiple patterning is done to delineate that pattern, whether it is 28nm or 7nm. This multiple patterning process is more or less a trick to reach even the 28nm dimensions. The multiple patterning is typically a combination of deposition, etch, and lithography steps.

If we look at Chart 3 below, using immersion DUV (ArF-1) at the 20nm node there are 13 mask layers, each of which uses multiple dep-etch steps. If we move across the top of the chart, at 10nm there are 18 mask layers, an increase of 50% in the use of deposition-etch steps.

Multiple patterning at the 7nm node, as shown in the bottom left of the chart, requires 27 mask layers. However, by switching to EUV (bottom right) at 7nm, only 14 mask layers are required, similar to the 20nm node with DUV.

The terminology is as follows in switching from DUV to EUV:Double litho, double etch (LELE) process will be eliminated

While ArF-I would continue to be used for the self-aligned double patterning (SADP) and

Self-aligned quadruple patterning (SAQP) processes."

 

Table from SeekingAlpha as cited above

From an ALD point of view, the FEOL and metallization up to M2 use 19 in the case of Immersion Lithography (N7) vs 10 in the case of EUV (N7+) ALD spacer-defined multiple patterning masks (SADP or SAQP). However, the bigger difference is in etch for LELE etc., where EUV N7+ uses only 2 such masks.