Showing posts with label Intel. Show all posts
Showing posts with label Intel. Show all posts

Sunday, October 22, 2017

Intel to present 10 nm Logic with 3rd gen FinFET and 2 level Cobalt interconnect

IEDM 2017 Announcement (LINK, Press kit): Intel researchers will present a 10nm logic technology platform with excellent transistor and interconnect performance and aggressive design-rule scaling. They demonstrated its versatility by building a 204Mb SRAM having three different types of memory cells: a high-density 0.0312µm2 cell, a low voltage 0.0367µm2 cell, and a high-performance 0.0441µm2 cell. The platform features 3rd-generation FinFETs fabricated with self-aligned quadruple patterning (SAQP) for critical layers, leading to a 7nm fin width at a 34nm pitch, and a 46nm fin height; a 5th-generation high-k metal gate; and 7th-generation strained silicon. There are 12 metal layers of interconnect, with cobalt wires in the lowest two layers that yield a 5-10x improvement in electromigration and a 2x reduction in via resistance. NMOS and PMOS current is 71% and 35% greater, respectively, compared to 14nm FinFET transistors. Metal stacks with four or six workfunctions enable operation at different threshold voltages, and novel self-aligned gate contacts over active gates are employed.

The graph on the left shows that the new platform maintains traditional scaling trends, while the photomicrograph on the right shows the platform’s 12-layer interconnect stack.


Reference: Paper 29.1, “A 10nm High Performance and Low-Power CMOS Technology Featuring 3rd-Generation FinFET Transistors, Self-Aligned Quad Patterning, Contact Over Active Gate and Cobalt Local Interconnects,” C. Auth et al, Intel

2017 IEEE International Electron Devices Meeting
December 2-6, 2017
Hilton San Francisco Union Square
333 O’Farrell Street
San Francisco, CA 94102

Wednesday, March 29, 2017

Intel announce first SAQP in Logic and Much Moore at 10 nm

Intel announce first SAQP and Much Moore at 10 nm during their most recent Investor Show (March 28, 2017). SAQP is already process of record in DRAM at Sasmung since 2016 10 nm class DRAM was introduced (LINK)



Technology Manufacturing Day - Strategy Overview (Stacy Smith)


Technology Manufacturing Day - Moore’s Law (Mark Bohr)

Technology Manufacturing Day - 14nm Leadership (Ruth Brain)


Technology Manufacturing Day - 10nm Leadership (Kaizad Mistry)



[check out slide 13, screendump]


Technology Manufacturing Day - 22FFL (Mark Bohr)


Technology Manufacturing Day - IDM Advantage (Murthy Renduchintala)


All recent briefings: LINK