Showing posts with label Graphene. Show all posts
Showing posts with label Graphene. Show all posts

Monday, July 1, 2019

Aixtron launch CVD equipment for production of graphene

[Graphen Flagship News, LINK] From prototypes to products: AIXTRON's new systems enable cost-effective and large-scale production of graphene and related materials by chemical vapour deposition. Today, Graphene Flagship industrial partner AIXTRON showcased two new systems that enable cost-effective graphene production for a myriad of applications – such as consumer electronics, sensors, and photonics.The new devices allow the production of graphene under ambient conditions, and bring the cost of graphene films down by two orders of magnitude. 

The Neutron is a roll-to-roll system capable of depositing large areas of graphene on metal foils under ambient conditions (Photo: EU Graphene Flagship)


Graphene Flagship partner AIXTRON introduced results from two of its systems that enable the large-scale production of graphene through chemical vapour deposition (CVD). The Neutron is a roll-to-roll system capable of depositing large areas of graphene on metal foils under ambient conditions; and the CCS 2D system enables wafer-scale production of graphene on insulating wafers, a breakthrough that will speed up the development of new graphene electronics. To demonstrate the cost-effective nature of the graphene produced, AIXTRON distributed samples at the Industrial Forum.



The innovative Neutron system has a capacity of up to 20,000 square meters of graphene per year; this is around 200 times the production capacity of typical reactors in use today. Alex Jouvray, Programme Manager at AIXTRON and Graphene Flagship Work Package Leader for Production, explains that "Neutron is the product that resulted from of over three years of R&D, which included the demonstration of roll-to-roll graphene growth during the first stages of the Graphene Flagship project." Neutron brings the production of large areas of graphene beyond academic circles and to the factory floor. "The foil that is coated with graphene enters and exits the Neutron system under ambient conditions," explains Jouvray. "Since it doesn't need a vacuum, the Neutron can be easily placed inline at graphene manufacturing plants," he adds. Large-area monolayer graphene produced using this novel technique could lead to applications in transparent conductors, wearable devices, and coatings. "Moreover, it's economical," adds Jouvray. "With Neutron, we are able to bring the cost of a square meter of graphene CVD films down by two orders of magnitude," he explains. "It's a game-changer."

The versatile CCS system targets semiconductor applications. Here, there are stringent contamination requirements; usually, graphene needs to be grown on metallic surfaces and foils, which, being non-flat, are challenging to handle in the semiconductor industry and contain metal contamination that require further cleaning steps before the material can enter a fab. During the first years of the Graphene Flagship project, together with the group of Camilla Coletti at Graphene Flagship partner Istituto Italiano di Tecnologia (IIT), AIXTRON scaled the growth of graphene on insulators to full wafer-scale on its CCS 2D reactor, which can accommodate 2-inch up to 8-inch wafers. The wafers exhibit low contamination levels that meet the requirements of semiconductor fabs directly after growth. Camilla Coletti comments that "such tremendous progress is only possible thanks to the Graphene Flagship project which brings together top scientists from academia and engineers from a world-leading equipment company." The system is also capable of large-scale production of other layered materials, such as boron nitride or transition metal dichalcogenides.

Kari Hjelt, Head of Innovation of the Graphene Flagship believes that "these systems developed by AIXTRON show how our investment into prototypes during the first years of the Graphene Flagship are leading to products that enable mass production of graphene by chemical vapour deposition." He adds, "these discoveries open up thousands of possibilities beyond graphene, the arrival of wafers featuring other layered materials, or even 'sandwich' heterostructures are just around the corner," concludes Hjelt.

Andrea C. Ferrari, Science and Technology Officer of the Graphene Flagship and Chair of its Management Panel added that "the ultimate aim of the Graphene Flagship is to bring graphene and related layered materials from the lab to the factory floor. To take these new materials to the traditional semiconductor fabs, which is key to achieve their widespread application in consumer electronics, photonics and sensors, industrial tools capable of large area, large rate and low-cost manufacturing of graphene and related materials are needed.""With these systems," —adds Ferrari— "Graphene Flagship Partner AIXTRON leads the way fostering the new market opportunities that these new materials open. The ability to produce large scale graphene viably is of particular importance as the Graphene Flagship gears up to launch the first Graphene Foundry. Moreover, these products are a cornerstone in the innovation and technology roadmap of the Graphene Flagship, and shows that we are set to achieve the ambitious goals for our first ten years."

Wednesday, January 3, 2018

Cornell University fabricate cell-sized origami robots by an ALD & graphene nanotechnology

Cornell University reports that one of their researcher teams has made a robot exoskeleton that can rapidly change its shape upon sensing chemical or thermal changes in its environment. And, they claim, these microscale machines – equipped with electronic, photonic and chemical payloads – could become a powerful platform for robotics at the size scale of biological microorganisms. Their work is outlined in “Graphene-based Bimorphs for Micron-sized, Autonomous Origami Machines,” published Jan. 2 in Proceedings of the National Academy of Sciences. Miskin is lead author; other contributors included David Muller, the Samuel B. Eckert Professor of Engineering, and doctoral students Kyle Dorsey, Baris Bircan and Yimo Han. [Graphene-based bimorphs for micron-sized, autonomous origami machines. Marc Z. Miskin et al (2018), PNAS https://doi.org/10.1073/pnas.1712889115 ]

Please check out this interview video for more amazing details - some snapshots are given below in  the form of screen dumps from vimeo [LINK]
 
 
 
The bimorph is built using atomic layer deposition of atomically thin layers (2 nm) of silicon dioxide onto aluminum over a cover slip – then wet-transferring a single atomic layer of graphene on top of the stack. The result is the thinnest bimorph ever made. [Vimeo Screen dump]
 

Processing has been taken place in Cornell University Clean room - Cornell NanoScale Facility for Science and Technology, here showing the ALD reactor and rpocessing of the SiO2 layer (Oxford Instruments, FlexAl) [Vimeo Screen dump]


The researchers can fabricate many different forms of origami shapes ranging from simple tetrahedrons to cubes and helix shaped objects [Vimeo Screen dump]
 

 
With this new amazing technology, the Cornell rersearchers are developing robotic ‘exoskeleton’ for electronics with integrated microchips. [Vimeo Screen dump]
 
 
 

Friday, August 11, 2017

A new featherweight, flame-resistant and super-elastic metamaterial from Purdue Uniuversity

Purdue University reports: WEST LAFAYETTE, Ind. — A new featherweight, flame-resistant and super-elastic metamaterial has been shown to combine high strength with electrical conductivity and thermal insulation, suggesting potential applications from buildings to aerospace.


A new composite material combines ultra-lightweight with flame-resistance, super-elasticity and other attributes that could make it ideal for various applications. Here, the material is viewed with a scanning electron microscope, while its flame resistance is put to the test. (Purdue University photo)

[From the abstract, Adv. Mater., DOI: 10.1002/adma.201605506] "A ceramic/graphene metamaterial (GCM) with microstructure-derived superelasticity and structural robustness is achieved by designing hierarchical honeycomb microstructures, which are composited with two brittle constituents (graphene and ceramic) assembled in multi-nanolayer cellular walls. Attributed to the designed microstructure, well-interconnected scaffolds, chemically bonded interface, and coupled strengthening effect between the graphene framework and the nanolayers of the Al2O3 ceramic (NAC), the GCM demonstrates a sequence of multifunctional properties simultaneously that have not been reported for ceramics and ceramics–matrix–composite structures, such as flyweight density, 80% reversible compressibility, high fatigue resistance, high electrical conductivity, and excellent thermal-insulation/flame-retardant performance simultaneously."
 
Findings were detailed in a research paper published on May 29 in the journal Advanced Materials. The paper was a collaboration between Purdue, Lanzhou University and the Harbin Institute of Technology, both in China, and the U.S. Air Force Research Laboratory. A research highlight about the work appeared in the journal Nature Research Materials and is available at https://www.nature.com/articles/natrevmats201744.pdf. A YouTube video (below) about the work is available at https://youtu.be/PVd-eS_KMlU.

The ALD process of the nanolayer Al2O3 ceramic (NAC) were performed in an Utratech Fiji F200 (now Veeco CNT) ALD system at 250 °C using trimethylaluminum (TMA) and H2O.
 
 

Sunday, July 2, 2017

New process for 2D MoS2 from Oxford Instruments

Scientists at Plasma Technology have developed a new process to deposit 2D MoS2 layers directly on Graphene, creating atomic layer heterostructures. This graphene-semiconductor film is a functional layer with applications in photodetection and sensing.

Source: Oxford Instruments LINK 

MoS2 grown on Grephene (Oxford Instruments)

Tuesday, June 20, 2017

Light, Superelastic, Electrically Conductive, and Flame-Retardant Graphene / ALD Ceramic Metamaterial

Researcher from Lanzhou University (China) and Purdue University (USA) has developed a new ceramic/graphene wonder metamaterial (GCM) with microstructure-derived superelasticity and structural robustness is achieved by designing hierarchical honeycomb microstructures

The GCM is composited by two brittle constituents (graphene and ceramic) assembled in multi-nanolayer cellular walls. The GCM demonstrates a sequence of multifunctional properties simultaneously that have not been reported for ceramics and ceramics–matrix–composite structures, such as: 
  • flyweight density
  • 80% reversible compressibility
  • high fatigue resistance
  • high electrical conductivity
  • excellent thermal-insulation/flame-retardant performance simultaneously. 


All details can be find in the Advanced Materials publication below. According to the suppoirting information the Al2O3 ceramic depositions were performed in an Utratech Fiji F200 ALD system (pictured above) at 250 C using trimethylaluminum (TMA) and H2O as the aluminum and oxygen source, respectively.


Flyweight, Superelastic, Electrically Conductive, and Flame-Retardant 3D Multi-Nanolayer Graphene/Ceramic Metamaterial
Qiangqiang Zhang et al
Adv. Mater., DOI: 10.1002/adma.201605506

Tuesday, June 13, 2017

Atomic layer deposition for device integration of graphene (Review)

Just published by Prof. Kessels: A brief and easy-to-read synopsis of our new review paper about ALD for device integration of graphene as published in Advanced Materials Interfaces (Atomic Layer Deposition for Graphene Device Integration, 26 May 2017, DOI: 10.1002/admi.201700232).

Atomic Limitts Blog: LINK

Picture from AtomicLimits.com
 


Friday, March 24, 2017

Uniform ALD Al2O3 on graphene for future logic devices

TU Eindhoven and Philips Innovation Labs have just publishe a very intersteing paper on ALD of Al2O3 on prestine graphene inclusing various post deposition treatments to achive higher mobility. The trick to deposit uniform Al2O3 on graphene is by using reversible hydrogen plasma functionalization prior to ALD Al2O3 using a Oxford Instruments FlexAl PEALD reactor. Please check tha paper in Chemistrry of Materials below for more details.

Uniform Atomic Layer Deposition of Al2O3 on Graphene by Reversible Hydrogen Plasma Functionalization

René H. J. Vervuurt, Bora Karasulu, Marcel A. Verheijen, Wilhelmus (Erwin) M. M. Kessels, and Ageeth A. Bol

Chem. Mater., 2017, 29 (5), pp 2090–2100
DOI: 10.1021/acs.chemmater.6b04368




Thursday, February 9, 2017

One atomic layer has been deposited by ALD on graphene at UNIST

EUREKALERT! reports: ULSAN, South Korea--A new study, affiliated with UNIST has introduced a novel method for fabrication of world's thinnest oxide semiconductor that is just one atom thick. This may open up new possibilities for thin, transparent, and flexible electronic devices, such as ultra-small sensors.


Friday, January 6, 2017

Functional OLEDs on Graphene electrodes by Fraunhofer FEP and Partners

Fraunhofer FEP reports that for the first time it has been shown possible to produce functional OLED electrodes from graphene. Such OLEDs can be integrated into touch displays according to the report.



  • Flexible OLED electrodes from graphene
  • The perfect material: transparent, stable, flexible, conductive
  • Ideal for touch screens, photovoltaic, wearables and much more

Above in a tweet embedded from Fraunhofer FEP an Orange luminous OLED fabricated on a graphene electrode. The process was developed and optimized in the EU-funded project "Gladiator" (12.4 M EUR - Graphene Layers: Production, Characterization and Integration) and you can find mor information here on the Fraunhofer FEP news release. Important partners where the Spanish company Graphena S.A. and British Aixtron supplier of the CVD reactor for Graphene growth.



Aixtron is offering CVD reactors for graphene and CNT growth. The AIXTRON BM systems can operate in both thermal CVD and plasma-enhanced CVD modes. The systems are based on the highly scalable showerhead concept and are available for wafer-sizes from 50mm to 300mm diameter. (aixtron.com pdf flyer)
Spanish company Graphenea S.A., which is responsible for the production of the graphene electrodes, as well as the British Aixtron Ltd., which is responsible for the construction of the production CVD reactors.

Read more at: http://phys.org/news/2017-01-milestone-graphene-production.html#jCp
Spanish company Graphenea S.A., which is responsible for the production of the graphene electrodes, as well as the British Aixtron Ltd., which is responsible for the construction of the production CVD reactors.

Read more at: http://phys.org/news/2017-01-milestone-graphene-production.html#jCp
Spanish company Graphenea S.A., which is responsible for the production of the graphene electrodes, as well as the British Aixtron Ltd.,

Read more at: http://phys.org/news/2017-01-milestone-graphene-production.html#jCp
Spanish company Graphenea S.A., which is responsible for the production of the graphene electrodes, as well as the British Aixtron Ltd.,

Read more at: http://phys.org/news/2017-01-milestone-graphene-production.html#jCp

Monday, September 5, 2016

US and Korean Researchers Making pristine graphene in a microwave oven

Nanotechweb.org reports : Researchers at Rutgers University in the US and UNIST in Korea have succeeded in producing high-quality graphene by simply zapping graphene oxide with microwaves for 1–2 seconds. The new technique produces pristine graphene that has an electron mobility as high as 1500 cm2/V/s when made into field-effect transistors with graphene as the channel material. This is among the highest value ever obtained from reduced graphene oxide materials.
 
 
 Continue reading here.
 

Monday, February 15, 2016

Resilient, customized, and high-performing graphene on top of common glass

Brookhaven National Laboratory reports: Graphene, the two-dimensional powerhouse, packs extreme durability, electrical conductivity, and transparency into a one-atom-thick sheet of carbon. Despite being heralded as a breakthrough "wonder material," graphene has been slow to leap into commercial and industrial products and processes.

Now, scientists have developed a simple and powerful method for creating resilient, customized, and high-performing graphene: layering it on top of common glass. This scalable and inexpensive process helps pave the way for a new class of microelectronic and optoelectronic devices—everything from efficient solar cells to touch screens.


 
Left: Schematic of a graphene field-effect-transistor used in this study. The device consists of a solar cell containing graphene stacked on top of a high-performance copper indium gallium diselenide (CIGS) semiconductor, which in turn is stacked on an industrial substrate (either soda-lime glass, SLG, or sodium-free borosilicate glass, BSG). The research revealed that the SLG substrate serves as a source of sodium doping, and improved device performance in a way not seen in the sodium-free substrate. Right: A scanning electron micrograph of the device as seen from above, with the white scale bar measuring 10 microns, and a transmission electron micrograph inset of the CIGS/graphene interface where the white scale bar measures 100 nanometers. (from Brookhaven National Laboratory report)
 
The collaboration—led by scientists at the U.S. Department of Energy's (DOE) Brookhaven National Laboratory, Stony Brook University (SBU), and the Colleges of Nanoscale Science and Engineering at SUNY Polytechnic Institute—published their results February 12, 2016, in the journal Scientific Reports.[Free, Open Access]
 
For sure you already spotted teh Al2O3 dielectric on the picture and yes it is deposietd by ALD, as reported in the paper: "Next, a 200 nm top gate-dielectric layer (Al2O3) is blanket deposited on GR/CIGS/Mo/SLG(BSG) or GR/SLG(BSG) substrates via Atomic Layer Deposition at 1 Ǻ/cycle using (Tri Methyl Aluminum) TMA/Water precursor at 250 °C." The detailed process integration can be foudn in the Supporting information (insered below)


 (This work is licensed under a Creative Commons Attribution 4.0 International License)

Saturday, February 13, 2016

ALD HfO2 HKMG FETs on CVD mono layer graphene channels on 200 mm glass wafers by Samsung

Samsung Advanced Institute of Technology and Samsung-SKKU Graphene/2D Center showcases ALD HfO2 high-k transistors on mono layer graphene channels using 200 mm glass wafers. The ALD Process is TEMAHf/H2O running at 200 C and they achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors.
 
Check out the free to down load Nature Scientific Report below.

 
SAIT (Samsung Advanced Institute of Technology)

Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors. 

Seong-Jun Jeong, Yeahyun Gu, Jinseong Heo, Jaehyun Yang, Chang-Seok Lee, Min-Hyun Lee, Yunseong Lee, Hyoungsub Kim, Seongjun Park & Sungwoo Hwang
Sci. Rep. 6, 20907; doi: 10.1038/srep20907 (2016).



(a) Optical image of the MOG-FET arrays fabricated on a 6″ Si wafer and a schematic illustration showing the structure of the MOG-FET device. (b) Optical microscope image of a fabricated MOG-FET unit device. (c) Cross sectional TEM image showing the HfO2 gate dielectric layer with a thickness of ~5 nm (including the seed layer converted to a HfO2 layer) on monolayered graphene. (d) Statistical distribution of the sheet resistance of a monolayered graphene before and after the ALD of HfO2 with and without an e-beam-evaporated Hf seed layer. Representative electrical characteristics measured from the fabricated MOG-FET devices: (e) gate dielectric leakage current, (f) gate capacitance as a function of the frequency, and (g) transfer curve (ID-VG). (Sci. Rep. 6, 20907; doi: 10.1038/srep20907 (2016)., Creative Commons Attribution 4.0 International License)

The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer.

Friday, December 18, 2015

European researchers reach graphene production breakthrough, under project GRAFOL

Graphene-info reports: Researchers involved in the €10.6 million European research project called GRAFOL have reportedly demonstrated a cost-effective roll-to-roll production tool capable of making large sheets of graphene on an industrial scale. The tool operates at atmospheric pressure and at reduced operating temperature, and is proclaimed by the researchers "the best route to low-cost manufacture".



Graphene-enhanced perovskite PV (Graphene-info)

Wednesday, November 18, 2015

Graphene - ALD bendable Supercaps by Nanyang Technological University and Partners

Nanowerk had an interesting post today on how Nanyang Technological University and Partners in Singapore and China are using graphene and ALD Metal Nitrides to fabricate bendable solid-state asymmetric super capacitors. Check out the processing to achieve the metal nitrides below - not the usual way but via the oxides and solution based chemistry! I assume that graphene is a tricky material to grow metal nitrides on


Illustration of the asymmetric supercapacitor, consisting of vertically aligned graphene nanosheets coated with iron nitride and titanium nitride as the anode and cathode, respectively. (as published in Nanowerk, ©WILEY-VCH Verlag)


"To get the maximum benefit from the graphene surface, the team used a precise method for creating thin-films, a process known as atomic layer deposition, to grow two different materials on vertically aligned graphene nanosheets: titanium nitride for their supercapacitor’s cathode and iron nitride for the anode." 



Tracking back to the original publication in Advanced Materials "All Metal Nitrides Solid-State Asymmetric Supercapacitors" DOI: 10.1002/adma.201501838 there are some more details available in the free to download supporting information from the authors where it is reviled that a BENEQ TFS 200 ALD reactor was used for the cathode and anode. Here´s the link and some details are given below:

A BENEQ TFS 200 that come in many sorts and flavours (www.beneq.com)

Electrode Material Synthesis

Preparation of TiN@GNS Cathode: All chemicals were bought from Sigma Aldrich and used without further purification. Graphene nanosheets (467 m2 g-1) were provided by INCUBATION ALLIANCE, INC. The cathode fabrication process is mainly composed of two steps: TiO2 deposition by atomic layer deposition (ALD) and transferring to nitride through annealing in ammonia (NH3) atmosphere. Before ALD, the GNS substrates were treated with oxygen plasma at 200 W for 10 minutes with an O2 gas flow of 100 sccm, 70 mTorr. In a typical ALD (Beneq TFS 200) process, 120 °C was applied to the GNS substrate with TiCl4 and water as the titanium and oxygen source, respectively. 166 cycles (~ 1.2 Å per cycle) deposition was conducted to obtain 20 nm TiO2 coating during which the reaction chamber was maintained with a steady N2 steam at 300 sccm (cubic centimeter per minute) at 1.0 mbar. The sample of TiO2@GNS was then annealed in NH3 atmosphere at 800 °C for 1 h with a gas flow of 50 sccm and heating rate of 20 °C per minute. The control sample of TiO2@GNS was synthesized with the same ALD process. 

Preparation of Fe2N@GNS Anode: 20 nm ZnO was deposited on GNS (oxygen plasma pretreated) with ALD at 200 °C. The ZnO@GNS sample was then immersed in 0.5 M Fe(NO3)3 solution for 2 h to have a thorough transformation from ZnO to FeOOH as reported by the previous work[1]. The FeOOH@GNS sample was then annealed with the same NH3 atmosphere situation at a lower temperature of 600 °C. The control sample of FeOOH@GNS was fabricated by the same method just without the afterward annealing.

Also Available in the supporting information linked above is a quite impressive results from a bending test odf a charged super capacitor (see figure below)


Capacitance retention of the full device at different bending conditions. "All Metal Nitrides Solid-State Asymmetric Supercapacitors" DOI: 10.1002/adma.201501838 (©WILEY-VCH Verlag).

Tuesday, November 10, 2015

ALD employed in nanographene charge trapping memory with a large memory window

A leading research centre for grapehene devices is Beijing National Laboratory for Condensed Matter Physics and Institute of Physics, Chinese Academy of Science. They have recently published a paper on Nanographene charge trapping memory. Here they use a 15 nm thick Al2O3, deposited by ALD, to act as a tunnelling layer and blocking layer, respectively (see abstract below).


According to the website: The research groups led by Prof. ZHANG Guangyu is recently focusing on graphene nanostructure fabrications and the related electrical transport studies and has:

Schematic of the graphene edge lithography. The process includes selectively ALD of Al2O3/HfO2 on graphene edges, dry etching of the unprotected graphene and KOH etching of the metal oxides.(Image by ZHANG Guangyu et al )

Nanographene charge trapping memory with a large memory window

Jianling Meng, Rong Yang, Jing Zhao, Congli He, Guole Wang, Dongxia Shi and Guangyu Zhang


 Left, AFM images of nanographen films showing a high density of nanographen islands. Right, the stack and structure of the nanographene charge tarpping memory cell (PhysOrg: http://phys.org/news/2015-11-nanographene-memory-miniaturize.html)


(Left) Atomic force microscope image of the nanographene film with a high density of nanographene islands, which provide more charge-trapping sites to increase store capacity. (Right) Structure of the nanographene-based charge trapping memory. Credit: Meng, et al. ©2015 IOP Publishing

Read more at: http://phys.org/news/2015-11-nanographene-memory-miniaturize.html#jCp
(Left) Atomic force microscope image of the nanographene film with a high density of nanographene islands, which provide more charge-trapping sites to increase store capacity. (Right) Structure of the nanographene-based charge trapping memory. Credit: Meng, et al. ©2015 IOP Publishing

Read more at: http://phys.org/news/2015-11-nanographene-memory-miniaturize.html#jCp
Nanographene is a promising alternative to metal nanoparticles or semiconductor nanocrystals for charge trapping memory. In general, a high density of nanographene is required in order to achieve high charge trapping capacity. Here, we demonstrate a strategy of fabrication for a high density of nanographene for charge trapping memory with a large memory window. The fabrication includes two steps: (1) direct growth of continuous nanographene film; and (2) isolation of the as-grown film into high-density nanographene by plasma etching. Compared with directly grown isolated nanographene islands, abundant defects and edges are formed in nanographene under argon or oxygen plasma etching, i.e. more isolated nanographene islands are obtained, which provides more charge trapping sites. As-fabricated nanographene charge trapping memory shows outstanding memory properties with a memory window as wide as ~9 V at a relative low sweep voltage of ±8 V, program/erase speed of ~1 ms and robust endurance of >1000 cycles. The high-density nanographene charge trapping memory provides an outstanding alternative for downscaling technology beyond the current flash memory.

Sunday, October 11, 2015

Wafer-scale single-domain-like graphene by defect-selective ALD of hexagonal ZnO

Korean researchers report defect-selective atomic layer deposition (ALD) for stitching grain boundaries of CVD graphene with ZnO to increase the connectivity between grains. In the present ALD process, ZnO with a hexagonal wurtzite structure was selectively grown mainly on the defect-rich grain boundaries to produce ZnO-stitched CVD graphene with well-connected grains.

Wafer-scale single-domain-like graphene by defect-selective atomic layer deposition of hexagonal ZnO

Kyung Sun Park, Sejoon Kim, Hongbum Kim, Deokhyeon Kwon, Yong-Eun Koo Lee, Sung-Wook Min, Seongil Im, Hyoung Joon Choi, Seulky Lim, Hyunjung Shin, Sang Man Koo and Myung Mo Sung

Nanoscale, 2015, Advance Article, DOI: 10.1039/C5NR05392GAccepted 24 Sep 2015



Large-area graphene films produced by means of chemical vapor deposition (CVD) are polycrystalline and thus contain numerous grain boundaries that can greatly degrade their performance and produce inhomogeneous properties. A better grain boundary engineering in CVD graphene is essential to realize the full potential of graphene in large-scale applications. Here, we report a defect-selective atomic layer deposition (ALD) for stitching grain boundaries of CVD graphene with ZnO so as to increase the connectivity between grains. In the present ALD process, ZnO with a hexagonal wurtzite structure was selectively grown mainly on the defect-rich grain boundaries to produce ZnO-stitched CVD graphene with well-connected grains. For the CVD graphene film after ZnO stitching, the inter-grain mobility is notably improved with only a little change in the free carrier density. We also demonstrate how ZnO-stitched CVD graphene can be successfully integrated into wafer-scale arrays of top-gated field-effect transistors on 4-inch Si and polymer substrates, revealing remarkable device-to-device uniformity.

UK collaboration seeks to develop new ultra-barrier materials based on graphene interlayers & roll to roll ALD

As reported by New Electronics : The Centre of Process Innovation (CPI) has announced that it has joined a UK based collaboration called ‘Gravia’, to develop the next generation of ultra-barrier materials using graphene for the production of flexible transparent plastic electronic based displays for the next generation of smartphones, tablets and wearable electronics.



The graphene market is predicted to be worth more than £800million by 2023 and could transform the manufacturing landscape in the UK.The project, including the University of Cambridge, FlexEnable and the National Physical Laboratory (NPL), expects to deliver a feasible material and process system. It builds upon existing investments by Innovate UK and the EPSRC in this area.


CPI Cleanroom

“The collaboration brings together world class supply chain expertise across the UK to bridge the gap from Graphene research to the manufacturing of commercial flexible display screens,” said James Johnstone, business development manager at CPI. 

“CPI’s role in the project is to use roll-to-roll atomic layer deposition technologies to scale up, test and fabricate the ultra barrier materials.”


Beneq Roll to Roll Atomic Layer Deposition Tool - CPI offers a roll to roll atomic layer deposition (ALD) tool which is capable of handling films up to 600mm wide with thicknesses ranging from 20 – 200 µm and can produce an active coat width of 480mm.

The incorporation of graphene interlayers offers potential for flexible displays. Its gas blocking properties will enable barrier materials that are flexible, transparent, robust, and impervious to many molecules. Gravia will seek to accelerate product development, improving upon current ultra barrier performance and lifetimes by producing consistent barrier materials and processes on large area substrates by utilising specialist growth techniques. The key challenge will be to develop large-area poly-crystalline graphene films which maximise performance whilst mitigating process imperfections.

Saturday, October 3, 2015

Graphene as a front contact for silicon-perovskite tandem solar cells

As reported by HZB : HZB team develops elegant process for coating fragile perovskite layers with graphene for the first time. Subsequent measurements show that the graphene layer is an ideal front contact in several respects.

The perovskite film (black, 200-300 nm) is covered by Spiro.OMeTAD, Graphene with gold contact at one edge, a glass substrate and an amorphous/crystalline silicon solar cell. Credit: F. Lang / HZB

Silicon absorbers primarily convert the red portion of the solar spectrum very effectively into electrical energy, whereas the blue portions are partially lost as heat. To reduce this loss, the silicon cell can be combined with an additional solar cell that primarily converts the blue portions. Teams at HZB have already acquired extensive experience with these kinds of tandem cells. A particularly effective complement to conventional silicon is the hybrid material called perovskite. It has a band gap of 1.6 electron volts with organic as well as inorganic components. However, it is very difficult to provide the perovskite layer with a transparent front contact. While sputter deposition of indium tin oxide (ITO) is common practice for inorganic silicon solar cells, this technique destroys the organic components of a perovskite cell.
 

Graphene as transparent front contact:

Now a group headed by Prof. Norbert Nickel has introduced a new solution. Dr. Marc Gluba and PhD student Felix Lang have developed a process to cover the perovskite layer evenly with graphene. Graphene consists of carbon atoms that have arranged themselves into a two-dimensional honeycomb lattice forming an extremely thin film that is highly conductive and highly transparent.

Fishing for graphene:

As a first step, the scientists promote growth of the graphene onto copper foil from a methane atmosphere at about 1000 degrees Celsius. For the subsequent steps, they stabilise the fragile layer with a polymer that protects the graphene from cracking. In the following step, Felix Lang etches away the copper foil. This enables him to transfer the protected graphene film onto the perovskite. “This is normally carried out in water. The graphene film floats on the surface and is fished out by the solar cell, so to speak. However, in this case this technique does not work, because the performance of the perovskite degrades with moisture. Therefore we had to find another liquid that does not attack perovskite, yet is as similar to water as possible”, explains Gluba.

Ideal front contact:

Subsequent measurements showed that the graphene layer is an ideal front contact in several respects. Thanks to its high transparency, none of the sunlight’s energy is lost in this layer. But the main advantage is that there are no open-circuit voltage losses, that are commonly observed for sputtered ITO layers. This increases the overall conversion efficiency. “This solution is comparatively simple and inexpensive to implement”, says Nickel. “For the first time, we have succeeded in implementing graphene in a perovskite solar cell. This enabled us to build a high-efficiency tandem device.”
 

Perovskite Solar Cells with Large-Area CVD-Graphene for Tandem Solar Cells

Felix Lang, Marc A. Gluba, Steve Albrecht, Jörg Rappich, Lars Korte, Bernd Rech, and Norbert H. Nickel
J. Phys. Chem. Lett., 2015, 6 (14), pp 2745–2750
DOI: 10.1021/acs.jpclett.5b0117

Wednesday, August 5, 2015

Korea University present wafer-scale graphene on silicon substrates

Researchers have a method to synthesize graphene at the wafer-scale. Their work, published in Applied Physics Letters, makes large-area synthesis of graphene compatible with silicon microelectronics. In the last decade, graphene has been intensively studied for its unique optical, mechanical, electrical and structural properties. The one-atom-thick carbon sheets could revolutionize the way electronic devices are manufactured and lead to faster transistors, cheaper solar cells, new types of sensors and more efficient bioelectric sensory devices. As a potential contact electrode and interconnection material, wafer-scale graphene could be an essential component in microelectronic circuits, but most graphene fabrication methods are not compatible with silicon microelectronics, thus blocking graphene's leap from potential wonder material to actual profit-maker. “For integrating graphene into advanced silicon microelectronics, large-area graphene free of wrinkles, tears and residues must be deposited on silicon wafers at low temperatures, which cannot be achieved with conventional graphene synthesis techniques as they often require high temperatures,” explained Professor Kim Jihyun of Korea University. Read more from Asian Scientist Magazine at: http://www.asianscientist.com/2015/08/tech/korea-wafer-scale-graphene-silicon-microelectronics/
 
As reported by AZONano: A team of researchers from Korea University, Seoul, has developed an easy and scalable technique for growing graphene, and have synthetically produced high-quality, multi-layer, wafer-scale graphene on silicon substrates. This latest breakthrough paves the way for using graphene in silicon microelectronics on a commercial scale. The study has been published in AIP Publishing’s journal Applied Physics Letters.
Wafer-scale (4 inch in diameter) synthesis of multi-layer graphene using high-temperature carbon ion implantation on nickel / SiO2 /silicon. CREDIT: J.Kim/Korea University, Korea


Full story: http://www.azonano.com/news.aspx?newsID=33336

Wafer-scale synthesis of multi-layer graphene by high-temperature carbon ion implantation

Janghyuk Kim, Geonyeop Lee and Jihyun Kim
Appl. Phys. Lett. 107, 033104 (2015); http://dx.doi.org/10.1063/1.4926605



Schematics of (a) E-beam evaporation of Ni on SiO2/Si substrate, (b) carbon ion implantation into Ni, (c) post-implantation activation annealing at various conditions, and (d) graphene synthesized on both sides of Ni layer. (e) Diagram of the post-implantation activation annealing conditions.
Citation: Appl. Phys. Lett. 107, 033104 (2015); http://dx.doi.org/10.1063/1.4926605

 
We report on the synthesis of wafer-scale (4 in. in diameter) high-quality multi-layer graphene using high-temperature carbon ion implantation on thin Ni films on a substrate of SiO2/Si. Carbon ions were bombarded at 20 keV and a dose of 1 × 1015 cm−2 onto the surface of the Ni/SiO2/Si substrate at a temperature of 500 °C. This was followed by high-temperature activation annealing (600–900 °C) to form a sp2-bonded honeycomb structure. The effects of post-implantation activation annealing conditions were systematically investigated by micro-Raman spectroscopy and transmission electron microscopy. Carbon ion implantation at elevated temperatures allowed a lower activation annealing temperature for fabricating large-area graphene. Our results indicate that carbon-ion implantation provides a facile and direct route for integrating graphene with Si microelectronics
Researchers have a method to synthesize graphene at the wafer-scale. Their work, published in Applied Physics Letters, makes large-area synthesis of graphene compatible with silicon microelectronics. In the last decade, graphene has been intensively studied for its unique optical, mechanical, electrical and structural properties. The one-atom-thick carbon sheets could revolutionize the way electronic devices are manufactured and lead to faster transistors, cheaper solar cells, new types of sensors and more efficient bioelectric sensory devices. As a potential contact electrode and interconnection material, wafer-scale graphene could be an essential component in microelectronic circuits, but most graphene fabrication methods are not compatible with silicon microelectronics, thus blocking graphene's leap from potential wonder material to actual profit-maker. “For integrating graphene into advanced silicon microelectronics, large-area graphene free of wrinkles, tears and residues must be deposited on silicon wafers at low temperatures, which cannot be achieved with conventional graphene synthesis techniques as they often require high temperatures,” explained Professor Kim Jihyun of Korea University. Read more from Asian Scientist Magazine at: http://www.asianscientist.com/2015/08/tech/korea-wafer-scale-graphene-silicon-microelectronics/

Sunday, July 12, 2015

Chalmers show Graphene-based film that be used for efficient cooling of electronics

Researchers at Chalmers University of Technology have developed a method for efficiently cooling electronics using graphene-based film. The film has a thermal conductivity capacity that is four times that of copper. Moreover, the graphene film is attachable to electronic components made of silicon, which favours the film’s performance compared to typical graphene characteristics shown in previous, similar experiments.



Graphene-based film on an electronic component with high heat intensity. Image: Johan Liu

Electronic systems available today accumulate a great deal of heat, mostly due to the ever-increasing demand on functionality. Getting rid of excess heat in efficient ways is imperative to prolonging electronic lifespan, and would also lead to a considerable reduction in energy usage. According to an American study, approximately half the energy required to run computer servers, is used for cooling purposes alone.



A couple of years ago, a research team led by Johan Liu, professor at Chalmers University of Technology, were the first to show that graphene can have a cooling effect on silicon-based electronics. That was the starting point for researchers conducting research on the cooling of silicon-based electronics using graphene.

“But the methods that have been in place so far have presented the researchers with problems”, Johan Liu says. “It has become evident that those methods cannot be used to rid electronic devices off great amounts of heat, because they have consisted only of a few layers of thermal conductive atoms. When you try to add more layers of graphene, another problem arises, a problem with adhesiveness. After having increased the amount of layers, the graphene no longer will adhere to the surface, since the adhesion is held together only by weak van der Waals bonds."

“We have now solved this problem by managing to create strong covalent bonds between the graphene film and the surface, which is an electronic component made of silicon,” he continues.

The stronger bonds result from so-called functionalisation of the graphene, i.e. the addition of a property-altering molecule. Having tested several different additives, the Chalmers researchers concluded that an addition of (3-Aminopropyl) triethoxysilane (APTES) molecules has the most desired effect. When heated and put through hydrolysis, it creates so-called silane bonds between the graphene and the electronic component (see picture).

Moreover, functionalisation using silane coupling doubles the thermal conductivity of the graphene. The researchers have shown that the in-plane thermal conductivity of the graphene-based film, with 20 micrometer thickness, can reach a thermal conductivity value of 1600 W/mK, which is four times that of copper.

“Increased thermal capacity could lead to several new applications for graphene,” says Johan Liu. "One example is the integration of graphene-based film into microelectronic devices and systems, such as highly efficient Light Emitting Diodes (LEDs), lasers and radio frequency components for cooling purposes. Graphene-based film could also pave the way for faster, smaller, more energy efficient, sustainable high power electronics."

Facts about the research:

The results were recently published in the renowned journal Advanced Functional Materials:


The research was conducted in collaboration with Shanghai University in China, Ecole Centrale Paris and EM2C – CNRS in France, and SHT Smart High Tech in Sweden.


Chalmers University of Technology conducts research and offers education in technology, science, shipping and architecture with a sustainable future as its global vision. Chalmers is well-known for providing an effective environment for innovation and has eight priority areas of international significance – Built Environment, Energy, Information and Communication Technology, Life Science Engineering, Materials Science, Nanoscience and Nanotechnology, Production, and Transport. 

Graphene Flagship, an FET Flagship initiative by the European Commission, is coordinated by Chalmers. Situated in Gothenburg, Sweden, Chalmers has 10,300 full-time students and 3,100 employees.